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1068 Commits

Author SHA1 Message Date
Stanislav Shwartsman
6f0db17b08 fixed #DB on rpeat instructions 2009-10-30 09:13:19 +00:00
Stanislav Shwartsman
98b51805d5 updates for Bochs debugger 2009-10-29 15:49:50 +00:00
Stanislav Shwartsman
78e4b3d616 split SSE move instructions 2009-10-24 11:17:51 +00:00
Stanislav Shwartsman
b80249dfcb added PANIC for unsupported VMX feature 2009-10-22 13:33:13 +00:00
Stanislav Shwartsman
da4722e257 optimize sr params 2009-10-16 18:29:45 +00:00
Stanislav Shwartsman
5909ef1494 loading of null segment with RPL != 0 2009-10-12 20:50:14 +00:00
Stanislav Shwartsman
6d6bf4a65e code optimization for future 2009-10-08 18:07:50 +00:00
Stanislav Shwartsman
d9f701ddb0 LSL/LAR fixed in 64-bit mode 2009-10-02 16:09:08 +00:00
Stanislav Shwartsman
85f1004ce0 implemented TPR shadow feature for VMX 2009-09-30 05:57:21 +00:00
Stanislav Shwartsman
d273ae14b0 rework in paging.cc 2009-09-26 06:06:35 +00:00
Stanislav Shwartsman
8e3276cf14 split opcodes by ModC0 2009-08-22 11:47:42 +00:00
Stanislav Shwartsman
8a95120e12 deprecate --enable-vme option, now it will be supported iff CPU_LEVEL >= 5 (like in real life) 2009-08-10 15:44:50 +00:00
Stanislav Shwartsman
66c4654418 segment desriptor 'A' bit handling fixes 2009-07-27 05:52:28 +00:00
Stanislav Shwartsman
f2d84e1604 Fixed VMREAD/VMWRITE of 16-bit vmx fields 2009-07-21 11:56:26 +00:00
Stanislav Shwartsman
733491871d copy/paste typo fix 2009-06-15 15:10:05 +00:00
Stanislav Shwartsman
cd445195dd cleanup configure options. All paging related stuff is now automatically set/unset according to cpu-level option. 
Related configure options (--enable-pae, --enable-mtrr, --enable-global-pages, --enable-large-pages) are deprecated.
Less configure options - less configure problems :)
 2009-06-15 09:30:56 +00:00
Stanislav Shwartsman
716465fb16 bugfix: Half-baked VMX Link Pointer state checking. 2009-06-06 10:21:49 +00:00
Stanislav Shwartsman
03ba2ec988 implement pdptr checks in legacy PAE mode 2009-05-31 07:49:04 +00:00
Stanislav Shwartsman
222129db4b Rewritten long mode page walk - large code cleanup and few bugfixes 2009-05-30 15:09:38 +00:00
Stanislav Shwartsman
3d7bbf4356 fixed VMXON pointer concept 2009-05-28 08:26:17 +00:00
Stanislav Shwartsman
847179fd13 mtrr reverved bits check 2009-05-21 13:25:30 +00:00
Stanislav Shwartsman
efc413d2b4 VMX fixes 2009-05-21 10:39:40 +00:00
Stanislav Shwartsman
aac70fdf25 faster vmenter/vmexit 2009-05-03 13:02:14 +00:00
Stanislav Shwartsman
78418c6a74 removed cr1 from cpu 2009-05-01 09:32:46 +00:00
Stanislav Shwartsman
89f057ae7b x87 fix 2009-04-27 14:00:55 +00:00
Stanislav Shwartsman
012b3a2e89 Eliminate code duplication 2009-04-14 13:43:21 +00:00
Stanislav Shwartsman
e0833381d5 Fixed priority between #NP and #GP 2009-04-14 09:23:36 +00:00
Stanislav Shwartsman
4fc66aab31 Fixes for compilation by Visual Studio 2008 2009-04-07 16:12:19 +00:00
Stanislav Shwartsman
9d4c24b6a3 Split instruction 32/64 2009-04-06 18:44:28 +00:00
Stanislav Shwartsman
153f86b1a8 save/restore mwait status correctly 2009-04-05 19:38:44 +00:00
Stanislav Shwartsman
fcb51dc168 oops, this break max_instr_count feature 2009-03-26 10:24:10 +00:00
Stanislav Shwartsman
043be27c2c M$ comilerr can't optimize very good functions with long_jmp inside 2009-03-26 09:28:49 +00:00
Stanislav Shwartsman
e5be60be64 Fixed lazy flags bug I added in one of my prev merges 
ICACHE code reorganization
 2009-03-22 21:12:35 +00:00
Stanislav Shwartsman
c3392488b5 reorganize cpu debugger support, less function, faster code 2009-03-17 19:40:26 +00:00
Stanislav Shwartsman
4470c6a1c8 make ICACHE always enabled option and deprecate it in the configure script 
Trace cache still can be turned off
 2009-03-13 18:48:08 +00:00
Stanislav Shwartsman
10c8d8ea33 improve lazy flags after ADD instruction 2009-03-13 18:26:10 +00:00
Stanislav Shwartsman
9417cbee63 - cpu optimizations 9remove redundant, add new) 2009-03-13 18:02:33 +00:00
Stanislav Shwartsman
9e723a044f - Added configure option to enable/disable A20 pin support. Disabling the 
A20 pin support slightly speeds up the emulation.

  - small code cleanup
 2009-03-10 16:28:01 +00:00
Stanislav Shwartsman
6fe0b40b44 move a20 handling into getHostAddr method of BX_MEM 2009-03-08 21:23:40 +00:00
Stanislav Shwartsman
6dac964b27 Two more prefix66 opcodes 2009-02-28 09:28:18 +00:00
Stanislav Shwartsman
b9de22961c minimize SSE tables, minor speedup in SSE code 2009-02-26 21:57:01 +00:00
Stanislav Shwartsman
2304f2abf1 reduce dependencies from CPU/APIC.H 2009-02-20 22:00:42 +00:00
Stanislav Shwartsman
78590cc6f2 remove redundant cpu->name variable 2009-02-20 17:05:03 +00:00
Stanislav Shwartsman
d01725b1e9 Fixed compilation error on MAC 2009-02-20 08:12:51 +00:00
Stanislav Shwartsman
1b72e66bb3 support for apic global disable 
separate between I/O apic and local apic
 2009-02-18 22:25:04 +00:00
Stanislav Shwartsman
87b705d036 Changes in lapicbase msr 2009-02-17 19:44:02 +00:00
Stanislav Shwartsman
3a1852ea23 take local APIC read/write access into CPU class from BX_MEM (needed for APIC virtualization later) 2009-02-17 19:20:47 +00:00
Stanislav Shwartsman
e8e699245f fix code duplication in cpu.h for eflags accessors 2009-02-13 20:09:56 +00:00
Stanislav Shwartsman
6003f52704 Fixed compilation error + x86-64 correctness fix 2009-02-09 19:46:34 +00:00
Stanislav Shwartsman
26fda0626d Added missed CR0 reserved bits #GP in long mode 2009-02-03 21:11:31 +00:00
Stanislav Shwartsman
592484408f Initial NMI virtualization for VMX, clean out CPU pins set/clear code 2009-02-03 19:17:15 +00:00
Stanislav Shwartsman
f6cb9e529f Fixes for VMX emulation 2009-02-02 18:59:44 +00:00
Stanislav Shwartsman
2378d31998 Fixes for DR6 handling 2009-02-01 20:47:06 +00:00
Stanislav Shwartsman
f8185a6bc6 Added Intel VMX emulation to Bochs CPU 2009-01-31 10:43:24 +00:00
Stanislav Shwartsman
a1c11c788b sepatate activity state from debug trap 2009-01-29 20:27:57 +00:00
Stanislav Shwartsman
aa982c27d8 move startup_SIPI code to CPU 2009-01-27 21:13:38 +00:00
Stanislav Shwartsman
0325c120b2 Separate PAUSE instruction from regular NOP 2009-01-27 20:29:05 +00:00
Stanislav Shwartsman
62005d4fd9 Minimize diff with VMX support branch 2009-01-23 09:26:24 +00:00
Stanislav Shwartsman
29a252b26e final version of exceptions cleanups/interface changes 2009-01-21 22:09:59 +00:00
Stanislav Shwartsman
e7ac62ac82 extensions for exception type for future 2009-01-20 21:28:43 +00:00
Stanislav Shwartsman
74b885d74b Updated instrumentation 
Simplified exception code
 2009-01-20 19:34:16 +00:00
Stanislav Shwartsman
c93d13d37b small cleanups 2009-01-20 18:15:25 +00:00
Stanislav Shwartsman
db098a1205 Fix dependencies of CPU code from disasm library 
Regent Makefile.in for CPU
 2009-01-19 19:01:03 +00:00
Stanislav Shwartsman
ef5df7c4a8 make functions from rdmsr and wrmsr - they will be reused in VMX 2009-01-19 18:08:38 +00:00
Stanislav Shwartsman
a396c8a1ce Rework SMM mess 2009-01-17 22:35:45 +00:00
Stanislav Shwartsman
cd367becd7 remove duplicate function 2009-01-17 18:56:25 +00:00
Stanislav Shwartsman
9929e6ed78 - updated FSF address 2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
e540ee75ca cleared external debugger configure stuff from configure script and makefile 2009-01-15 21:52:52 +00:00
Stanislav Shwartsman
0836545037 Merge io.cc and io_pro.cc (required for future VMX use) 2009-01-15 16:53:08 +00:00
Stanislav Shwartsman
836e9649d8 modify set cr0 functionality 2009-01-10 10:07:57 +00:00
Stanislav Shwartsman
6ea14b747c Fixed SEGFAULT with configurable MSRS 
fixed osdep issue in win32 enhanced debugger module
 2009-01-08 18:07:44 +00:00
Stanislav Shwartsman
69153fc532 added enum for memory types 2009-01-03 20:04:03 +00:00
Stanislav Shwartsman
3cd5ab1041 added phy addr check 2009-01-02 13:21:48 +00:00
Stanislav Shwartsman
e182e74a4d Added ability to define user MSRs spec for emulated CPU 2008-12-28 20:30:48 +00:00
Stanislav Shwartsman
a794bef607 optimize invlpg for split large pages 2008-12-19 16:03:25 +00:00
Stanislav Shwartsman
a2e07ff971 - Removed --enable-guest2hos-tlb configure option. The option will be 
always enabled for any Bochs configuration.
 2008-12-11 21:19:38 +00:00
Stanislav Shwartsman
35487c3ebd get/set_segment_ar_data prepared for future reuse in other than SMM mode 2008-12-06 18:52:02 +00:00
Stanislav Shwartsman
15fa42963f get/set_segment_ar_data prepared for future reuse in other than SMM mode 2008-12-06 18:01:00 +00:00
Stanislav Shwartsman
d7fa44d270 optimize code access detection 2008-12-05 22:34:42 +00:00
Stanislav Shwartsman
098308dd9f some variable renames + comp warn fix 2008-12-01 19:06:14 +00:00
Stanislav Shwartsman
f69ac41e59 added infrastructure for init disable 2008-12-01 18:54:24 +00:00
Stanislav Shwartsman
e402062499 -Fixes for INVLPG 2008-11-29 19:28:10 +00:00
Stanislav Shwartsman
cde9595e86 implement cluster addressing model in local apic 
deliver INIT IPI through local apic
 2008-11-20 18:44:15 +00:00
Stanislav Shwartsman
577c8c7969 another way to do the same optimization 2008-10-08 20:40:26 +00:00
Stanislav Shwartsman
17040303f7 Optimization of repeat string 2008-10-08 20:15:37 +00:00
Stanislav Shwartsman
ab716f62aa inline prepareMMX method 2008-10-08 11:14:35 +00:00
Stanislav Shwartsman
67fae3ab41 Fixed compilation 2008-10-06 20:06:30 +00:00
Stanislav Shwartsman
2066d8b594 Fixed compilation issues 2008-10-06 17:50:06 +00:00
Stanislav Shwartsman
fb71c07b15 Fixes for MONITOR/MWAIT - the feature is still EXPERIMENTAL ONLY ! 2008-10-03 16:53:08 +00:00
Stanislav Shwartsman
c009e87a81 Remove external debugger interface: 
- it is closed source (!!!)
 - we have very nice replacement now
 2008-10-01 09:44:40 +00:00
Stanislav Shwartsman
bc381e51da very small cleanups 2008-09-19 19:18:57 +00:00
Stanislav Shwartsman
db664c4012 more optimizations after fetchdecode 2008-09-16 20:57:16 +00:00
Stanislav Shwartsman
a9c77eb75d Try to optimize individual instructions after fetchdecode 2008-09-16 19:20:03 +00:00
Stanislav Shwartsman
7566faf948 A bit simplify FPU decoding 2008-09-16 18:28:53 +00:00
Stanislav Shwartsman
d57a211df9 Fixed handling of prefixes for EMMS 
Small FPU optimization
 2008-09-12 20:59:31 +00:00
Stanislav Shwartsman
f5ba90da55 Misaligned check small optimization 2008-09-08 15:45:57 +00:00
Stanislav Shwartsman
c1306f7d75 small non-significant speedups 2008-09-06 21:10:40 +00:00
Stanislav Shwartsman
b3b2f77675 Reduce size of Bochs static tables by changing from bx_bool (which is 32bit) to Bit8u 2008-09-06 18:21:29 +00:00
Stanislav Shwartsman
7145d240f4 Optimize system read using Guest2Host TLB 2008-09-06 17:44:02 +00:00
Stanislav Shwartsman
7a57ccd435 - Partially fixed x87 Underflow/Overflow (#P) unmasked responce 2008-09-02 19:46:55 +00:00
Stanislav Shwartsman
bdf25fa3ca Inexact Result (#P) unmasked responce 
CVS ----------------------------------------------------------------------
 2008-09-02 05:38:36 +00:00
Stanislav Shwartsman
398f80a214 - Fixed CALL FAR between legacy and 64-bit modes 2008-08-31 06:04:14 +00:00
Stanislav Shwartsman
79eb5efffa - Preliminary implementation of X86 IO breakpoints 2008-08-30 08:14:46 +00:00
Stanislav Shwartsman
b96f78dc0a Some kind of big change in fetchdecode tables invented in order to compress the tables for better host data cache utilization 2008-08-29 19:23:03 +00:00
Stanislav Shwartsman
a5a01c4b42 optimize LEAVE operation 2008-08-27 21:57:40 +00:00
Stanislav Shwartsman
d029823fb5 Fixed compilation error under --enable-smp 2008-08-24 17:29:17 +00:00
Stanislav Shwartsman
d0803ebd10 branch_16 optimizations 2008-08-23 22:27:58 +00:00
Stanislav Shwartsman
5e92a1642d Fixed compilation errors, added BX_ASSERT in paging.cc 2008-08-18 05:20:23 +00:00
Stanislav Shwartsman
56504e4a67 Add some missed eflags accessors and pay more attention for special ones 2008-08-16 21:06:56 +00:00
Stanislav Shwartsman
e2fa98b629 - Fixed TLB flush on CR3 change - flush all pages is CR4.PGE is OFF 2008-08-16 15:35:35 +00:00
Stanislav Shwartsman
dcb82ec4bf Optimize TLB flush methods 2008-08-13 21:51:54 +00:00
Stanislav Shwartsman
8ecea83f02 Fixed compilation error 2008-08-12 05:03:51 +00:00
Stanislav Shwartsman
70c7c5ceca Use LOAD_Eb approach to remove duplicated GbEb methods 2008-08-11 20:34:05 +00:00
Stanislav Shwartsman
a8adb36dc2 Implemented MOVBE Intel Atom(R) instruction 2008-08-11 18:53:24 +00:00
Stanislav Shwartsman
b61017e5b6 Split more opcodes using new LOAD technique 2008-08-10 21:16:12 +00:00
Stanislav Shwartsman
1da5943f1a More use of LOAD_Ex method 2008-08-10 19:34:28 +00:00
Stanislav Shwartsman
0d90ab0478 Completely new way to handle LD+OP cases - allows to significantly reduce number of BX_CPU_C methods 2008-08-09 21:05:07 +00:00
Stanislav Shwartsman
5dd02b26e3 Make even more efficient RmAddr calculation - good optimizing compiler could make more efficient code than it was before 2008-08-08 09:22:49 +00:00
Stanislav Shwartsman
bbf02a8bc5 More clean rewrite of the TLB access bits 2008-08-07 22:14:38 +00:00
Stanislav Shwartsman
6398ebb1d4 First step of access bits cleanup and optimization - no perf gain yet 2008-08-03 19:53:09 +00:00
Stanislav Shwartsman
2e8bc558d1 Speedup SSE by introducing read/write_virtual_dqword_aligned methods 2008-08-02 10:16:47 +00:00
Stanislav Shwartsman
67f302352c Implement PDPE cache to support faster PAE paging tranlsation 2008-08-01 13:28:44 +00:00
Stanislav Shwartsman
59514dcbfb Fixed compilation err typo 2008-07-26 20:50:20 +00:00
Stanislav Shwartsman
c388f48fff - Fixed memory bug in tripple fault detection 
- Implement 16-byte memory accessor for SSEx - speedup SSE code emulation by >20%
 2008-07-26 14:19:06 +00:00
Stanislav Shwartsman
85686db212 Removed unused methods 2008-07-13 14:22:43 +00:00
Stanislav Shwartsman
3f5efb6475 Remove more duplicated methods 2008-07-13 10:06:07 +00:00
Stanislav Shwartsman
0127415ba6 Clear some duplicated arithmetic opcodes - difference only in operands order 2008-07-13 09:59:59 +00:00
Stanislav Shwartsman
c1f308d80d Push error code if segment violation occurs when pushing arguments into a new stack 2008-06-25 02:28:31 +00:00
Stanislav Shwartsman
a6fda9a971 Instrumentation code updated, some PANIC messages fixed 2008-06-23 02:56:31 +00:00
Stanislav Shwartsman
678ac970aa Reorganize ctrl_xfer8.cc code, allows to inline branch32 method 2008-06-22 03:45:55 +00:00
Stanislav Shwartsman
98581c44d3 Fixed compilation when use64 is disabled 2008-06-13 08:17:52 +00:00
Stanislav Shwartsman
1a355e270e split io repeat methods by address size 2008-06-12 20:12:25 +00:00
Stanislav Shwartsman
92568f7525 Faster 32-bit emulation wwith 64-bit enabled mode. 
~10% speedup byu optimization of 32-bit mem access
 2008-06-12 19:14:40 +00:00
Stanislav Shwartsman
607900dd4d very small cleeanup 2008-06-12 16:40:53 +00:00
Stanislav Shwartsman
424f316e07 Fixed comment 2008-06-02 20:11:03 +00:00
Stanislav Shwartsman
7494b8823b - Support of AES CPU extensions, to enable configure with 
--enable-aes option
 2008-05-30 20:35:08 +00:00
Stanislav Shwartsman
d295371450 - Correctly handle segment a byte in BIG real mode 2008-05-26 21:46:39 +00:00
Stanislav Shwartsman
77fbc2c187 Fixed LAR/LSL in 64-bit mode, compilation error fixes 2008-05-25 15:53:29 +00:00
Stanislav Shwartsman
3619c0f6b4 Some changes to make x86-debugger feature working back 2008-05-23 17:49:46 +00:00
Stanislav Shwartsman
4e5d10d02e Code reorganization + small bug fixes in translate linear code 2008-05-19 18:10:32 +00:00
Stanislav Shwartsman
76fc10e3d4 Added ability to override exception class to TRAP (#DB) 2008-05-15 20:10:00 +00:00
Stanislav Shwartsman
d934190370 Fixed data type for cr3_masked 2008-05-11 19:58:41 +00:00
Stanislav Shwartsman
4a76bd2169 Fixed setting of reserved bits in CR3 register 2008-05-11 19:36:06 +00:00
Stanislav Shwartsman
d3528cccd6 Style fixes - name convention for push to new stack methods 2008-05-10 20:35:03 +00:00
Stanislav Shwartsman
ec1ff39a5f Splitted memory access methods for 32 and 64-bit code. 
The 64-bit code got >10% speedup, the 32-bit code also got about 2% because laddr cacluation optimization
 2008-05-10 18:10:53 +00:00
Stanislav Shwartsman
3634c6f892 Compress FPU tag word 2008-05-10 13:34:47 +00:00
Stanislav Shwartsman
8e7cf2bf3a - Fixed CPUID 
- Merged jmp_call_gate16 and jmp_call_gate32 to single function
 2008-05-09 18:09:04 +00:00
Stanislav Shwartsman
5da460b6dc Clear segment descriptor cache when loading null selector 2008-05-06 19:45:17 +00:00
Stanislav Shwartsman
f642b57a54 Lazy falgs optimizations by Darek Mihocka 2008-05-04 15:07:08 +00:00
Stanislav Shwartsman
ed4be45a8b Split shift/rotate opcodes in 32-bit mode and 64-bit mode 2008-05-02 22:47:07 +00:00
Stanislav Shwartsman
f5780a5f5c Hide some BX_MEM_C variables 
Optimize resolve16 methods - by reducing their amount again - reduce chance for misspredictin
 2008-05-01 20:08:37 +00:00
Stanislav Shwartsman
81deffd65d More fetchdecode fixes 2008-04-30 21:32:33 +00:00
Stanislav Shwartsman
06c6ac0060 - Fixed effective address wrap in 64-bit mode with 32-bit address size 
- Fixed SMSW instruction in 32-bit and 64-bit modes
 2008-04-28 18:18:08 +00:00
Stanislav Shwartsman
67e534832b Remove from CPU reference to MEM object - it is only one and could be static 2008-04-27 19:49:02 +00:00
Stanislav Shwartsman
e86102eea5 Fixed 2nd dword of 64-bit descriptor check 2008-04-26 19:41:28 +00:00
Stanislav Shwartsman
9047c9be96 Support for reserved bits checking in paging 
Check for page is in DTLB before invalidating by INVLPG
 2008-04-25 20:08:23 +00:00
Stanislav Shwartsman
64f2489afb Correctly implement opcode group G11 i.e. instructions C6 and C7 should @UD when modrm nnn field != 0 (1st instr in the group 2008-04-24 21:52:28 +00:00
Stanislav Shwartsman
d24a274909 Eliminate can_pop function - with bugfix in retf 2008-04-23 17:25:21 +00:00
Stanislav Shwartsman
d9bf2b8453 Small emulation speed optimization 2008-04-19 22:29:44 +00:00
Stanislav Shwartsman
bdaef81603 Added debugger memory trace functionality. Enable by 'trace-mem on' command 2008-04-19 13:21:23 +00:00
Stanislav Shwartsman
cacec881cf Fixed param type for set_TSC 2008-04-18 18:37:29 +00:00
Stanislav Shwartsman
15e9dca062 - support 64-bit write to MSR_TSC using WRMSR instruction 
- fixed save/restore param type for async_event
- fixed setting of reserved bits in upper part of CR4 in 64-bit mode
 2008-04-18 18:32:40 +00:00
Stanislav Shwartsman
892fa99c6f - prefetch hint should be NOP when use in register mode 
- #GP when trying to set reserved bits of CR4_HI in 64-bit mode
- #GP when trying to set reserved bits of EFER MSR
- clear upper part of RSI/RDI when executing rep instructions with 32-bit asize
  even if no repeat iterations were executed (because of RCX=0 for example)
- write SYSENTER_EIP_MSR and SYSENTER_ESP_MSR as 64-bit when x86_64 supported
- set MSR_FMASK reset value
- MSR_FMASK should be 32-bit only
- check for fetch permissions when doing ITLB lookup
- #GP when trying to write non-canonical address to MSR_CSTAR or MSR_LSTAR
- correct repeat instructions timing
- mark TSS busy in TR after it is loaded
 2008-04-16 16:44:06 +00:00
Stanislav Shwartsman
4c26043969 Fixed 3rd fault detection (shutdown condition) 2008-04-15 17:22:11 +00:00
Stanislav Shwartsman
fab4042cad SYSENTER/SYSEXIT in long mode 2008-04-15 14:41:50 +00:00
Stanislav Shwartsman
a98cd9f781 small cpu code reorganization 2008-04-08 17:58:56 +00:00
Stanislav Shwartsman
a33d8c6008 Make get_laddr and get_segment_base BX_SMF 2008-04-08 05:36:30 +00:00
Stanislav Shwartsman
a851cfd8f0 Re-implemented modebp debugger function in simple and more clean way 2008-04-07 19:59:53 +00:00
Stanislav Shwartsman
fea49bb270 Fixed linear address wrap in legacy (not long64) mode 2008-04-07 18:39:17 +00:00
Stanislav Shwartsman
77d91d59aa Inline prepare_SSE and prepare_XSAVE functions 2008-04-06 18:00:20 +00:00
Stanislav Shwartsman
90f1973bef Removed BX_USE_TLB - TLB is always used, only Guest2HostTLB is optional feature 
Use Guest2HostTLB in prefetch code for IFETCHES - speedup above 3%
 2008-04-05 20:41:00 +00:00
Stanislav Shwartsman
1bdddc1f78 Split SHRD/SHLD instructions 2008-04-05 19:08:01 +00:00
Stanislav Shwartsman
5826e2843a Inline pop/push functions 
Store only single byte of opcode in b1() - speedup shift instructions
Code cleanups
 2008-04-05 17:51:55 +00:00
Stanislav Shwartsman
2aaafa76a2 Reorganize fetchdecode tables with another level of redirection - a leap toward future improvements 
Currently no speedup and no slowdown - about the same results on my Bochs benchmarking
A lot of code reorganization in fetchdecode
 2008-04-04 22:39:45 +00:00
Stanislav Shwartsman
62e3728591 preparations for future optimizations - not necessary speedupo now 2008-04-03 17:56:59 +00:00
Stanislav Shwartsman
e91409704f Convert EFER to val32 register, similar to other control registers 2008-03-31 20:56:27 +00:00
Stanislav Shwartsman
3f2487a0af Enabled tracing cross repeated instructions 2008-03-31 18:53:08 +00:00
Stanislav Shwartsman
08f958f458 Fixed pageWriteStampTable to handle BIOS code as well - increased the table to all 4G instead of allocated memory size 
Avoid checking of pageWriteStamp in the heart of cpu loop with trace cache - now decWriteStamp will post stopTraceExecution event if it hits code page
 2008-03-29 21:01:25 +00:00
Stanislav Shwartsman
7aef2d5892 Inline get_ZF/SF/PF lazy flags functions - gcc didn't get them inline before 2008-03-29 18:44:13 +00:00
Stanislav Shwartsman
f3a91710e4 Split access_linear to access_read_linear and access_write_linear 2008-03-29 18:18:08 +00:00
Stanislav Shwartsman
e48b398bee Add NIL register and simplify more BxResolve work 2008-03-29 09:34:35 +00:00
Stanislav Shwartsman
94f30955be Fixed compilation error 2008-03-25 16:46:39 +00:00
Stanislav Shwartsman
9fcbf28cea Removed can_push method - normal memory accesses will be used instead. 
Fixed reset value of TR.TYPE
 2008-03-24 22:13:04 +00:00
Stanislav Shwartsman
167c7075fb Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code 2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
7e490699d4 Removing hooks for not-implemented SSE4A from the Bochs code. 2008-03-21 20:04:42 +00:00
Stanislav Shwartsman
64bfbb32b5 Inline icache lookup code - speedup of 3% according to my measurements 2008-03-06 20:22:24 +00:00
Stanislav Shwartsman
65df050a21 Fixed compilation warning 2008-03-03 15:34:03 +00:00
Stanislav Shwartsman
946b7a369d Added const to fetchPtr in cpu functions 2008-03-03 15:16:46 +00:00
Stanislav Shwartsman
2172e96654 small trace/iacache cleanups, always allow speculative tracing for trace cache 2008-03-03 14:35:36 +00:00
Stanislav Shwartsman
405fcfd75d Reorganize 3-byte opcode tables - bigger tables but easier to maintain them 2008-02-29 03:02:03 +00:00
Stanislav Shwartsman
a459a64f3e whispace, tab2space, indent, dos2unix and other cleanups 2008-02-15 22:05:43 +00:00
Stanislav Shwartsman
cdcd7522aa Added RIP to the GPR register file as lst register 
This allowed to optimize (read - remove) two more BxResolve methods in 64-bit mode
+ Some white space cleanup
 2008-02-15 19:03:54 +00:00
Stanislav Shwartsman
4fc0df26e8 a bit optimize and simplify x87 decoding 2008-02-14 18:59:41 +00:00
Stanislav Shwartsman
ae86ad28a0 Finalize XSAVE/XRSTOR instructions 2008-02-13 22:25:24 +00:00
Stanislav Shwartsman
457152334e step2 in XSAVE implementation 2008-02-13 16:45:21 +00:00
Stanislav Shwartsman
8615022962 Added first stubs for XSAVE/XRESTOR implementation 
Disassemble XSAVE/XRSTOR instructions (4 instructions)
Update CHANGES - a bit speculatively
 2008-02-12 22:41:39 +00:00
Stanislav Shwartsman
8d7410a852 Canonical check have higher priority than #AC check 2008-02-11 20:52:10 +00:00
Stanislav Shwartsman
063d896226 Optimization in 16-bit resolve functions 
Fixes for hosts which can't support misaligned memory access
 2008-02-07 20:43:13 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
1a55fce072 remove staruct for eflags and use single 32-bit variable 2008-01-29 22:26:29 +00:00
Stanislav Shwartsman
37fbb82baa Cleanups. Move bxInstruction_c definition to separate file instr.h 2008-01-29 17:13:10 +00:00
Stanislav Shwartsman
7b80c5f481 I merged and succeded to remove some similar execution functions - less code, less chance for branch misprediction 2008-01-25 19:34:30 +00:00
Stanislav Shwartsman
9ec2c87aaa cleanups and optimizations 2008-01-22 16:20:30 +00:00
Stanislav Shwartsman
192f398b46 removed --enable-magic-breakpoint configure option - it is enabled by default if Bochs internal debugger compiled in. Also it always possible to switch magic break off by .bochsrc option 2008-01-21 21:36:58 +00:00
Stanislav Shwartsman
63d8d50cfc code cleanup 2008-01-20 20:11:17 +00:00
Stanislav Shwartsman
8c9de8b4db speculative tracing on fetchdecode level 2008-01-18 09:36:15 +00:00
Stanislav Shwartsman
9e53b71a55 Segment base in not long mode should only 32-bit 2008-01-14 19:03:50 +00:00
Stanislav Shwartsman
c6fd4ebf94 Split CALL_Ev and JMP_Ev methods 2008-01-12 16:40:38 +00:00
Stanislav Shwartsman
77b4b70b9b oops, revert incorrectly merged change 2008-01-10 20:32:23 +00:00
Stanislav Shwartsman
1f4608cd84 Fix for implemened 3dnow instuctions (most of them are not implemented) 2008-01-10 20:26:49 +00:00
Stanislav Shwartsman
d9984bb3a1 Eliminate BxResolve call from the heart of cpu loop and move into instructions that really require this calculation. Yes, it blows the code of EVERY CPU method but it has >15% speedup ! 2008-01-10 19:37:56 +00:00
Stanislav Shwartsman
a9e001bd30 Optimize short traces 2008-01-05 10:21:25 +00:00
Stanislav Shwartsman
eee1a9030d a bit simplify and optimize shift instructions 
print failed segment info in check_cs - more debug info
 2007-12-30 20:16:35 +00:00
Stanislav Shwartsman
d891f0d8ec Fixed more VC2008 warnings - hopefully last ones 2007-12-30 17:53:12 +00:00
Stanislav Shwartsman
79fc57dec8 Fixed more VCPP2008 warnings 2007-12-26 23:07:44 +00:00
Stanislav Shwartsman
c3c9c40674 Move MaxFetch calculation into fetchdecode - simplify the logic 2007-12-22 17:17:40 +00:00
Stanislav Shwartsman
e9a148f9c4 lmost last instruction split -> CMOV in 16/32 bit modes 2007-12-21 18:24:19 +00:00
Stanislav Shwartsman
a93b0afdbe Merge page split detection method suggested by Darek Mihocka 2007-12-21 10:33:39 +00:00
Stanislav Shwartsman
5d4e32b8da Avoid pointer params for every read_virtual_* except 16-byte SSE and 10-byte x87 reads 2007-12-20 20:58:38 +00:00
Stanislav Shwartsman
b516589e4e Changes in write_virtual_* and pop_* functions -> avoid moving parameteres by pointer 2007-12-20 18:29:42 +00:00
Stanislav Shwartsman
c9932e97eb Fixes in resolve.cc -> reduce amount of resolve functions even more 2007-12-18 21:41:44 +00:00
Stanislav Shwartsman
fe2e0525da More optimization for string instructions 2007-12-17 19:52:01 +00:00
Stanislav Shwartsman
0af87ab63b Split string instructions according to the address size - simpler and faster 2007-12-17 18:48:26 +00:00
Stanislav Shwartsman
a545bf63ce push_64 and pop_64 could happen only in 64-bit mode 2007-12-16 21:40:44 +00:00
Stanislav Shwartsman
46366b5064 Speedup simulation by eliminating CPL==3 check from read/write_virtual* functions 2007-12-16 21:03:46 +00:00
Stanislav Shwartsman
de5838ce80 cleanups and fixes for Immediate_IbIb of SSE4A 2007-12-16 20:47:10 +00:00
Stanislav Shwartsman
1e843cb462 Decode SSE4A 
Rework immediate bytes decoding to make it faster
 2007-12-15 17:42:24 +00:00
Stanislav Shwartsman
3a6d714398 Split for JMP_Ew/Ed opcodes from Grp5 2007-12-14 23:15:52 +00:00
Stanislav Shwartsman
fd73390ca5 Split 64-bit CMOVcc opcode 2007-12-14 22:41:43 +00:00
Stanislav Shwartsman
903f6dea35 Split setCC functions - makes code faster and simpler 2007-12-14 21:29:36 +00:00
Stanislav Shwartsman
d9a59c7a1f Added ability to merge traces cross JCC branch instructions 
Makes traces longer -> emulation faster in average
 2007-12-14 20:41:09 +00:00
Stanislav Shwartsman
db69a25c36 Trace cache instrumentation methods 
Next step will be tracing cross non-taken branches
 2007-12-14 11:27:44 +00:00
Stanislav Shwartsman
adda3befd3 Trace cache optimization merged 2007-12-09 18:36:05 +00:00
Stanislav Shwartsman
ee465a7714 misaligned SSE support works only for loads 2007-12-09 17:40:23 +00:00
Stanislav Shwartsman
d54d537f81 One more step for lazy flags optimization 2007-12-06 16:57:59 +00:00
Stanislav Shwartsman
a835e3f8ff get_FLAG_Lazy not always returns 0/1 2007-12-05 06:27:01 +00:00
Stanislav Shwartsman
295a36ef58 2nd step of lazy flags optimization 2007-12-05 06:17:09 +00:00
Stanislav Shwartsman
88899cf617 Changes for lazy flags handling -> 1st stap in transition to new lazy flags handling by Darek Mihocka (www.emulators.com) 2007-12-04 19:27:23 +00:00
Stanislav Shwartsman
c58e95f611 Make hw breakpoint match check a function - normally it should be called from read/write_virtual as well 2007-12-03 20:49:24 +00:00
Stanislav Shwartsman
a0147fe055 Fixed bug prevented to boot Win98 2007-11-30 08:49:12 +00:00
Stanislav Shwartsman
1a55835155 Optimize lazy flags for MUL/IMUL 2007-11-29 21:45:10 +00:00
Stanislav Shwartsman
8cfd17202a some simple SSE code optimizations 2007-11-27 22:12:45 +00:00
Stanislav Shwartsman
c51888f43f Split last BxLockable opcodes -> this allows to eliminate mod==0xc0 check from fetchdecode of every instruction 
reduce ACPU.CC dependencies - now that file doesn't depend of CPU
 2007-11-25 20:22:10 +00:00
Stanislav Shwartsman
e51184c8cf Eliminate saving of RSP from heart of cpu_loop 
Now save RSP only where it is really required
 2007-11-24 14:22:34 +00:00
Stanislav Shwartsman
d0052dcd3e Removed unused setFlags code 2007-11-23 22:49:54 +00:00
Stanislav Shwartsman
1dbe51a2fb Split ENTER_IwBw function according to os32. Fixed ENTER/LEAVE in 64-bit mode 2007-11-22 17:33:06 +00:00
Stanislav Shwartsman
0a1063ad77 Split GvEv opcode groups 2007-11-21 22:36:02 +00:00
Stanislav Shwartsman
506dc3d963 Optimize 64-bit fetchdecode prefix handling 
Deparecated set_FLAG() method, setB_FLAG() method was used everywhere
Rename setB_FLAG to set_FLAG, so set_FLAG() will must receive 0/1 inly
 2007-11-20 23:00:44 +00:00
Stanislav Shwartsman
48650a70b4 Optimized alignment check 2007-11-20 21:22:03 +00:00
Stanislav Shwartsman
1af7010e50 Optimized memory access for 64-bit mode 
Starting convergence to new lazy flags scheme by Darek Mihocka (www.emulators.com). The new flags code is still being validated and perfected but I try to minimize the diff between 2 versionS
 2007-11-20 17:15:33 +00:00
Stanislav Shwartsman
30f42d74f1 make sreg index tables static in fetchdecode and remove them from init.cc/cpu.h 2007-11-18 21:07:40 +00:00
Stanislav Shwartsman
bcaba54489 Merge resolve functions for 32 and 64-bit 2007-11-18 19:46:14 +00:00
Stanislav Shwartsman
57d2d14865 Split POP_Ev opcodes 2007-11-18 18:49:19 +00:00
Stanislav Shwartsman
cdc9a09090 Split more opcodes 2007-11-18 18:24:46 +00:00
Stanislav Shwartsman
83f6eb6945 Changes copyrights for the files I wrote :) 
Also split EqId G1 group for x86-64
 2007-11-17 23:28:33 +00:00
Stanislav Shwartsman
613bad34ee split MOVZX/MOVSX opcodes 2007-11-17 18:29:00 +00:00
Stanislav Shwartsman
5ec15df46d Split more opcodes EbIb opcodes 2007-11-17 18:08:46 +00:00
Stanislav Shwartsman
d5a58e1df2 Split more opcodes - G3 group 2007-11-17 16:20:37 +00:00
Stanislav Shwartsman
d9e58bd598 split11b on opcode tables level - split almost eevery splittable instruction 
will be continued
 2007-11-17 12:44:10 +00:00
Stanislav Shwartsman
abe3f4c5c2 Split one more opcode 2007-11-16 21:43:23 +00:00
Stanislav Shwartsman
393018cdf8 More split11b 2007-11-16 17:45:58 +00:00
Stanislav Shwartsman
351244d1ea Rename splitmod11b methods 2007-11-16 08:30:22 +00:00
Stanislav Shwartsman
db02731cbf Replace BxAnother attribute in fetchdecode by table lookup like it is done in disasm. This is done in preparation to feature huge fetchdecode change - all fethdecode tables will be duplicated and made separatate table for ModC0 and others. 
So ALL instructions will emjoy SplitMod11b automatically (if they want).
After splitting ALL instruction I hope to get 20% speedup at least.
 2007-11-15 17:57:56 +00:00
Stanislav Shwartsman
0fa82afe1f Bugfix and optimize BxResolve calls - bugfix in 64-bit mode 2007-11-13 17:30:54 +00:00
Stanislav Shwartsman
edfff23ca0 Split JCC methods to 16 different methods per branch condition 2007-11-12 18:20:15 +00:00
Stanislav Shwartsman
aed6640ef4 speedup JCC for 64-bit -> separate JZ/JNZ for single faster methods 2007-11-11 21:26:10 +00:00
Stanislav Shwartsman
7648101f28 Optimize metainfo data - ilen() and b1() methods get speedup 2007-11-11 21:14:24 +00:00
Stanislav Shwartsman
eea5023da8 small simplification for fetchdecode 2007-11-11 20:56:22 +00:00
Stanislav Shwartsman
9dc471bbe5 Simplify Guest2HostTLB code 
Fixed APIC CPUID bit
 2007-11-11 20:44:07 +00:00
Stanislav Shwartsman
5fd21257de Remove qick TLBN invalidation code - it actually only could slow down emulation 2007-11-09 21:14:56 +00:00
Stanislav Shwartsman
2653d54e96 split 32-bit modermdata variable in BxInstruction_c to 4 Bit8u variables 
this way it is possible to save shifts and masking when accessing modrm fields
 2007-11-08 18:21:37 +00:00
Stanislav Shwartsman
2f5fa07af3 small speedups 2007-11-07 10:40:40 +00:00
Stanislav Shwartsman
44e49f2fe2 Fixed CPU state print in debug dump 2007-11-05 16:28:03 +00:00
Stanislav Shwartsman
e137560b14 Complete MONITOR/MWAIT implemntation (including monitoring of memory range) 
Fixed PANIC in read/write Cr/Dr - should #UD with unkown register used
 2007-11-01 18:03:48 +00:00
Stanislav Shwartsman
ce0e0287fb Naturally speedup repeat execution functions, fix TLB index calculations 2007-10-30 22:15:42 +00:00
Stanislav Shwartsman
a4e20e9d29 warnings fixed 2007-10-24 23:02:09 +00:00
Stanislav Shwartsman
6d7134ef99 Remove dump_cpu debugger function, CPI method and all related structures. 
Extended 'info' command in debugger to have all functionality of dump_cpu if needed. Also param tree print always could be used !
 2007-10-23 21:51:44 +00:00
Stanislav Shwartsman
292153b30e Fixed BranchImm cases in 64-bit mode 2007-10-22 17:41:41 +00:00
Stanislav Shwartsman
42fdd8a3a1 During Bochs benchmarking I figured out that hostasm actually slow down the emulation ... so remove this ugly code which also doesn't help :) 
speedup flags update for some instructions - idea was taken from DT patch by h.johansson
 2007-10-21 22:07:33 +00:00
Stanislav Shwartsman
28a5c6741c Fix SSE4 MOVNTDQA instruction - memory access must be always aligned 2007-10-20 17:03:33 +00:00
Stanislav Shwartsman
679110caa9 fixed push to new stack for long mode 2007-10-19 12:40:19 +00:00
Stanislav Shwartsman
0fc32d3c81 Fixed except_chk issue in more clean way - added 3 new methods for pushing to new, still not loaded stack 2007-10-19 10:14:33 +00:00
Stanislav Shwartsman
4ec7f5df39 Optimize access to IP (16 bit) - made IP register similar to GPR 2007-10-18 22:44:39 +00:00
Stanislav Shwartsman
e9801ef501 Support for restore cpu (and any other device from bochs root) from debugger 2007-10-14 19:04:51 +00:00
Stanislav Shwartsman
082eb05b6b First step to fully configurable CPUID 
- put CPUID functions data into array, in future we could load this array from configure file
 - cpuid initialize function is more flexible now but still reuire some work
 2007-10-12 19:30:51 +00:00
Stanislav Shwartsman
8adbbcf17c Started first implementation of MONITOR/MWAIT 2007-10-11 21:29:01 +00:00
Stanislav Shwartsman
f6ed95785f added cpu state param - for future use and for dbg info 
started to move debugger to info bx_param interface -> info sse and info mmx commands modified
 2007-10-11 18:12:00 +00:00
Stanislav Shwartsman
82b7eaabd5 CLFLUSH do not fault when checking execute only segment 2007-10-10 21:48:46 +00:00
Stanislav Shwartsman
07739173f5 add --show-ips to all configs for future releases (it is not ON by default ?) 
Bit32u -> bx_phy_address in debugger and some other places
 2007-10-09 19:49:23 +00:00
Stanislav Shwartsman
dbb91069f4 Added SSE4_2 instructions emulation 2007-10-01 19:59:37 +00:00
Stanislav Shwartsman
071c5c1a26 A lot of changes but everything is really trivial. 
Make save/restore default feature, the configure option for save/restore removed from configure script and save/restore made available forever. All code now assume it is exists. Bochs save/restore tree previosly called "save_restore" renamed to "bochs" tree and it will be havily used everywhere, starting from save/restore and ending by various bochs debugger functions. I am going to rework debugger code to get rid of debug CPU access functions and use this "bochs" param tree instead
 2007-09-28 19:52:08 +00:00
Stanislav Shwartsman
91e6ca8d5c Implemented MTRR support 
Fixes in #PF exception priority
 2007-09-20 17:33:35 +00:00
Stanislav Shwartsman
0dc4badfbb Added SSE4A and SSE4_2 to disassembler 
Implemented POPCNT instruction
 2007-09-19 19:38:10 +00:00
Stanislav Shwartsman
70f513b07b Make efer control MSR separate register 2007-09-10 20:47:08 +00:00
Stanislav Shwartsman
412eeeeb7c Get crregs definition to separate file from cpu.h 2007-09-10 16:00:15 +00:00
Stanislav Shwartsman
016660698e just code cleanup, preparation for future 2007-08-31 18:09:34 +00:00
Stanislav Shwartsman
5ac1bb6646 rewrite page fault 2007-08-30 16:48:10 +00:00
Stanislav Shwartsman
895891b673 Implemented #AC check under configure option 
Fixes in misaligned SSE support
 2007-07-31 20:25:52 +00:00
Stanislav Shwartsman
38d1f39c77 Converted CR0 bits to one register similar to CR4 - a bit slower but helps with other features implemntation 2007-07-09 15:16:14 +00:00
Stanislav Shwartsman
5189cfbf10 SSE4 support 2007-04-19 16:12:21 +00:00
Stanislav Shwartsman
6c139a9c8c Define LIN and PHY address size in config.h 2007-04-14 10:05:30 +00:00
Stanislav Shwartsman
223b9fda0e Fixed RIP relative mode when in 32-bit address size 2007-04-09 21:15:00 +00:00
Stanislav Shwartsman
e26609fa97 Support for Intel LSS/LFS/LGS in 64-bit mode 
TODO: have both AMD and Intelk versions
 2007-04-09 20:28:15 +00:00
Stanislav Shwartsman
1ec33ec518 Correctly #UD on aliased instructions when no SSE2 is configured 2007-03-22 22:51:41 +00:00
Stanislav Shwartsman
b8787fd5a7 Some code cleanups and warning fixes 2007-03-14 21:15:15 +00:00
Stanislav Shwartsman
05ea111e1c Clean CPU debug methods in main cpu_loop 2007-03-06 17:47:18 +00:00
Stanislav Shwartsman
c24627c00f Implemented CLFLUSH instruction 
Set of minor fixes for correctness
 2007-01-28 21:27:31 +00:00
Stanislav Shwartsman
82607c4a35 Safety net - comment BX_WRITE_32BIT_REG macro - always use WRITE_32BIT_REGZ instead ! 2007-01-26 22:16:59 +00:00
Stanislav Shwartsman
8221fa6838 - Fixed zero upper 32-bit part of GPR in x86-64 mode 
- CMOV_GdEd should zero upper 32-bit part of GPR register even if the
    'cmov' condition was false !
 2007-01-26 22:12:05 +00:00
Stanislav Shwartsman
f8003098b1 Rename SSE4 to SSE3E to match intel docs. SSE4 coming later ;) 
Fixed "last prefix" for REX in 64-bit mode
 2007-01-25 19:09:41 +00:00
Stanislav Shwartsman
9db896d100 minor x86_64 fixes and cleanups 2007-01-12 22:47:21 +00:00
Stanislav Shwartsman
5c21f7821f Speed simulation between 3 to 5% by eliminating several checks from cpu loop. 
The checks were related to repeat instructions - handle them differently
 2007-01-05 13:40:47 +00:00
Volker Ruppert
e8cd2052c9 - improved gdbstub network efficiency (SF patch #1149659 by Avi Kivity) 
- reimplemented "enter debugger" in ask dialog for gdbstub
- X11 and wxWidgets ask dialog now show "Debugger" button for gdbstub
- indent mode changes
 2006-10-29 08:48:30 +00:00
Stanislav Shwartsman
650086669c Print 64-bit registers in 'info registers' command and in dump_regs 2006-10-21 22:06:39 +00:00
Stanislav Shwartsman
6c63e84d23 Fixed CR3 masking in long mode 
Added PANIC assertion of 32-bit physical address in PAE mode
cleanup
 2006-10-04 19:08:40 +00:00
Stanislav Shwartsman
65082e4a4f Handle granularity field for LDT 
Next step - fix code duplication with TSS
 2006-08-25 19:56:03 +00:00
Stanislav Shwartsman
3ce7764fce Fixes in 64-bit decoding 2006-08-11 17:23:36 +00:00
Stanislav Shwartsman
c7aa53d044 Fixed compilation error of extdb 2006-06-25 21:44:46 +00:00
Stanislav Shwartsman
070d782ec8 Move paddr_valid param of dbg_xlate_linear2phy method to return value. 
This is much easier to use.
 2006-06-17 12:09:55 +00:00
Stanislav Shwartsman
869f74b3ee Reduce amount of dbg_get_cpu calls (I would like to remove this function) and use save/restore power in debugger 2006-06-11 16:40:37 +00:00
Stanislav Shwartsman
6c3420a18b Add debug prints before any #GP excepion which only possible to be generated 2006-06-09 22:29:07 +00:00
Stanislav Shwartsman
286b89d763 Several x86-64 MSRs were not-initilized ! 
Fixed small save-restore bug in dma.cc
First step to make save-restore code look better (only several files processed for example)
 2006-05-28 17:07:57 +00:00
Stanislav Shwartsman
8b0df8e99b Merge SAVE_RESTORE branch to CVS 2006-05-27 15:54:49 +00:00
Stanislav Shwartsman
7c1767d17a Partial sync with save-restore 2006-05-27 14:02:34 +00:00
Stanislav Shwartsman
1acdb7f274 Simplify CPU loop and fix compilation error 2006-05-24 16:46:57 +00:00
Stanislav Shwartsman
73e1266cbe Add CR0 consistency checks and CS.L/CS.D consistency check 
Optimize icache writestamps - 2x more space to decrement for page-write-stamp
 2006-05-19 20:04:33 +00:00
Stanislav Shwartsman
7c2c9c41e8 Remove unused CPU vars 2006-05-15 18:00:55 +00:00
Stanislav Shwartsman
f4c7b4074e Support for x86-64 in x86 debugger (DR0-DR7) 2006-05-13 12:49:45 +00:00
Stanislav Shwartsman
fe644dfcbf - Code cleanup, remove x86-64 code from functions which cannot be called from x86-64 
- Fix PANIC multiple SSE prefix decoding (fetchdecode and disasm)
- More Bit32u -> bx_phy_address convert
- Lazy flags optimization
 2006-05-12 17:04:19 +00:00
Stanislav Shwartsman
91ada6c72c Separate RepeatSpeedups code in io.cc to stand-alone CPU methods 
FestRepINSW and FastRepOUTSW similar to that is done in string.cc
Done to simplify the code, it was just impossible to understand it.
 2006-05-07 20:45:42 +00:00
Stanislav Shwartsman
20b14aefa6 Fix in BSWAP 64-bit mode - allow to use additional R8-R15 registers 
Also fixed code duplication story with BSWAP instruction
 2006-05-07 18:58:47 +00:00
Stanislav Shwartsman
d69eba6c07 Split in/out instructions based on operand size 2006-05-07 18:27:36 +00:00
Stanislav Shwartsman
f93ab35357 Flush TLB for all CPUs when memory mapping information changed by system (A20 change, PAM write or similar events) 2006-04-29 17:21:49 +00:00
Stanislav Shwartsman
199c987ee3 Return back (modified) dbg_is_end_instr_bpoint method in cpu.cc 2006-04-29 16:14:47 +00:00
Stanislav Shwartsman
2889ed190c Removed icount guard for debugger. Implement STEPN debugger command using CPU_LOOP method capabilities 2006-04-29 09:27:49 +00:00
Stanislav Shwartsman
1a0b7ee1e3 I want to replace debugger ICOUNT guard by existent cpu_loop funtionality, first step to do that ... 2006-04-29 07:12:13 +00:00
Stanislav Shwartsman
4b86ae3917 Added new ar_byte function, might be used to fix code duplication and for save-restore 2006-04-25 15:35:26 +00:00
Stanislav Shwartsman
b2408c2fca Added assertion check CPU method, could be used for "debug mode" run with checking various assumptions before each instruction emulation 2006-04-25 14:42:57 +00:00
Stanislav Shwartsman
1939544bf8 move get_descriptor_l/get_descriptor_h methods to general cpu methods (were debugger only) 2006-04-23 17:16:27 +00:00
Stanislav Shwartsman
d972e4a4b7 Fixed CR3 restore in RSM instruction 
Added HALT state indication (actually make existant one working for single CPU)
 2006-04-10 19:05:21 +00:00
Stanislav Shwartsman
45f30f0a4c some code written to enter CPU to shutdown state. 
finally the shutdown handling should be done exactly as in VmWare - the GUI should ask user if the CPU should reset and go to HLT/IF=0 if user choosed to stay in shutdown mode.
CPU configure option reset-on-triple-failt should be extended to shutdown-reset=0|1
small code cleanups and fixes
 2006-04-07 20:47:32 +00:00
Stanislav Shwartsman
03eac64013 Added decoding of new SSE4 instructions (recently published in Intel docs) 
At least CPUID detects them correctly
The code is never tested (still) ! (but should work fine)
 2006-04-06 18:30:05 +00:00
Stanislav Shwartsman
f8c3968d42 Changes list made after CVS service crash: 
- Fixed critical bug in CPU code added with one of the prev commits
  - Disasm support for SSE4
  - Rename PNI->SSE3 everywhere in the code
  - Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
  - Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
  - Fixed ENTER and LEAVE instructions in x86-64 mode
  - Added ability to turn ON instruction trace, only GUI support is missed.
    Instruction trace could be enabled if Bochs was compiled with disasm
  - More changes Bit32u -> bx_phy_address
  - Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
  - Small code cleanup
  - Update CHANGES and user docs
 2006-04-05 17:31:35 +00:00
Stanislav Shwartsman
ae2ea87c43 More fixes for SMM 2006-03-29 18:08:13 +00:00
Stanislav Shwartsman
4fd9bd53c3 Change Bit32u -> bx_phy_address in memory 2006-03-28 16:53:02 +00:00
Stanislav Shwartsman
da3d26d7f4 Preliminary implemntation of SMM save statei 
Fixed fetchModeMask for load32bitOsStack
 2006-03-27 18:02:07 +00:00
Stanislav Shwartsman
5c3fba4399 Support access to SMRAM in memory object 
Cleanup in CPU code
 2006-03-26 18:58:01 +00:00
Stanislav Shwartsman
f347ab97bf Fixed CALL/JMP far through call gate 64 
Decode SWAPGS and RDTSCP instructions
Indent changes in fetchdecode
 2006-03-22 20:47:11 +00:00
Stanislav Shwartsman
d6f85c12f6 NMI support inside the CPU. 
Added two functions to query NMI and SMI from Bochs debugger.
In future they could be used for generating NMI or SMI by user request using GUI button (could be implemented separatelly later and under configure-time or .bocshrc option)
 2006-03-16 20:24:09 +00:00
Stanislav Shwartsman
a64b16391d Remove unused vars 2006-03-15 17:57:11 +00:00
Stanislav Shwartsman
da0b2ac377 Update dependencies for iodev and root project folders. 
Fixed compilation errors for 386 case
Added file header for slowdown_timer.h
 2006-03-06 22:32:03 +00:00
Stanislav Shwartsman
7b6c2587a9 Now devices could be compiled separatelly from CPU 
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
 2006-03-06 22:03:16 +00:00
Stanislav Shwartsman
5fad793989 move local apic handling to the access_linear function for the memory class. 
speedup the whole simulation by 2% !
 2006-03-01 22:32:24 +00:00
Stanislav Shwartsman
9b3be40d88 Improve OS/2 hack - save full segment (including hidden part) and not only selector value 2006-02-28 20:29:03 +00:00
Stanislav Shwartsman
a527b2cfca first smm - implement cpu state when switching to SMM 
smm coming soon
fixed code duplication in init.cc
 2006-02-28 19:50:08 +00:00
Stanislav Shwartsman
55ceecf79b Small optimization in icache page-write-stamp 2006-02-28 17:47:33 +00:00
Stanislav Shwartsman
79306b851c Separate fetch/decode instruction block to stand-alone method. 
The method could be reused when building instruction trace for DT
 2006-02-23 18:23:31 +00:00
Stanislav Shwartsman
5c58b22f44 Fixed opcode names according to Intel docs 
Fixed bug found during disasm validation
 2006-02-17 13:34:31 +00:00
Stanislav Shwartsman
203a9caf31 SMM mode could leave together with pmode or any other (according to amd docs) 
so we need separate bx_bool indicator in_smm instead
 2006-02-14 20:03:14 +00:00
Stanislav Shwartsman
024ce249bf Define SMM mode for future implementation. 
I would like all next commits be aware of SMM mode.
It can't be implemented right now (too many questions w/o answers) but it will be done till next major release definitelly.
 2006-02-14 19:00:08 +00:00
Stanislav Shwartsman
2646484dc1 Fix 'show' command in Boch debugger. 
Fully supported show-interrupts, show-mode and show-call options
Enable toggling of show options (bug report from SF)
 2006-02-12 20:21:36 +00:00
Stanislav Shwartsman
1d4fa8b327 Available back ability to use eip register as source in 'set reg = <expr>' cmd. 
Setting the eip register still not available (deliberatelly).
I don't want to enable it util I find some easy interface to do it.
I don't want to allow setting of part of RIP register using 'set eip=<expr>' and leave the upper part unchanged ....

Remove unused test registres from debugger
Fix compilation error in cpu.h
Change trace-on/trace-off commands. Make one 'trace' command with usage of 'trace on/trace off'
 2006-01-31 19:45:34 +00:00
Stanislav Shwartsman
067f23e3da Fix set 'ah,bh,ch,dh' registers from debugger 
Enable disasm by default - in adds some useful information to debug messages in log file
Remove defines for 8bit registers from cpu.h, the x86 arch defines not match defines used by set_reg and get_reg methods.
 2006-01-27 19:50:00 +00:00
Stanislav Shwartsman
18afa9fd2d This is cumulative patch for bochs debugger, it is only very first step towards working debugger supporting all new simulator functionalitieS. 
- move crc.cc from debugger to bochs folder and make it projct-wide and not local for debugger
 - added new 'info sse' command for debugger
 - extend 'modebp' command to break on any mode change
 - remove unimplemened 'info program' function, it is always printed fixed text
 - move debugger help to parser, cleanup and simplify it
 2006-01-24 19:03:55 +00:00
Stanislav Shwartsman
9df8079206 Write to MSR_TSC implemented (patch by Bryce) 2006-01-21 12:06:03 +00:00
Stanislav Shwartsman
08c15c67c0 Don't know how much it helps ... 
First step to make bx debugger supporting x86-64. guard_found object fields conerted to bx_address for x86-64 support.
 2006-01-19 18:32:39 +00:00
Stanislav Shwartsman
2c8f6f7720 Merged patch: determine number of processors to emulate through .bochsrc 2006-01-18 18:35:38 +00:00
Stanislav Shwartsman
89e3472178 Fix validate_seg_regs check 2006-01-09 19:34:52 +00:00
Stanislav Shwartsman
dfc633ef0a New debug function in cpu 2005-12-19 17:58:08 +00:00
Stanislav Shwartsman
cd2a8da34c Add more debugging/instrumentation functionality 2005-12-14 20:05:40 +00:00
Stanislav Shwartsman
f863d1e902 Generate #GP exception instead of #TS when TSS selector points to bad TSS 2005-12-12 19:44:06 +00:00
Stanislav Shwartsman
8c91790680 Redefine registers accessors in cpu.h 
Change BxSupportPAE and BxSupportGlobalPages macros to Bochs style names
Set bx_cpu_id in BX_CPU_C constructor (safe way)
Backup cpu-level check for paging features at compile time (already checked in configure)
Some warnings and indent fixes
speed up get_segment_base method for x86-64 case
 2005-11-26 21:36:51 +00:00
Stanislav Shwartsman
670395f1be VME support - beta #1 2005-10-17 13:06:09 +00:00
Stanislav Shwartsman
e83c77db49 Preparing to VME implementation 
DO NOT ENABLE VME option until the implementation will be completed !
 2005-10-16 23:13:19 +00:00
Stanislav Shwartsman
7022be46f5 Fix undefined flags handling for ROR and RCR instructions 2005-10-13 19:28:10 +00:00
Stanislav Shwartsman
8c783bc329 Fixed cpu_mode corruption in x86-64 mode 
Removed all potentially unsafe and duplicated code in setFLAGS methods to avoid such kind of problems in future
 2005-09-29 17:32:32 +00:00
Stanislav Shwartsman
d1c722211e Fix duplicate opcodes, fix opcode names and disasm bugs 2005-09-23 16:45:41 +00:00
Stanislav Shwartsman
95b12d7429 #SF patch fixed transition from vm8086 to PM 2005-09-11 20:00:29 +00:00
Stanislav Shwartsman
33c0c5367c Fixed bug in tasking.cc last change 2005-09-03 11:39:26 +00:00
Stanislav Shwartsman
086ee4c9aa Fix code duplication in tas 2005-08-28 17:37:37 +00:00
Stanislav Shwartsman
823dfa6f40 This code will be required for dynamic translation in future. 
For now it is no more than code duplication fix ...
 2005-08-23 20:01:54 +00:00
Stanislav Shwartsman
126069829d Fixed compilation error when icache is disabled 2005-08-13 14:10:22 +00:00
Stanislav Shwartsman
b192b2af9b Optimize pageWriteStamp checking 2005-08-10 18:18:57 +00:00
Stanislav Shwartsman
37bd193337 Split PUSHF/POPF to 3 different methods according to op size. 
By the way fix VIP/VIF flags handling in POPF/PUSHF (future fix for VME)
 2005-08-08 19:56:11 +00:00
Stanislav Shwartsman
8be190d848 Implemented RDTSCP instruction 2005-08-05 12:47:33 +00:00
Stanislav Shwartsman
ea30a3ef06 Implemented CALL FAR in 64-bit mode 2005-08-04 19:38:51 +00:00
Stanislav Shwartsman
084b4fa2b2 Fixed IRET implementation for long mode 2005-08-03 21:19:11 +00:00
Stanislav Shwartsman
3681126235 Fixed ugly load_ss64/mode changing workaround in exception.cc 2005-08-03 21:10:42 +00:00
Stanislav Shwartsman
d8ab4e3424 Fully implemented jump_far and ret_far in 64-bit mode. 
Note that I am not sure about 100% correctness, I am just coding Intel specs ...
Code review and massive testing still required.
 2005-08-02 18:44:20 +00:00
Stanislav Shwartsman
f096a80716 Fix code duplication for check_cs descriptor 
The function will execute
 - segment is executable code segment
 - conforming/non-conforming segment priviledge checks
 - segment is present
 2005-08-01 21:40:17 +00:00
Stanislav Shwartsman
954aae3f99 Speedup push/pop operations, they actually not needed to do can_push/can_pop checkes, the same checkes already done in read/write_virtial methods 
Split push_seg_reg methods according to op size
 2005-07-31 17:57:27 +00:00
Stanislav Shwartsman
5da36b7d3d Fixed code duplication, added canonical address checking for RETF in long mode 2005-07-29 06:29:57 +00:00
Stanislav Shwartsman
2b5a812674 Split last bit.cc methods according to os16/32/64 2005-07-25 04:18:20 +00:00
Stanislav Shwartsman
51e03f071d Fixed XLAT instruction for x86-64 
Small optimization for lazy flags for ADD/ADC/SUB/SBB instructions
Enable RETF64 for same privelege level return
 2005-07-21 01:59:05 +00:00
Stanislav Shwartsman
169fa0c574 Clearify the code. x86-64 code always running in pmode so it is not needed to check if we are in protected mode everytime 2005-07-10 20:32:32 +00:00
Stanislav Shwartsman
01d8a97613 Try to cleanup/rewrite RepeatSpeedups optimization 
This code doesn't add new speedups but makes it very easy
After some validation it could be no problem to enable repeat speedups optimization for REP MOVSx with any address size. And REP STOSx too.
 2005-07-04 17:44:08 +00:00
Stanislav Shwartsman
64f6d8c293 Separate force_flags function from read_flags (fix code duplication) 2005-06-16 17:25:04 +00:00
Stanislav Shwartsman
0b60100a0d Merged patch for Hkan T. Johansson 
TLB access bit optimizations
 2005-06-14 20:55:57 +00:00
Stanislav Shwartsman
663f7d5ef3 CMPXCHG16B instruction implemented 2005-05-19 20:25:16 +00:00
Stanislav Shwartsman
caa0648188 Move duplicated code to separate function 
And fix a bug I added by previous merge
 2005-04-17 21:51:59 +00:00
Stanislav Shwartsman
6fa52214b0 Canonical address check for RIP in x86-64 2005-04-17 18:54:54 +00:00
Stanislav Shwartsman
0b6a3afb53 Fixed compilation problem in segment_ctrl.pro 
Restore back the workaround for segmentation checking in exception.cc until the better solution will be found
 2005-04-13 17:13:05 +00:00
Stanislav Shwartsman
9b30cad4c4 Just software changes: 
1. Separate interrupt function to 3 different functions (real_mode, long_mode, pmode)
2. Added PANIC messages for not implemented FAR CALL, FAR JUMP and FAR RET in long mode
 2005-04-12 18:08:10 +00:00
Stanislav Shwartsman
c2c18d2aa4 Clean fix for loading NULL SS selector in exception.cc 2005-04-11 18:53:04 +00:00
Stanislav Shwartsman
1755589376 Separate pageWriteStamp from ICACHE. The pageWriteStamp has totally independant structure and could be used in future with icache structure. Also it could be significantly speeded up using BX_SMF analog constructions. 2005-04-10 19:42:48 +00:00
Stanislav Shwartsman
6d491de4d3 Fixed bug with jumping from long mode when executing interrupt 2005-03-30 22:31:03 +00:00
Stanislav Shwartsman
0f7f728e86 Added debug messages for interrupt function in long mode 
Added mode switch debug prints
 2005-03-30 20:53:04 +00:00
Stanislav Shwartsman
da9091f04a Fixed compatability mode execution bug, compatability mode and long mode should be treated as protected for all protected_mode() checks 2005-03-29 21:37:06 +00:00
Kevin Lawton
831afe7c40 Removed unused instruction (function) prototypes which were generated as 
a result of the initial implementation of AMD64 support.  These appear
  to have been cut-n-paste vestiges.
 2005-03-25 21:33:47 +00:00
Kevin Lawton
e6cb602231 Moved macros for duplicate SSE/SSE2 functions from fetchdecode.h to 
cpu.h, and defined function prototypes for the case where bochs
  is compiled with a new #define (called StandAloneDecoder) is set.
  This allows for the decoder to be tested separately from bochs.
 2005-03-23 01:45:16 +00:00
Kevin Lawton
4e03c4448c Added some comment tags so that a script can pull out relevant parts 
of the decoder to test it in standalone mode.  A few lines in cpu.h
  were re-arranged to make this easy, but no real lines of code were
  changed or generated.
Changed a few PANICs to INFOs after testing corresponding cases.
 2005-03-22 18:19:55 +00:00
Stanislav Shwartsman
f77ddd9701 Remove cpu_onlline_map varaible, it wasn't initialized properly and might cause APIC problems 2005-03-19 18:43:00 +00:00
Stanislav Shwartsman
6e53a54907 Extend cpu_mode for : 
#define BX_MODE_IA32_REAL       0x0   // CR0.PE=0
#define BX_MODE_IA32_PROTECTED  0x1   // CR0.PE=1, EFLAGS.VM=0
#define BX_MODE_IA32_V8086      0x2   // CR0.PE=1, EFLAGS.VM=1
#define BX_MODE_LONG_COMPAT     0x3   // EFER.LMA = 0, EFER.LME = 1
#define BX_MODE_LONG_64         0x4   // EFER.LMA = 1, EFER.LME = 1
 2005-03-15 19:00:04 +00:00
Stanislav Shwartsman
189e55885d put VME initial code in BX_SUPPORT_VME ifdefs 2005-03-13 20:18:37 +00:00
Stanislav Shwartsman
fd13784231 Small cleanup in access.cc 
VME feature code should be valid only for CPU LEVEL >= 4
 2005-03-12 19:34:18 +00:00
Stanislav Shwartsman
2a5a5c2de5 Fixed compilation error for 486 CPU 
small fixes for IRET instructionm
 2005-03-12 16:40:14 +00:00
Stanislav Shwartsman
24fa5935c1 Getting little bit closer to VME feature 2005-03-09 22:01:13 +00:00
Stanislav Shwartsman
709b218c10 Reduce metaInfo initialization in fetchDecode 2005-03-01 21:44:01 +00:00
Stanislav Shwartsman
b25088bf2f Merge patch [1153327] ignore segment bases in x86-64 by Avi Kivity 2005-02-28 18:56:05 +00:00
Stanislav Shwartsman
c583a6f9cf move segments and descriptors definitions and macroses for new descriptor.h 2005-02-27 17:41:45 +00:00
Stanislav Shwartsman
2bfc842c09 CPU fixes by Kevin Lawton 2005-02-16 21:27:21 +00:00
Stanislav Shwartsman
91526a90b3 Merged patch 
[1123895] x86-64 gdb/debugger fixes by Avi Kivity
 2005-02-16 18:58:48 +00:00
Stanislav Shwartsman
799403620e Small speedup in boundaryFetch method 2005-02-12 14:00:13 +00:00
Stanislav Shwartsman
9305305493 First (and may be last) step to implementation of 
Virtual Mode Extensions (VME)
and
Protected Mode Virtual Interrupts (PVI)
instructions STI and CLI have full support of these features, according to Intel docs. Need to check POPF and PUSHF instructions and afterwise VME and PVI extensions could be enabled in CR4
 2005-02-03 22:08:34 +00:00
Stanislav Shwartsman
bbcc5e0e3a Split BOUND instruction to two different according to operand size 
Coding style change
 2005-01-28 20:50:48 +00:00
Stanislav Shwartsman
8fe15b0ddc Fixed compilation error 2004-12-17 10:50:49 +00:00
Stanislav Shwartsman
f5b64a3a59 more preparations to NXE feature 2004-12-16 22:21:35 +00:00
Stanislav Shwartsman
da24883199 Extend page directory entries to 8 byte in PAE mode when X86_64 is enabled 
(prepartions to NX feature implementation)
 2004-12-13 22:26:36 +00:00
Stanislav Shwartsman
46bb3d8853 remove duplicated data arrays from CPU 2004-12-11 20:51:13 +00:00
Stanislav Shwartsman
0d09a8c8a8 fix code duplication 2004-11-26 19:53:04 +00:00
Stanislav Shwartsman
69c0b06955 fixes in disassembler 
split REPEAT instructions according to opsize to speedup execution
now each REPEATABLE instruction splitted to 3 different instructions, one for 16-bit operand size, one for 32-bit and one for 64-bit. Choosing of correct instruction occure in fetchdecode step.
 2004-11-20 23:26:32 +00:00
Stanislav Shwartsman
645e04860e For now : disable fetching from physical address 0xFFFFFFF0 after #RESET 
because ICACHE do not support physical address > mem.len.
This is the first part of the fix, the rest coming soon
 2004-11-18 23:16:36 +00:00
Stanislav Shwartsman
7b62a6e206 Fix reset registers in CPU for #RESET signal 
Extract ICACHE from cpu.h to separate icache.h
 2004-11-14 19:29:34 +00:00
Stanislav Shwartsman
2ce5495d38 Fixed compilation errors 2004-11-03 06:35:48 +00:00
Stanislav Shwartsman
2ed7e4eed5 EIP > CS.limit should be checked in real mode too. 
Enable for now for JUMP instructions, still todo - CALL and RET
 2004-11-02 17:31:14 +00:00
Stanislav Shwartsman
f06c8b6b95 EIP > CS.limit should not be a problem 
Manual says that GP(0) shouldd be generated in this case ALWAYS
Fixed instructions PANIC messages to ERROR for this case
And ... do not leave PANIC messages w/o taking care that user could push CONTINUE button and program should know to continue after the PANIC code line. Mainly in rerurn instructions were several problems ...
 2004-11-02 16:10:02 +00:00
Stanislav Shwartsman
a9022ac5cb Fixed compilation prroblem reported in bug 
[ bochs-Bugs-913418 ] compiler errors with --enable-external-debugger option
Remove code duplication
 2004-10-29 21:15:48 +00:00
Stanislav Shwartsman
5e23909c7c prepations for NX bit implementation 2004-10-21 18:20:40 +00:00
Stanislav Shwartsman
040be015d8 1. Added required GP(0) exception when setting conficting flags in CR0 
2. APIC disabled compilation error fixed
 2004-09-21 20:19:19 +00:00
Stanislav Shwartsman
760a195c9d * Fix LOCK prefix handling for x86-64 
* Split BT*_EvGv functions to 3 different function according to exec mode
 2004-09-17 20:47:19 +00:00
Stanislav Shwartsman
bbd55fe16f Merge and commit patch.apic-zwane from CVS patches directory. 
the patch release notes by Zwane:

o Define symbols for constants like
o APIC arbitration
o Processor priority
o Various interrupt delivery fixes
o Focus processor checking
o ExtINT delivery

I need to release this now so that i don't fall too far behind CVS, when
it was part of the bochs-smp patch it could boot 2.4.18 4way. Apologies
for the whitespace changes.


Also remove patch.apic-ppr-zwane patch because it already included in
patch.apic-zwane.

I hope it will help to boot x86-64 or cmp systems required missed APIC
features !
 2004-09-15 21:48:57 +00:00
Stanislav Shwartsman
283f9ae5d2 Simplify cpu.h 
Speedup FYL2X and FYL2XP1 instructions
 2004-09-14 20:19:54 +00:00
Stanislav Shwartsman
6cdb42d909 Little bit optimize memory access functions. Now values are calculated only if they actually needed. 2004-09-13 20:48:11 +00:00
Stanislav Shwartsman
fc631037ff remove obsolete comments from fetchdecode 2004-09-06 20:22:39 +00:00
Stanislav Shwartsman
016207b222 Commented problematic check in misc_mem.cc 
Implemnted lazy-flags and undocumented flags handling for IMUL instructions
 2004-08-30 21:47:24 +00:00
Stanislav Shwartsman
b370a417a4 Optimize lazy-flags for ADC and SBB instructions 2004-08-18 20:47:35 +00:00
Stanislav Shwartsman
1b7b791493 Speedup lazy-flags for INC and DEC instructions 2004-08-14 20:00:24 +00:00
Stanislav Shwartsman
1732e54baa Fixed undocumented flags handling for some instructions. 
Bugfix for CF flag handling for SHL64 instruction
 2004-08-14 19:34:02 +00:00
Stanislav Shwartsman
a1f830d429 Implemented FAST lazy flags version for logic instructions. 
Small code cleanup/simplification for others.
 2004-08-13 20:00:03 +00:00
Stanislav Shwartsman
5de51f67d9 Prepare lazy flags macroses for more efficient lazy flags handling 2004-08-11 21:26:23 +00:00
Stanislav Shwartsman
8f0cf91fff This commit is the first commit in long series of changes the have several purposes: 
1. Review and commit patch

	[ 896733 ] Lazy flags, for more instructions, only 1 src op

   May be partially, but I hope to get all ideas from patch in

2. Get Bochs speedup after lazy flags optimization

3. Most important for me: improve correctness of emulation by handling several
   undocumented EFLAGS modifications. And finally pass

	UFLAGS - Undefined Flags Test v 3.0
	Copyright (C) Potemkin's Hackers Group (PHG) 1989,1995

   The test still fails on > 50% of its checks.
 2004-08-09 21:28:47 +00:00
Stanislav Shwartsman
f9bd2b74be 1. Fixed bug in FSUB instruction 
2. Fixed bug

[ 989478 ] I-Cache and undefined Instruktions

The L4 microkernel uses an undefined instruction to
trap for a special requests into the kernel (LOCK NOP).
The handler fixes this up and gives the user a special
code page with syscall stubs. If you're not using the
I-Cache optimization everthing works find on bochs. But
if you enable the I-Cache (--enable-icache), then the
undefined opcode exception is thrown only once for ever
virtual address it occurs. See the demodisk of the
L4KA::pistachio
(http://www.l4ka.org/projects/pistachio/download.php).
In this case the pingpong benchmark of this demo is of
interest. Everything runs fine until the program tries
to spawn a new task for its measurements. This new task
shares the code of the creating program. But the new
task stops executing at the undefined instruction
explained above and no exception is thrown.
 2004-07-29 20:15:19 +00:00
Stanislav Shwartsman
50aaf8ec6f Implemented FFREEP 287+ compatability instruction 2004-07-15 19:45:33 +00:00
Stanislav Shwartsman
79b1cfdc1c removed unused code 2004-07-12 19:20:55 +00:00
Stanislav Shwartsman
5c5b556f24 Merge softfloat-fpu-implementation_ver4_branch branch 2004-06-18 14:11:11 +00:00
Stanislav Shwartsman
3274e0dd12 Commit patch 
[ 950905 ] Do not PANIC on rare, bad input from user-mode
by h.johansson
with little changes and fixes
 2004-05-10 21:05:51 +00:00
Stanislav Shwartsman
cf6d1b8bd9 port some changes from spftfloat-fpu branch to the MT 2004-04-09 15:34:59 +00:00
Stanislav Shwartsman
3f7c794b26 commit patch 
899972 data xfer performance patch V 2.0.4   2004-02-18 15:38 nobody psychosmur
 2004-02-26 19:17:40 +00:00
Christophe Bothamy
e17995f5db - host asms in a specific file 
- add msvcc host asm instructions, patch by suzu
 2004-02-15 17:57:45 +00:00
Christophe Bothamy
82429b5ac5 - fixes for booting OS/2 by Dmitri Froloff 
- v8086 priveleged instruction processing bug (was also reported by
  LightCone Aug  7 2003)
  - exception process bug (was reported by Diego Henriquez Sat Nov 15
  01:16:51 CET 2003)
  - segment validation with IRET instruction
  - CS segment not present exception processing with IRET
 2004-02-11 23:47:55 +00:00
Stanislav Shwartsman
9120961241 update checking for pending FPU exceptions code 2004-01-31 13:43:26 +00:00
Michael Brown
d1922bc835 Changed #ifdef MAGIC_BREAKPOINT to #if BX_MAGIC_BREAKPOINT and added a 
configure script option --enable-magic-breakpoints (enabled by default).

Documented the instruction required to trigger the magic breakpoint
(xchgw %bx,%bx).
 2004-01-29 17:49:03 +00:00
Daniel Gimpelevich
ae66bb33c0 Applied Russ Cox's CPU panic debug patch from Oct 2003. 2004-01-17 08:36:29 +00:00
Christophe Bothamy
e7e0b40bd1 - remove calculation on cr3 in dtranslate_linear, one of the most called functions (patch by Conn Clark) 2003-12-30 22:12:45 +00:00
Daniel Gimpelevich
fb80d47dbf *** empty log message *** 2003-12-29 21:24:35 +00:00
Stanislav Shwartsman
7deb9491da Fixed compilation error for FPU disabled case 2003-12-29 20:26:05 +00:00
Daniel Gimpelevich
68fd1dc95b cleanup optimizations & fix compile error 2003-12-29 07:28:28 +00:00
Stanislav Shwartsman
fd60a984a0 Instructions that should not check pending FPU exceptions 2003-12-28 18:58:15 +00:00
Stanislav Shwartsman
9ccb363ec3 bochs style decode/execute of FPU instructions. 
With this coding style each instruction could be implemented separatelly even not together with current Bochs FPU emulator.
Step-by-step I am going to transfer all FPU instructions from current Bochs FPU emulator to new style and remove an old bugged emulator.
Anyway, now I could implement all currently missed FPU instructions without hacking wm-fpu-emu.
 2003-12-27 13:50:06 +00:00
Stanislav Shwartsman
d51aece0c1 Change BX_PANIC messages to BX_INFO when behaviour is accepted with Intel/AMD docs. 
Instructions MOV_CxRx and MOV_RxCx are not supported in v8086 mode according to Intel manuals.
Also these instructions are treated as register-to-register regardless to MODRM byte fields (according to AMD manuals)
Also commit fix for MOV_EwSw by Kevin
 2003-11-13 21:17:31 +00:00
Stanislav Shwartsman
ac50ab3760 Implemented RCPSS/RCPPS SSE instructions 2003-11-07 20:53:27 +00:00
Stanislav Shwartsman
4e74efdf0c Fast fxsave/fxrstor 2003-10-24 20:44:43 +00:00
Stanislav Shwartsman
ac20b6405a - FXSAVE/FXRSTOR instructions should be available in P6 mode 
- Added second UD2 opcode to fetchdecode
- Added RDPMC instruction to fetchdecode
- 'changes' updated
 2003-10-24 18:34:16 +00:00
Stanislav Shwartsman
7f570b0150 Added PNI new streaming extensions instructions 
PNI could be enabled by setting BX_SUPPORT_PNI in config.h
After the feature will be fully validation I'll also add configure option.

The implemntation is ~complete. I've missed only three FPU new opcodes of FUSTTP instruction and MONITOR/WAIT instructions.

Enjoy ! ;)
 2003-08-29 21:20:52 +00:00
Stanislav Shwartsman
254ad17328 Changes method of resolving opcode/attributes from group table 
New method more flexible and easy to understanding.
Reorganizing fetchdecode code and make it more easy and understandable
 2003-08-28 19:25:23 +00:00
Stanislav Shwartsman
79f46df971 separate APIC from CPU 2003-08-17 18:55:16 +00:00
Alexander Krisak
8559551001 iretd cpu instruction in real mode implemented, i hope this closes bugs 537047, 
603410, 637822, 664544, 687619.
 2003-08-17 18:15:04 +00:00
Stanislav Shwartsman
1616539667 additional FPU changes 2003-08-01 09:32:33 +00:00
Volker Ruppert
2ef0c43c7d - description of ldtr fixed 2003-06-08 09:55:50 +00:00
Stanislav Shwartsman
1d45167e5b Merged NEW-INSTRUCTIONS branch 2003-05-15 16:41:17 +00:00
Kevin Lawton
a17d06abcb Optimized the main cpu loop iCache checks to remove a redundant 
check.

Commented out a number of instances of invalidate_prefetch_q(),
for branches which do not change CS since the EIP window mechanism
takes care of validating that EIP lands in the current page or not
in the main cpu loop anyways.

Fixed a couple cases (v8086 mode and real mode) of loading CS where
the EIP page window was not invalidated in segment_ctrl_pro.cc.
That may fix some aliasing problems reported before (OS2).
 2003-05-10 22:25:55 +00:00
Stanislav Shwartsman
d1d2fb34f0 Fixed number of compilation errors for FPU disabled case 
Transfer fpu.cc from /fpu to /cpu
 2003-04-22 20:21:34 +00:00
Stanislav Shwartsman
7db893970c Read attributes bits even for BxSplit11b opcodes 
Move lock prefix check later in fetchdecode function when all attributes is ready.
 2003-04-06 19:08:31 +00:00
Stanislav Shwartsman
a050c1ac7d Reserved cpu attribute bit for 3DNOW instructions decoding 2003-04-05 16:40:55 +00:00
Stanislav Shwartsman
1e71c9e56e Merged patch-unallowed-lock-cases patch. 
According to the Intel manuals:

  The  LOCK  prefix  can be prepended only to the following instructions
  and  only  to  those  forms  of the instructions where the destination
  operand  is  a  memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG,
  CMPXCH8B,  DEC,  INC,  NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. If
  the  LOCK prefix is used with one of these instructions and the source
  operand  is a memory operand, an undefined opcode exception (#UD) will
  be  generated. An undefined opcode exception will also be generated if
  the  LOCK  prefix  is used with any instruction not in the above list.

 Checking of the LOCK prefix done in fetchDecode state and not overloads
 Bochs's execution.
 2003-04-05 12:16:53 +00:00
Christophe Bothamy
1a518b81fe - add __attribute__((regparm(X))) performance trick with gcc on x86 
on some cpu instructions (patch from Conn Clark)
- performance improvement is 1% on win95 boot
 2003-03-17 00:41:01 +00:00
Christophe Bothamy
50efc3b8c7 - apply Conn Clark's patch.perf-regparm-cclark : 
- it works only on x86 with gcc2.95+
  - uses the GCC function atribute "regparm(n)" to declare that certain
    functions use the register calling convention
  - performance improvement is about 6%
 2003-03-02 23:59:12 +00:00
Peter Tattam
94880d1412 Fix guest2host and related optimizations to work on 64 bit host. 
1) fixed the type of "hostPageAddr" and associated typecasts.
2) fixed the type of "pages" and associated typecasts (overloaded variable)
3) patch to cpu.cc to calculate "eipPageBias" correctly in 64 bit mode
 2003-02-28 02:37:18 +00:00
Peter Tattam
70d752c8c2 external debugger only: fixed ask() to be virtual to let a panic trap into external debugger 2003-02-26 02:41:30 +00:00
Stanislav Shwartsman
7fa75388a1 Added bx_cpuid value to the BX_CPU class to avoid any problems with BX_CPU_ID implementation 2003-02-13 15:51:22 +00:00
Stanislav Shwartsman
cdfc3cbce4 instrumentation enchancements: 
* renamed CPU_ID to BX_CPU_ID.
  with this new name there is no possibility for name contentions and BX_CPU_ID
  definition could be moved out to NEED_CPU_REG_SHORTCUTS block

* returned back `unsigned BX_CPU::which_cpu(void)` function

* added BX_CPU_ID parameter for
	BX_INSTR_PHY_READ(a20addr, len);
	BX_INSTR_PHY_WRITE(a20addr, len);
    now it will be
	BX_INSTR_PHY_READ(cpu_id, a20addr, len);
	BX_INSTR_PHY_WRITE(cpu_id, a20addr, len);
 2003-02-13 15:04:11 +00:00
Bryce Denney
7336c891ee - CPU_ID fix from Shai Fultheim, who writes: 
> CPU_ID is defined as
  > #define CPU_ID (BX_CPU_THIS_PTR local_apic.get_id())
  > This is not true when the APIC name is changed (true in Linux). Please
  > change this to:
  > #define CPU_ID (BX_CPU_THIS - BX_CPU(0))
 2003-02-09 13:30:39 +00:00
Christophe Bothamy
939b558fdf - apply patch.sysenterexit-mrieker: 
- adds sysenter/sysexit support for cpu-level>=6
  - enabled by ./configure --enable-sep
 2003-01-20 20:10:31 +00:00
Stanislav Shwartsman
29ab05b4da Removed duplicate SSE opcodes 2002-12-22 20:48:45 +00:00
Stanislav Shwartsman
1cd38bb7dd Recommitted SSE code reorganization. 
Fix in FXSAVE/FXRESTOR opcodes -> If the OSFXSR bitCR4 is not set, the FXRSTOR instruction does not restore the states of the XMM and MXCSR registers.
 2002-12-22 20:13:00 +00:00
Stanislav Shwartsman
4906ffef7c Clean Peter's commit with MOVNTDQ instruction implementation 2002-12-20 09:11:39 +00:00
Bryce Denney
9b2914fd1d - Temporarily revert Stanislav's changes between 2002-12-18 and 2002-12-19. 
Because source files were added/removed it would require an update
  of the windows and macos project files, so I want to wait until after 2.0.
    M Makefile.in         1.51 back to 1.50
    M cpu.h               1.121 back to 1.120
    M fetchdecode.cc      1.37 back to 1.36
    M fetchdecode64.cc    1.33 back to 1.32
    M sse.cc              1.17 back to 1.16
    A sse2.cc             1.27 back to 1.26  (added back)
    R sse_move.cc         removed
    R sse_pfp.cc          removed
- to bring these changes back again, all we have to do is
  "cvs update -j tmp-before1 -j tmp-after1"
 2002-12-19 05:53:18 +00:00
Stanislav Shwartsman
aa361badf2 Reorganized SSE/SSE2 code 
sse.cc -> general SSE stuff and SSE integer (MMX extensions)
sse_move.cc -> memory transfer and shuffle opcodes
sse_pfp.cc -> packed floating point operations
 2002-12-18 22:33:44 +00:00
Christophe Bothamy
16ebfdb9e1 - update for macos compile 2002-12-12 15:29:45 +00:00
Stanislav Shwartsman
bcd57bdcaf *** Current duplicate SSE/SSE2 instructions list *** 
MOVUPS_VpsWps  (0f 10) = MOVUPD_VpdWpd  (66 0f 10) = MOVDQU_VdqWdq (f3 0f 6f)
MOVUPS_WpsVps  (0f 11) = MOVUPD_WpdVpd  (66 0f 11) = MOVDQU_WdqVdq (f3 0f 7f)
MOVAPS_VpsWps  (0f 28) = MOVAPD_VpdWpd  (66 0f 28) = MOVDQA_VdqWdq (66 0f 6f)
MOVAPS_WpsVps  (0f 29) = MOVAPD_WpdVpd  (66 0f 29) = MOVDQA_WdqVdq (66 0f 7f)

MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)
MOVLPS_VpsMq   (0f 12) = MOVLPD_VsdMq   (66 0f 12)
MOVLPS_MqVps   (0f 13) = MOVLPD_MqVsd   (66 0f 13)
MOVHPS_VpsMq   (0f 16) = MOVHPD_VpdMq   (66 0f 16)
MOVHPS_MqVps   (0f 17) = MOVHPD_MqVpd   (66 0f 17)

ANDPS_VpsWps   (0f 54) = ANDPD_VpdWpd   (66 0f 54) = PAND_VpdWpd   (66 0f db)
ANDNPS_VpsWps  (0f 55) = ANDNPD_VpdWpd  (66 0f 55) = PANDN_VpdWpd  (66 0f df)
ORPS_VpsWps    (0f 56) = ORPD_VpdWpd    (66 0f 56) = POR_VpdWpd    (66 0f eb)
XORPS_VpsWps   (0f 57) = XORPD_VpdWpd   (66 0f 57) = PXOR_VpdWpd   (66 0f ef)

Removed dupes
 2002-11-25 21:58:55 +00:00