Fixed compilation prroblem reported in bug
[ bochs-Bugs-913418 ] compiler errors with --enable-external-debugger option Remove code duplication
This commit is contained in:
Stanislav Shwartsman
parent
63eae87ab2
commit
a9022ac5cb
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: bochs.h,v 1.143 2004-10-16 15:44:00 vruppert Exp $
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// $Id: bochs.h,v 1.144 2004-10-29 21:15:39 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -107,11 +107,6 @@ int bx_begin_simulation (int argc, char *argv[]);
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#define DEV_vga_mem_read(addr) bx_dbg_ucmem_read(addr)
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#define DEV_vga_mem_write(addr, val) bx_dbg_ucmem_write(addr, val)
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#if BX_SUPPORT_A20
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# define A20ADDR(x) ( (x) & bx_pc_system.a20_mask )
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#else
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# define A20ADDR(x) (x)
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#endif
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#define BX_INP(addr, len) bx_dbg_inp(addr, len)
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#define BX_OUTP(addr, val, len) bx_dbg_outp(addr, val, len)
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#define BX_HRQ (bx_pc_system.HRQ)
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@ -138,12 +133,6 @@ int bx_begin_simulation (int argc, char *argv[]);
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#else
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// =-=-=-=-=-=-=- Normal optimized use -=-=-=-=-=-=-=-=-=-=-=-=-=-=
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#if BX_SUPPORT_A20
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# define A20ADDR(x) ( (x) & bx_pc_system.a20_mask )
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#else
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# define A20ADDR(x) (x)
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#endif
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//
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// some pc_systems functions just redirect to the IO devices so optimize
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// by eliminating call here
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//
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@ -176,6 +165,12 @@ int bx_begin_simulation (int argc, char *argv[]);
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#endif
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#if BX_SUPPORT_A20
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# define A20ADDR(x) ( (x) & bx_pc_system.a20_mask )
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#else
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# define A20ADDR(x) (x)
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#endif
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// you can't use static member functions on the CPU, if there are going
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// to be 2 cpus. Check this early on.
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@ -186,9 +181,6 @@ int bx_begin_simulation (int argc, char *argv[]);
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#endif
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// #define BX_IAC() bx_pc_system.IAC()
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//#define BX_IAC() bx_dbg_IAC()
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//
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// Ways for the the external environment to report back information
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// to the debugger.
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@ -472,13 +464,10 @@ int bx_atexit(void);
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BOCHSAPI extern bx_debug_t bx_dbg;
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#define BX_READ 0
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#define BX_WRITE 1
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#define BX_RW 2
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// memory access type (read/write/rw)
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#define BX_READ 0
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#define BX_WRITE 1
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#define BX_RW 2
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#include "memory/memory.h"
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@ -494,10 +483,6 @@ enum PCS_OP { PCS_CLEAR, PCS_SET, PCS_TOGGLE };
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/* --- EXTERNS --- */
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#if BX_GUI_SIGHANDLER
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.89 2004-10-16 19:34:17 sshwarts Exp $
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// $Id: cpu.cc,v 1.90 2004-10-29 21:15:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -750,8 +750,7 @@ BX_CPU_C::prefetch(void)
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BX_PANIC(("prefetch: running in bogus memory"));
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}
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else {
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BX_PANIC(("prefetch: getHostMemAddr vetoed direct read, pAddr=0x%x.",
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pAddr));
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BX_PANIC(("prefetch: getHostMemAddr vetoed direct read, pAddr=0x%x.", pAddr));
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}
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.181 2004-10-21 18:20:32 sshwarts Exp $
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// $Id: cpu.h,v 1.182 2004-10-29 21:15:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -738,8 +738,6 @@ typedef struct {
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} bx_segment_reg_t;
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typedef void * (*BxVoidFPtr_t)(void);
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class BX_CPU_C;
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class bxInstruction_c {
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public:
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@ -1475,7 +1473,11 @@ public: // for now...
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// constructors & destructors...
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BX_CPU_C();
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~BX_CPU_C(void);
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#if BX_EXTERNAL_DEBUGGER
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virtual ~BX_CPU_C();
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#else
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~BX_CPU_C();
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#endif
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void init (BX_MEM_C *addrspace);
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// prototypes for CPU instructions...
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: ctrl_xfer32.cc,v 1.30 2004-10-19 20:05:07 sshwarts Exp $
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// $Id: ctrl_xfer32.cc,v 1.31 2004-10-29 21:15:48 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -62,7 +62,7 @@ BailBigRSP("RETnear32_Iw");
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/* ??? #SS(0) -or #GP(0) */
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}
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access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0,
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access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP,
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4, CPL==3, BX_READ, &return_EIP);
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if (protected_mode() &&
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@ -120,7 +120,7 @@ BailBigRSP("RETnear32");
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/* ??? #SS(0) -or #GP(0) */
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}
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access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0,
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access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP,
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4, CPL==3, BX_READ, &return_EIP);
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if ( return_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) {
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: ctrl_xfer64.cc,v 1.25 2004-10-19 20:05:07 sshwarts Exp $
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// $Id: ctrl_xfer64.cc,v 1.26 2004-10-29 21:15:48 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -56,7 +56,7 @@ BX_CPU_C::RETnear64_Iw(bxInstruction_c *i)
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// /* ??? #SS(0) -or #GP(0) */
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// }
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access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 0,
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access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP,
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8, CPL==3, BX_READ, &return_RIP);
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/* Pentium book says imm16 is number of words ??? */
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@ -90,7 +90,7 @@ BX_CPU_C::RETnear64(bxInstruction_c *i)
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// /* ??? #SS(0) -or #GP(0) */
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// }
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access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 0,
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access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP,
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8, CPL==3, BX_READ, &return_RIP);
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RIP = return_RIP;
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@ -2,7 +2,7 @@
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#ifdef WIN32
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// windows.h included in bochs.h
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#else
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//# error "extdb.cc only supported in win32 environment"
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# error "extdb.cc only supported in win32 environment"
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#endif
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TRegs regs;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: paging.cc,v 1.48 2004-10-21 18:20:34 sshwarts Exp $
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// $Id: paging.cc,v 1.49 2004-10-29 21:15:48 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -604,7 +604,6 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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bx_address lpf;
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Bit32u ppf, poffset, error_code, paddress;
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Bit32u pde, pde_addr;
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bx_bool isWrite;
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Bit32u accessBits, combined_access;
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unsigned priv_index;
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#if BX_USE_TLB
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@ -614,15 +613,14 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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InstrTLB_Increment(tlbLookups);
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InstrTLB_Stats();
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bx_bool isWrite = (rw>=BX_WRITE); // write or r-m-w
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#if BX_SupportPAE
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if (BX_CPU_THIS_PTR cr4.get_PAE()) {
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Bit32u pdp, pdp_addr;
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lpf = laddr & BX_CONST64(0xfffffffffffff000); // linear page frame
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poffset = laddr & 0x00000fff; // physical offset
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isWrite = (rw>=BX_WRITE); // write or r-m-w
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//BX_DEBUG (("poffset: %-8x laddr: %-8x lpf: %-8x",poffset,laddr,lpf));
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#if BX_USE_TLB
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TLB_index = BX_TLB_INDEX_OF(lpf);
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@ -658,33 +656,33 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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// PML4 Entry NOT present
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error_code = 0x00000000; // RSVD=0, P=0
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goto page_fault_not_present;
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}
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}
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if ( !(pml4 & 0x20) ) {
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pml4 |= 0x20;
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BX_CPU_THIS_PTR mem->writePhysicalPage(this, pml4_addr, 4, &pml4);
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}
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}
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// Get PDP entry
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pdp_addr = (pml4 & 0xfffff000) |
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((laddr & BX_CONST64(0x0000007fc0000000)) >> 27);
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}
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}
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else
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#endif
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{
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{
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pdp_addr = BX_CPU_THIS_PTR cr3_masked |
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((laddr & 0xc0000000) >> 27);
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}
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}
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BX_CPU_THIS_PTR mem->readPhysicalPage(this, pdp_addr, 4, &pdp);
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if ( !(pdp & 0x01) ) {
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// PDP Entry NOT present
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error_code = 0x00000000; // RSVD=0, P=0
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goto page_fault_not_present;
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}
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}
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if ( !(pdp & 0x20) ) {
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pdp |= 0x20;
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BX_CPU_THIS_PTR mem->writePhysicalPage(this, pdp_addr, 4, &pdp);
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}
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}
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// Get page dir entry
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pde_addr = (pdp & 0xfffff000) |
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@ -695,7 +693,7 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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// Page Directory Entry NOT present
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error_code = 0x00000000; // RSVD=0, P=0
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goto page_fault_not_present;
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}
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}
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#if BX_SUPPORT_4MEG_PAGES
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// (KPL) Weird. I would think the processor would consult CR.PSE?
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@ -724,18 +722,18 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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if (!priv_check[priv_index]) {
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error_code = 0x00000001; // RSVD=0, P=1
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goto page_fault_access;
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}
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}
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// Update PDE if A/D bits if needed.
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if ( ((pde & 0x20)==0) ||
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(isWrite && ((pde&0x40)==0)) ) {
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pde |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
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BX_CPU_THIS_PTR mem->writePhysicalPage(this, pde_addr, 4, &pde);
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}
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}
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}
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else
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#endif
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{ // 4k pages.
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{ // 4k pages.
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Bit32u pte, pte_addr;
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// Get page table entry
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@ -756,7 +754,7 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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// Page Table Entry NOT present
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error_code = 0x00000000; // RSVD=0, P=0
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goto page_fault_not_present;
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}
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}
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priv_index =
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#if BX_CPU_LEVEL >= 4
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@ -769,21 +767,21 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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if (!priv_check[priv_index]) {
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error_code = 0x00000001; // RSVD=0, P=1
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goto page_fault_access;
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}
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}
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// Update PDE A bit if needed.
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if ( (pde & 0x20)==0 ) {
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pde |= 0x20; // Update A bit.
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BX_CPU_THIS_PTR mem->writePhysicalPage(this, pde_addr, 4, &pde);
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}
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}
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// Update PTE A/D bits if needed.
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if ( ((pte & 0x20)==0) ||
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(isWrite && ((pte&0x40)==0)) ) {
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if (((pte & 0x20)==0) || (isWrite && ((pte&0x40)==0)))
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{
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pte |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
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BX_CPU_THIS_PTR mem->writePhysicalPage(this, pte_addr, 4, &pte);
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}
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}
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}
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// Calculate physical memory address and fill in TLB cache entry
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paddress = ppf | poffset;
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@ -825,7 +823,6 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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lpf = laddr & 0xfffff000; // linear page frame
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poffset = laddr & 0x00000fff; // physical offset
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isWrite = (rw>=BX_WRITE); // write or r-m-w
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#if BX_USE_TLB
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TLB_index = BX_TLB_INDEX_OF(lpf);
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@ -854,7 +851,7 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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// Page Directory Entry NOT present
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error_code = 0x00000000; // RSVD=0, P=0
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goto page_fault_not_present;
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}
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}
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#if BX_SUPPORT_4MEG_PAGES
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if ((pde & 0x80) && (BX_CPU_THIS_PTR cr4.get_PSE())) {
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@ -885,20 +882,18 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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if (!priv_check[priv_index]) {
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error_code = 0x00000001; // RSVD=0, P=1
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goto page_fault_access;
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}
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// Update PDE if A/D bits if needed.
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if ( ((pde & 0x20)==0) ||
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(isWrite && ((pde&0x40)==0)) ) {
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pde |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
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BX_CPU_THIS_PTR mem->writePhysicalPage(this, pde_addr, 4, &pde);
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}
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}
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// Update PDE if A/D bits if needed.
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if (((pde & 0x20)==0) || (isWrite && ((pde&0x40)==0))) {
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pde |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
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BX_CPU_THIS_PTR mem->writePhysicalPage(this, pde_addr, 4, &pde);
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}
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}
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// Else normal 4Kbyte page...
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else
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#endif
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{
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{
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Bit32u pte, pte_addr;
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#if (BX_CPU_LEVEL < 6)
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@ -906,7 +901,7 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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if ( !(pde & 0x20) ) {
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pde |= 0x20;
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BX_CPU_THIS_PTR mem->writePhysicalPage(this, pde_addr, 4, &pde);
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}
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}
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#endif
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// Get page table entry
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@ -934,7 +929,7 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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// Page Table Entry NOT present
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error_code = 0x00000000; // RSVD=0, P=0
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goto page_fault_not_present;
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}
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}
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priv_index =
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#if BX_CPU_LEVEL >= 4
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@ -947,24 +942,23 @@ BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
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if (!priv_check[priv_index]) {
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error_code = 0x00000001; // RSVD=0, P=1
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goto page_fault_access;
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}
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}
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#if (BX_CPU_LEVEL >= 6)
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// update PDE if A bit was not set before
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if ( !(pde & 0x20) ) {
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pde |= 0x20;
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BX_CPU_THIS_PTR mem->writePhysicalPage(this, pde_addr, 4, &pde);
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}
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}
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#endif
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// Update PTE if A/D bits if needed.
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if ( ((pte & 0x20)==0) ||
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(isWrite && ((pte&0x40)==0)) ) {
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if (((pte & 0x20)==0) || (isWrite && ((pte&0x40)==0)))
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{
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pte |= (0x20 | (isWrite<<6)); // Update A and possibly D bits
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BX_CPU_THIS_PTR mem->writePhysicalPage(this, pte_addr, 4, &pte);
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}
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}
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}
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// Calculate physical memory address and fill in TLB cache entry
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paddress = ppf | poffset;
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||||
@ -1115,9 +1109,6 @@ page_fault:
|
||||
BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
|
||||
unsigned rw, void *data)
|
||||
{
|
||||
Bit32u pageOffset;
|
||||
unsigned xlate_rw;
|
||||
|
||||
|
||||
#if BX_X86_DEBUGGER
|
||||
if ( BX_CPU_THIS_PTR dr7 & 0x000000ff ) {
|
||||
@ -1137,15 +1128,9 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
|
||||
}
|
||||
#endif
|
||||
|
||||
if (rw==BX_RW) {
|
||||
xlate_rw = BX_RW;
|
||||
rw = BX_READ;
|
||||
}
|
||||
else {
|
||||
xlate_rw = rw;
|
||||
}
|
||||
|
||||
pageOffset = laddr & 0x00000fff;
|
||||
Bit32u pageOffset = laddr & 0x00000fff;
|
||||
unsigned xlate_rw = rw;
|
||||
if (rw==BX_RW) rw = BX_READ;
|
||||
|
||||
if (BX_CPU_THIS_PTR cr0.pg) {
|
||||
/* check for reference across multiple pages */
|
||||
@ -1239,7 +1224,6 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
else {
|
||||
// Paging off.
|
||||
if ( (pageOffset + length) <= 4096 ) {
|
||||
@ -1388,7 +1372,6 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl,
|
||||
}
|
||||
#endif
|
||||
}
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: memory.h,v 1.21 2004-09-01 18:12:23 vruppert Exp $
|
||||
// $Id: memory.h,v 1.22 2004-10-29 21:15:48 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -26,7 +26,8 @@
|
||||
// License along with this library; if not, write to the Free Software
|
||||
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
|
||||
#ifndef BX_MEM_H
|
||||
# define BX_MEM_H 1
|
||||
|
||||
#define BX_USE_MEM_SMF 0
|
||||
|
||||
@ -55,7 +56,6 @@ struct memory_handler_struct {
|
||||
};
|
||||
|
||||
class BOCHSAPI BX_MEM_C : public logfunctions {
|
||||
|
||||
private:
|
||||
struct memory_handler_struct **memory_handlers;
|
||||
bx_bool rom_present[65];
|
||||
@ -90,7 +90,7 @@ public:
|
||||
BX_MEM_SMF bx_bool dbg_crc32(
|
||||
unsigned long (*f)(unsigned char *buf, int len),
|
||||
Bit32u addr1, Bit32u addr2, Bit32u *crc);
|
||||
BX_MEM_SMF Bit8u * getHostMemAddr(BX_CPU_C *cpu, Bit32u a20Addr, unsigned op) BX_CPP_AttrRegparmN(3);
|
||||
BX_MEM_SMF Bit8u* getHostMemAddr(BX_CPU_C *cpu, Bit32u a20Addr, unsigned op) BX_CPP_AttrRegparmN(3);
|
||||
BX_MEM_SMF bx_bool registerMemoryHandlers(memory_handler_t read_handler, void *read_param,
|
||||
memory_handler_t write_handler, void *write_param,
|
||||
unsigned long begin_addr, unsigned long end_addr);
|
||||
@ -113,3 +113,5 @@ BOCHSAPI extern BX_MEM_C *bx_mem_array[BX_ADDRESS_SPACES];
|
||||
#else
|
||||
# define BX_DBG_DIRTY_PAGE(page)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: misc_mem.cc,v 1.51 2004-10-21 18:20:40 sshwarts Exp $
|
||||
// $Id: misc_mem.cc,v 1.52 2004-10-29 21:15:48 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2002 MandrakeSoft S.A.
|
||||
@ -95,7 +95,7 @@ void BX_MEM_C::init_memory(int memsize)
|
||||
{
|
||||
int idx;
|
||||
|
||||
BX_DEBUG(("Init $Id: misc_mem.cc,v 1.51 2004-10-21 18:20:40 sshwarts Exp $"));
|
||||
BX_DEBUG(("Init $Id: misc_mem.cc,v 1.52 2004-10-29 21:15:48 sshwarts Exp $"));
|
||||
// you can pass 0 if memory has been allocated already through
|
||||
// the constructor, or the desired size of memory if it hasn't
|
||||
// BX_INFO(("%.2fMB", (float)(BX_MEM_THIS megabytes) ));
|
||||
@ -336,23 +336,24 @@ BX_MEM_C::dbg_crc32(unsigned long (*f)(unsigned char *buf, int len),
|
||||
return(1);
|
||||
}
|
||||
|
||||
//
|
||||
// Return a host address corresponding to the guest physical memory
|
||||
// address (with A20 already applied), given that the calling
|
||||
// code will perform an 'op' operation. This address will be
|
||||
// used for direct access to guest memory as an acceleration by
|
||||
// a few instructions, like REP {MOV, INS, OUTS, etc}.
|
||||
// Values of 'op' are { BX_READ, BX_WRITE, BX_RW }.
|
||||
//
|
||||
// The other assumption is that the calling code _only_ accesses memory
|
||||
// directly within the page that encompasses the address requested.
|
||||
//
|
||||
|
||||
Bit8u * BX_CPP_AttrRegparmN(3)
|
||||
BX_MEM_C::getHostMemAddr(BX_CPU_C *cpu, Bit32u a20Addr, unsigned op)
|
||||
// Return a host address corresponding to the guest physical memory
|
||||
// address (with A20 already applied), given that the calling
|
||||
// code will perform an 'op' operation. This address will be
|
||||
// used for direct access to guest memory as an acceleration by
|
||||
// a few instructions, like REP {MOV, INS, OUTS, etc}.
|
||||
// Values of 'op' are { BX_READ, BX_WRITE, BX_RW }.
|
||||
|
||||
// The other assumption is that the calling code _only_ accesses memory
|
||||
// directly within the page that encompasses the address requested.
|
||||
{
|
||||
if ( a20Addr >= BX_MEM_THIS len )
|
||||
return(NULL); // Error, requested addr is out of bounds.
|
||||
if (op == BX_READ) {
|
||||
if ( (a20Addr > 0x9ffff) && (a20Addr < 0xc0000) )
|
||||
return(NULL); // Vetoed! Mem mapped IO (VGA)
|
||||
|
||||
#if BX_SUPPORT_APIC
|
||||
bx_generic_apic_c *local_apic = &cpu->local_apic;
|
||||
if (local_apic->get_base () == (a20Addr & ~0xfff))
|
||||
@ -361,6 +362,10 @@ BX_MEM_C::getHostMemAddr(BX_CPU_C *cpu, Bit32u a20Addr, unsigned op)
|
||||
if (ioapic->get_base () == (a20Addr & ~0xfff))
|
||||
return(NULL); // Vetoed! IOAPIC address space
|
||||
#endif
|
||||
|
||||
if (op == BX_READ) {
|
||||
if ( (a20Addr > 0x9ffff) && (a20Addr < 0xc0000) )
|
||||
return(NULL); // Vetoed! Mem mapped IO (VGA)
|
||||
#if !BX_SUPPORT_PCI
|
||||
return( (Bit8u *) & vector[a20Addr] );
|
||||
#else
|
||||
@ -382,14 +387,6 @@ BX_MEM_C::getHostMemAddr(BX_CPU_C *cpu, Bit32u a20Addr, unsigned op)
|
||||
}
|
||||
else { // op == {BX_WRITE, BX_RW}
|
||||
Bit8u *retAddr;
|
||||
#if BX_SUPPORT_APIC
|
||||
bx_generic_apic_c *local_apic = &cpu->local_apic;
|
||||
if (local_apic->get_base () == (a20Addr & ~0xfff))
|
||||
return(NULL); // Vetoed! APIC address space
|
||||
bx_generic_apic_c *ioapic = bx_devices.ioapic;
|
||||
if (ioapic->get_base () == (a20Addr & ~0xfff))
|
||||
return(NULL); // Vetoed! IOAPIC address space
|
||||
#endif
|
||||
if ((a20Addr < 0xa0000) || (a20Addr > 0xfffff)) {
|
||||
retAddr = (Bit8u *) & vector[a20Addr];
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user