Trace cache instrumentation methods
Next step will be tracing cross non-taken branches
This commit is contained in:
Stanislav Shwartsman
parent
48d815427c
commit
db69a25c36
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.188 2007-12-09 18:36:03 sshwarts Exp $
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// $Id: cpu.cc,v 1.189 2007-12-14 11:27:44 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -57,25 +57,30 @@ void flushICaches(void)
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pageWriteStampTable.resetWriteStamps();
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}
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#define InstrumentICACHE 0
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#define InstrumentTRACECACHE 0
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#if InstrumentICACHE
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#if InstrumentTRACECACHE
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static Bit32u iCacheLookups=0;
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static Bit32u iCacheMisses=0;
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static Bit32u iCacheMergeTraces=0;
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static Bit32u iCacheLength[BX_MAX_TRACE_LENGTH+1];
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static Bit32u iCacheTraceLengh[BX_MAX_TRACE_LENGTH];
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#define InstrICache_StatsMask 0xfffffff
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#define InstrICache_Stats() {\
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if ((iCacheLookups & InstrICache_StatsMask) == 0) { \
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BX_INFO(("ICACHE lookups: %u, misses: %u, merges: %u, hit rate = %6.2f%% ", \
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BX_INFO(("ICACHE lookups: %u, misses: %u, merges: %u, hit rate = %3.2f%%", \
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(unsigned) iCacheLookups, \
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(unsigned) iCacheMisses, \
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(unsigned) iCacheMergeTraces, \
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(iCacheLookups-iCacheMisses) * 100.0 / iCacheLookups)); \
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for (unsigned trace_len_idx=0; trace_len_idx<BX_MAX_TRACE_LENGTH;trace_len_idx++) { \
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BX_INFO(("trace[%02d]: %u\t(%3.2f%%)", trace_len_idx+1, \
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iCacheTraceLengh[trace_len_idx], \
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iCacheTraceLengh[trace_len_idx] * 100.0/(iCacheLookups-iCacheMisses))); \
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iCacheTraceLengh[trace_len_idx] = 0; \
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} \
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iCacheLookups = iCacheMisses = iCacheMergeTraces = 0; \
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for (int i=0;i<=BX_MAX_TRACE_LENGTH;i++) iCacheLength[i] = 0; \
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} \
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}
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#define InstrICache_Increment(v) (v)++
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@ -85,7 +90,7 @@ static Bit32u iCacheLength[BX_MAX_TRACE_LENGTH+1];
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#define InstrICache_Increment(v)
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#endif
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#endif // BX_SUPPORT_ICACHE
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#endif // InstrumentTRACECACHE
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// Make code more tidy with a few macros.
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#if BX_SUPPORT_X86_64==0
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@ -108,6 +113,7 @@ bxICacheEntry_c* BX_CPU_C::fetchInstructionTrace(bxInstruction_c *iStorage, bx_a
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if ((trace->pAddr == pAddr) &&
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(trace->writeStamp == pageWriteStamp))
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{
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InstrICache_Increment(iCacheTraceLengh[trace->ilen-1]);
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return trace; // We are lucky - trace cache hit !
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}
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@ -172,8 +178,6 @@ bxICacheEntry_c* BX_CPU_C::fetchInstructionTrace(bxInstruction_c *iStorage, bx_a
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if (mergeTraces(trace, i, pAddr)) break;
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}
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InstrICache_Increment(iCacheLength[trace->ilen-1]);
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return trace;
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}
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@ -202,6 +206,30 @@ bx_bool BX_CPU_C::mergeTraces(bxICacheEntry_c *trace, bxInstruction_c *i, bx_phy
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return 0;
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}
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void BX_CPU_C::instrumentTraces(void)
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{
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Bit32u currPageWriteStamp = *(BX_CPU_THIS_PTR currPageWriteStampPtr);
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bxICacheEntry_c *e = BX_CPU_THIS_PTR iCache.entry;
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Bit32u trace_length[BX_MAX_TRACE_LENGTH], invalid_entries = 0;
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unsigned i;
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for (i=0; i < BX_MAX_TRACE_LENGTH; i++) trace_length[i] = 0;
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for (i=0; i<BxICacheEntries; i++, e++) {
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if (e->writeStamp == currPageWriteStamp)
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trace_length[e->ilen-1]++;
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else
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invalid_entries++;
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}
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for (i=0; i < BX_MAX_TRACE_LENGTH; i++) {
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BX_INFO(("traces[%02d]: %u\t%f%%", i+1,
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trace_length[i], trace_length[i]*100.0/BxICacheEntries));
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}
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BX_INFO(("invalid entries: %u\t%f%%",
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invalid_entries, invalid_entries*100.0/BxICacheEntries));
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}
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#else
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bxInstruction_c* BX_CPU_C::fetchInstruction(bxInstruction_c *iStorage, bx_address eipBiased)
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.386 2007-12-09 18:36:04 sshwarts Exp $
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// $Id: cpu.h,v 1.387 2007-12-14 11:27:44 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -2939,6 +2939,7 @@ public: // for now...
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#if BX_SUPPORT_TRACE_CACHE
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BX_SMF bxICacheEntry_c* fetchInstructionTrace(bxInstruction_c *, bx_address);
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BX_SMF bx_bool mergeTraces(bxICacheEntry_c *trace, bxInstruction_c *i, bx_phy_address pAddr);
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BX_SMF void instrumentTraces(void);
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#else
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BX_SMF bxInstruction_c* fetchInstruction(bxInstruction_c *, bx_address);
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#endif
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.187 2007-12-14 10:15:12 sshwarts Exp $
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// $Id: proc_ctrl.cc,v 1.188 2007-12-14 11:27:44 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -189,8 +189,6 @@ void BX_CPU_C::CLFLUSH(bxInstruction_c *i)
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#if BX_CPU_LEVEL >= 3
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void BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
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{
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Bit32u val_32;
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if (!real_mode() && CPL!=0) {
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BX_ERROR(("MOV_DdRd: CPL!=0 not in real mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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@ -202,15 +200,15 @@ void BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
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* reg field specifies which special register
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*/
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invalidate_prefetch_q();
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/* This instruction is always treated as a register-to-register,
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* regardless of the encoding of the MOD field in the MODRM byte.
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*/
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if (!i->modC0())
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BX_PANIC(("MOV_DdRd(): rm field not a register!"));
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invalidate_prefetch_q();
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val_32 = BX_READ_32BIT_REG(i->rm());
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Bit32u val_32 = BX_READ_32BIT_REG(i->rm());
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switch (i->nnn()) {
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case 0: // DR0
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@ -325,6 +323,8 @@ void BX_CPU_C::MOV_RdDd(bxInstruction_c *i)
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/* This instruction is always treated as a register-to-register,
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* regardless of the encoding of the MOD field in the MODRM byte.
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*/
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if (!i->modC0())
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BX_PANIC(("MOV_RdDd(): rm field not a register!"));
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switch (i->nnn()) {
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case 0: // DR0
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@ -389,18 +389,20 @@ void BX_CPU_C::MOV_DqRq(bxInstruction_c *i)
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* reg field specifies which special register
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*/
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/* This instruction is always treated as a register-to-register,
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* regardless of the encoding of the MOD field in the MODRM byte.
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*/
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invalidate_prefetch_q();
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/* #GP(0) if CPL is not 0 */
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if (CPL != 0) {
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BX_ERROR(("MOV_DqRq: #GP(0) if CPL is not 0"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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invalidate_prefetch_q();
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/* This instruction is always treated as a register-to-register,
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* regardless of the encoding of the MOD field in the MODRM byte.
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*/
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if (!i->modC0())
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BX_PANIC(("MOV_DqRq(): rm field not a register!"));
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Bit64u val_64 = BX_READ_64BIT_REG(i->rm());
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switch (i->nnn()) {
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@ -497,16 +499,18 @@ void BX_CPU_C::MOV_RqDq(bxInstruction_c *i)
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BX_ASSERT(protected_mode());
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/* This instruction is always treated as a register-to-register,
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* regardless of the encoding of the MOD field in the MODRM byte.
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*/
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/* #GP(0) if CPL is not 0 */
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if (CPL != 0) {
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BX_ERROR(("MOV_RqDq: #GP(0) if CPL is not 0"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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/* This instruction is always treated as a register-to-register,
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* regardless of the encoding of the MOD field in the MODRM byte.
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*/
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if (!i->modC0())
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BX_PANIC(("MOV_RqDq(): rm field not a register!"));
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switch (i->nnn()) {
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case 0: // DR0
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val_64 = BX_CPU_THIS_PTR dr0;
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@ -558,9 +562,6 @@ void BX_CPU_C::MOV_RqDq(bxInstruction_c *i)
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void BX_CPU_C::MOV_CdRd(bxInstruction_c *i)
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{
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// mov general register data to control register
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Bit32u val_32;
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if (!real_mode() && CPL!=0) {
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BX_ERROR(("MOV_CdRd: CPL!=0 not in real mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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@ -572,13 +573,15 @@ void BX_CPU_C::MOV_CdRd(bxInstruction_c *i)
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* reg field specifies which special register
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*/
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invalidate_prefetch_q();
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/* This instruction is always treated as a register-to-register,
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* regardless of the encoding of the MOD field in the MODRM byte.
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*/
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if (!i->modC0())
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BX_PANIC(("MOV_CdRd(): rm field not a register!"));
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invalidate_prefetch_q();
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val_32 = BX_READ_32BIT_REG(i->rm());
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Bit32u val_32 = BX_READ_32BIT_REG(i->rm());
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switch (i->nnn()) {
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case 0: // CR0 (MSW)
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@ -674,9 +677,6 @@ void BX_CPU_C::MOV_RdCd(bxInstruction_c *i)
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#if BX_SUPPORT_X86_64
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void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
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{
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// mov general register data to control register
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Bit64u val_64;
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BX_ASSERT(protected_mode());
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/* NOTES:
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@ -685,6 +685,12 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
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* reg field specifies which special register
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*/
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/* #GP(0) if CPL is not 0 */
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if (CPL!=0) {
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BX_ERROR(("MOV_CqRq: #GP(0) if CPL is not 0"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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/* This instruction is always treated as a register-to-register,
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* regardless of the encoding of the MOD field in the MODRM byte.
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*/
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@ -693,13 +699,7 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
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invalidate_prefetch_q();
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/* #GP(0) if CPL is not 0 */
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if (CPL!=0) {
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BX_ERROR(("MOV_CqRq: #GP(0) if CPL is not 0"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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val_64 = BX_READ_64BIT_REG(i->rm());
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Bit64u val_64 = BX_READ_64BIT_REG(i->rm());
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switch (i->nnn()) {
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case 0: // CR0 (MSW)
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@ -760,18 +760,18 @@ void BX_CPU_C::MOV_RqCq(bxInstruction_c *i)
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* reg field specifies which special register
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*/
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/* This instruction is always treated as a register-to-register,
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* regardless of the encoding of the MOD field in the MODRM byte.
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*/
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if (!i->modC0())
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BX_PANIC(("MOV_RqCq(): rm field not a register!"));
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/* #GP(0) if CPL is not 0 */
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if (CPL!=0) {
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BX_ERROR(("MOV_RqCq: #GP(0) if CPL is not 0"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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/* This instruction is always treated as a register-to-register,
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* regardless of the encoding of the MOD field in the MODRM byte.
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*/
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if (!i->modC0())
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BX_PANIC(("MOV_RqCq(): rm field not a register!"));
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switch (i->nnn()) {
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case 0: // CR0 (MSW)
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val_64 = BX_CPU_THIS_PTR cr0.val32;
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