a bit simplify and optimize shift instructions
print failed segment info in check_cs - more debug info
This commit is contained in:
Stanislav Shwartsman
parent
72d72c92d4
commit
eee1a9030d
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.405 2007-12-30 17:53:12 sshwarts Exp $
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// $Id: cpu.h,v 1.406 2007-12-30 20:16:34 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -3887,18 +3887,19 @@ IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
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// specify which kinds of immediate data a required by instruction.
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#define BxImmediate 0x000f // bits 3..0: any immediate
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#define BxImmediate_Ib 0x0001 // 8 bit
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#define BxImmediate_Ib_SE 0x0002 // sign extend to OS size
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#define BxImmediate_Iw 0x0003 // 16 bit
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#define BxImmediate_IbIb 0x0004 // SSE4A
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#define BxImmediate_IwIb 0x0005 // enter_IwIb
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#define BxImmediate_IvIw 0x0006 // call_Ap, not encodable in 64-bit mode
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#define BxImmediate_Id 0x0007 // 32 bit
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#define BxImmediate_O 0x0008 // MOV_ALOd, mov_OdAL, mov_eAXOv, mov_OveAX
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#define BxImmediate_BrOff8 0x0009 // Relative branch offset byte
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#define BxImmediate_BrOff16 0x000A // Relative branch offset word, not encodable in 64-bit mode
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#define BxImmediate_I1 0x0001 // imm8 = 1
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#define BxImmediate_Ib 0x0002 // 8 bit
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#define BxImmediate_Ib_SE 0x0003 // sign extend to OS size
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#define BxImmediate_Iw 0x0004 // 16 bit
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#define BxImmediate_IbIb 0x0005 // SSE4A
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#define BxImmediate_IwIb 0x0006 // enter_IwIb
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#define BxImmediate_IvIw 0x0007 // call_Ap, not encodable in 64-bit mode
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#define BxImmediate_Id 0x0008 // 32 bit
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#define BxImmediate_O 0x0009 // MOV_ALOd, mov_OdAL, mov_eAXOv, mov_OveAX
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#define BxImmediate_BrOff8 0x000A // Relative branch offset byte
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#define BxImmediate_BrOff16 0x000B // Relative branch offset word, not encodable in 64-bit mode
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#if BX_SUPPORT_X86_64
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#define BxImmediate_Iq 0x000B // 64 bit override
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#define BxImmediate_Iq 0x000C // 64 bit override
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#endif
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#define BxImmediate_BrOff32 BxImmediate_Id // Relative branch offset dword
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: ctrl_xfer16.cc,v 1.49 2007-12-20 20:58:37 sshwarts Exp $
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// $Id: ctrl_xfer16.cc,v 1.50 2007-12-30 20:16:34 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -48,7 +48,7 @@ void BX_CPU_C::RETnear16_Iw(bxInstruction_c *i)
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Bit16u return_IP = pop_16();
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if (return_IP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
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if (return_IP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
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{
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BX_ERROR(("retnear_iw: IP > limit"));
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exception(BX_GP_EXCEPTION, 0, 0);
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@ -79,7 +79,7 @@ void BX_CPU_C::RETnear16(bxInstruction_c *i)
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Bit16u return_IP = pop_16();
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if (return_IP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
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if (return_IP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
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{
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BX_ERROR(("retnear: IP > limit"));
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exception(BX_GP_EXCEPTION, 0, 0);
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@ -1,5 +1,5 @@
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////////////////////////////////////////////////////////////////////////
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// $Id: ctrl_xfer_pro.cc,v 1.64 2007-12-14 20:41:09 sshwarts Exp $
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// $Id: ctrl_xfer_pro.cc,v 1.65 2007-12-30 20:16:34 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -43,18 +43,18 @@ void BX_CPU_C::check_cs(bx_descriptor_t *descriptor, Bit16u cs_raw, Bit8u check_
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if (descriptor->valid==0 || descriptor->segment==0 ||
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IS_DATA_SEGMENT(descriptor->type))
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{
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BX_ERROR(("check_cs: not a valid code segment !"));
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BX_ERROR(("check_cs(0x%04x): not a valid code segment !", cs_raw));
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exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
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}
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#if BX_SUPPORT_X86_64
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if (descriptor->u.segment.l) {
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if (! BX_CPU_THIS_PTR efer.lma) {
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BX_PANIC(("check_cs: attempt to jump to long mode without enabling EFER.LMA !"));
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BX_PANIC(("check_cs(0x%04x): attempt to jump to long mode without enabling EFER.LMA !", cs_raw));
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}
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if (descriptor->u.segment.d_b) {
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BX_ERROR(("check_cs: Both L and D bits enabled for segment descriptor !"));
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BX_ERROR(("check_cs(0x%04x): Both L and D bits enabled for segment descriptor !", cs_raw));
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exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
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}
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}
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@ -63,27 +63,27 @@ void BX_CPU_C::check_cs(bx_descriptor_t *descriptor, Bit16u cs_raw, Bit8u check_
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// if non-conforming, code segment descriptor DPL must = CPL else #GP(selector)
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if (IS_CODE_SEGMENT_NON_CONFORMING(descriptor->type)) {
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if (descriptor->dpl != check_cpl) {
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BX_ERROR(("check_cs: non-conforming code seg descriptor dpl != cpl"));
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BX_ERROR(("check_cs(0x%04x): non-conforming code seg descriptor dpl != cpl", cs_raw));
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exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
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}
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/* RPL of destination selector must be <= CPL else #GP(selector) */
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if (check_rpl > check_cpl) {
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BX_ERROR(("check_cs: non-conforming code seg selector rpl > cpl"));
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BX_ERROR(("check_cs(0x%04x): non-conforming code seg selector rpl > cpl", cs_raw));
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exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
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}
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}
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// if conforming, then code segment descriptor DPL must <= CPL else #GP(selector)
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else {
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if (descriptor->dpl > check_cpl) {
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BX_ERROR(("check_cs: conforming code seg descriptor dpl > cpl"));
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BX_ERROR(("check_cs(0x%04x): conforming code seg descriptor dpl > cpl", cs_raw));
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exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
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}
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}
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// code segment must be present else #NP(selector)
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if (! descriptor->p) {
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BX_ERROR(("check_cs: code segment not present !"));
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BX_ERROR(("check_cs(0x%04x): code segment not present !", cs_raw));
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exception(BX_NP_EXCEPTION, cs_raw & 0xfffc, 0);
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}
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.156 2007-12-22 17:17:40 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.157 2007-12-30 20:16:34 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -392,8 +392,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* CD /wr */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
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/* CE /wr */ { BxTraceEnd, &BX_CPU_C::INTO },
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/* CF /wr */ { BxTraceEnd, &BX_CPU_C::IRET16 },
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/* D0 /wr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D1 /wr */ { BxGroup2, NULL, BxOpcodeInfoG2Ew },
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/* D0 /wr */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Eb },
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/* D1 /wr */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Ew },
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/* D2 /wr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D3 /wr */ { BxGroup2, NULL, BxOpcodeInfoG2Ew },
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/* D4 /wr */ { BxImmediate_Ib, &BX_CPU_C::AAM },
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@ -956,8 +956,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* CD /dr */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
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/* CE /dr */ { BxTraceEnd, &BX_CPU_C::INTO },
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/* CF /dr */ { BxTraceEnd, &BX_CPU_C::IRET32 },
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/* D0 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D1 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Ed },
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/* D0 /dr */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Eb },
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/* D1 /dr */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Ed },
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/* D2 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D3 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Ed },
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/* D4 /dr */ { BxImmediate_Ib, &BX_CPU_C::AAM },
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@ -1527,8 +1527,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* CD /wm */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
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/* CE /wm */ { BxTraceEnd, &BX_CPU_C::INTO },
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/* CF /wm */ { BxTraceEnd, &BX_CPU_C::IRET16 },
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/* D0 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D1 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Ew },
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/* D0 /wm */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Eb },
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/* D1 /wm */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Ew },
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/* D2 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D3 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Ew },
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/* D4 /wm */ { BxImmediate_Ib, &BX_CPU_C::AAM },
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@ -2091,8 +2091,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* CD /dm */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
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/* CE /dm */ { BxTraceEnd, &BX_CPU_C::INTO },
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/* CF /dm */ { BxTraceEnd, &BX_CPU_C::IRET32 },
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/* D0 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D1 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Ed },
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/* D0 /dm */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Eb },
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/* D1 /dm */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Ed },
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/* D2 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D3 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Ed },
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/* D4 /dm */ { BxImmediate_Ib, &BX_CPU_C::AAM },
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@ -2806,6 +2806,9 @@ modrm_done:
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imm_mode = attr & BxImmediate;
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if (imm_mode) {
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switch (imm_mode) {
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case BxImmediate_I1:
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i->modRMForm.Ib = 1;
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break;
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case BxImmediate_Ib:
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if (ilen < remain) {
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i->modRMForm.Ib = *iptr;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode64.cc,v 1.163 2007-12-22 17:17:40 sshwarts Exp $
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// $Id: fetchdecode64.cc,v 1.164 2007-12-30 20:16:34 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -381,8 +381,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
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/* CD /wr */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
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/* CE /wr */ { 0, &BX_CPU_C::BxError },
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/* CF /wr */ { BxTraceEnd, &BX_CPU_C::IRET64 },
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/* D0 /wr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D1 /wr */ { BxGroup2, NULL, BxOpcodeInfoG2Ew },
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/* D0 /wr */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Eb },
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/* D1 /wr */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Ew },
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/* D2 /wr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D3 /wr */ { BxGroup2, NULL, BxOpcodeInfoG2Ew },
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/* D4 /wr */ { 0, &BX_CPU_C::BxError },
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@ -910,8 +910,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
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/* CD /dr */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
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/* CE /dr */ { 0, &BX_CPU_C::BxError },
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/* CF /dr */ { BxTraceEnd, &BX_CPU_C::IRET64 },
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/* D0 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D1 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Ed },
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/* D0 /dr */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Eb },
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/* D1 /dr */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Ed },
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/* D2 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D3 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Ed },
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/* D4 /dr */ { 0, &BX_CPU_C::BxError },
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@ -1439,8 +1439,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
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/* CD /qr */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
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/* CE /qr */ { 0, &BX_CPU_C::BxError },
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/* CF /qr */ { BxTraceEnd, &BX_CPU_C::IRET64 },
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/* D0 /qr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D1 /qr */ { BxGroup2, NULL, BxOpcodeInfo64G2Eq },
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/* D0 /qr */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Eb },
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/* D1 /qr */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfo64G2Eq },
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/* D2 /qr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D3 /qr */ { BxGroup2, NULL, BxOpcodeInfo64G2Eq },
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/* D4 /qr */ { 0, &BX_CPU_C::BxError },
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@ -1974,8 +1974,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
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/* CD /wm */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
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/* CE /wm */ { 0, &BX_CPU_C::BxError },
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/* CF /wm */ { BxTraceEnd, &BX_CPU_C::IRET64 },
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/* D0 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D1 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Ew },
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/* D0 /wm */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Eb },
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/* D1 /wm */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Ew },
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/* D2 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D3 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Ew },
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/* D4 /wm */ { 0, &BX_CPU_C::BxError },
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@ -2503,8 +2503,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
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/* CD /dm */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
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/* CE /dm */ { 0, &BX_CPU_C::BxError },
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/* CF /dm */ { BxTraceEnd, &BX_CPU_C::IRET64 },
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/* D0 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D1 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Ed },
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/* D0 /dm */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Eb },
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/* D1 /dm */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Ed },
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/* D2 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D3 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Ed },
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/* D4 /dm */ { 0, &BX_CPU_C::BxError },
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@ -3032,8 +3032,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
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/* CD /qm */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
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/* CE /qm */ { 0, &BX_CPU_C::BxError },
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/* CF /qm */ { BxTraceEnd, &BX_CPU_C::IRET64 },
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/* D0 /qm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D1 /qm */ { BxGroup2, NULL, BxOpcodeInfo64G2Eq },
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/* D0 /qm */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfoG2Eb },
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/* D1 /qm */ { BxGroup2 | BxImmediate_I1, NULL, BxOpcodeInfo64G2Eq },
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/* D2 /qm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
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/* D3 /qm */ { BxGroup2, NULL, BxOpcodeInfo64G2Eq },
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/* D4 /qm */ { 0, &BX_CPU_C::BxError },
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@ -3762,6 +3762,9 @@ modrm_done:
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imm_mode = attr & BxImmediate;
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if (imm_mode) {
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switch (imm_mode) {
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case BxImmediate_I1:
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i->modRMForm.Ib = 1;
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break;
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case BxImmediate_Ib:
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if (ilen < remain) {
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i->modRMForm.Ib = *iptr;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: mult16.cc,v 1.25 2007-12-20 20:58:37 sshwarts Exp $
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// $Id: mult16.cc,v 1.26 2007-12-30 20:16:35 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -225,7 +225,7 @@ void BX_CPU_C::IMUL_GwEw(bxInstruction_c *i)
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op1_16 = BX_READ_16BIT_REG(i->nnn());
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Bit32s product_32 = op1_16 * op2_16;
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Bit32s product_32 = op1_16 * op2_16;
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Bit16u product_16 = (product_32 & 0xFFFF);
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/* now write product back to destination */
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: shift16.cc,v 1.39 2007-12-20 20:58:37 sshwarts Exp $
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// $Id: shift16.cc,v 1.40 2007-12-30 20:16:35 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -149,12 +149,10 @@ void BX_CPU_C::ROL_Ew(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned bit0, bit15;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // 0xd3
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -199,12 +197,10 @@ void BX_CPU_C::ROR_Ew(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned bit14, bit15;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // 0xd3
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -249,12 +245,10 @@ void BX_CPU_C::RCL_Ew(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned of, cf;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // 0xd3
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count = (count & 0x1f) % 17;
|
||||
|
||||
@ -299,12 +293,10 @@ void BX_CPU_C::RCR_Ew(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned of, cf;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // 0xd3
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count = (count & 0x1f) % 17;
|
||||
|
||||
@ -341,12 +333,10 @@ void BX_CPU_C::SHL_Ew(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned of = 0, cf = 0;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // 0xd3
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f; /* use only 5 LSB's */
|
||||
|
||||
@ -388,12 +378,10 @@ void BX_CPU_C::SHR_Ew(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned of, cf;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // 0xd3
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f; /* use only 5 LSB's */
|
||||
|
||||
@ -432,12 +420,10 @@ void BX_CPU_C::SAR_Ew(bxInstruction_c *i)
|
||||
Bit16u op1_16, result_16;
|
||||
unsigned count, cf;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // 0xd3
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f; /* use only 5 LSB's */
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: shift32.cc,v 1.38 2007-12-20 20:58:37 sshwarts Exp $
|
||||
// $Id: shift32.cc,v 1.39 2007-12-30 20:16:35 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -124,12 +124,12 @@ void BX_CPU_C::ROL_Ed(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned bit0, bit31;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x1f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -164,12 +164,12 @@ void BX_CPU_C::ROR_Ed(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned bit31, bit30;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x1f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -204,12 +204,12 @@ void BX_CPU_C::RCL_Ed(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x1f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -249,12 +249,12 @@ void BX_CPU_C::RCR_Ed(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x1f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -295,12 +295,12 @@ void BX_CPU_C::SHL_Ed(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x1f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -336,12 +336,12 @@ void BX_CPU_C::SHR_Ed(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned of, cf;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x1f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -378,12 +378,12 @@ void BX_CPU_C::SAR_Ed(bxInstruction_c *i)
|
||||
Bit32u op1_32, result_32;
|
||||
unsigned count;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x1f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x1f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: shift64.cc,v 1.28 2007-12-20 20:58:37 sshwarts Exp $
|
||||
// $Id: shift64.cc,v 1.29 2007-12-30 20:16:35 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -126,12 +126,12 @@ void BX_CPU_C::ROL_Eq(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned bit0, bit63;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x3f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -166,12 +166,12 @@ void BX_CPU_C::ROR_Eq(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned bit62, bit63;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x3f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -206,12 +206,12 @@ void BX_CPU_C::RCL_Eq(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x3f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -251,12 +251,12 @@ void BX_CPU_C::RCR_Eq(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned of, cf;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x3f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -296,12 +296,12 @@ void BX_CPU_C::SHL_Eq(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x3f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -337,12 +337,12 @@ void BX_CPU_C::SHR_Eq(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x3f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -379,12 +379,12 @@ void BX_CPU_C::SAR_Eq(bxInstruction_c *i)
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
|
||||
if (i->b1() == 0xc1)
|
||||
count = i->Ib() & 0x3f;
|
||||
else if (i->b1() == 0xd1)
|
||||
count = 1;
|
||||
else // (i->b1() == 0xd3)
|
||||
count = CL & 0x3f;
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: shift8.cc,v 1.32 2007-12-20 20:58:37 sshwarts Exp $
|
||||
// $Id: shift8.cc,v 1.33 2007-12-30 20:16:35 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -38,12 +38,10 @@ void BX_CPU_C::ROL_Eb(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned bit0, bit7;
|
||||
|
||||
if (i->b1() == 0xc0)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd0)
|
||||
count = 1;
|
||||
else // 0xd2
|
||||
if (i->b1() == 0xd2)
|
||||
count = CL;
|
||||
else // 0xc0 or 0xd0
|
||||
count = i->Ib();
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -91,12 +89,10 @@ void BX_CPU_C::ROR_Eb(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned bit6, bit7;
|
||||
|
||||
if (i->b1() == 0xc0)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd0)
|
||||
count = 1;
|
||||
else // 0xd2
|
||||
if (i->b1() == 0xd2)
|
||||
count = CL;
|
||||
else // 0xc0 or 0xd0
|
||||
count = i->Ib();
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -145,14 +141,10 @@ void BX_CPU_C::RCL_Eb(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned of, cf;
|
||||
|
||||
if (i->b1() == 0xc0)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd0)
|
||||
count = 1;
|
||||
else // 0xd2
|
||||
if (i->b1() == 0xd2)
|
||||
count = CL;
|
||||
|
||||
count = (count & 0x1f) % 9;
|
||||
else // 0xc0 or 0xd0
|
||||
count = i->Ib();
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -162,6 +154,8 @@ void BX_CPU_C::RCL_Eb(bxInstruction_c *i)
|
||||
/* pointer, segment address pair */
|
||||
op1_8 = read_RMW_virtual_byte(i->seg(), RMAddr(i));
|
||||
}
|
||||
|
||||
count = (count & 0x1f) % 9;
|
||||
|
||||
if (! count) return;
|
||||
|
||||
@ -192,14 +186,10 @@ void BX_CPU_C::RCR_Eb(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xc0)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd0)
|
||||
count = 1;
|
||||
else // 0xd2
|
||||
if (i->b1() == 0xd2)
|
||||
count = CL;
|
||||
|
||||
count = (count & 0x1f) % 9;
|
||||
else // 0xc0 or 0xd0
|
||||
count = i->Ib();
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -210,6 +200,8 @@ void BX_CPU_C::RCR_Eb(bxInstruction_c *i)
|
||||
op1_8 = read_RMW_virtual_byte(i->seg(), RMAddr(i));
|
||||
}
|
||||
|
||||
count = (count & 0x1f) % 9;
|
||||
|
||||
if (! count) return;
|
||||
|
||||
result_8 = (op1_8 >> count) | (getB_CF() << (8 - count)) |
|
||||
@ -234,12 +226,10 @@ void BX_CPU_C::SHL_Eb(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned of = 0, cf = 0;
|
||||
|
||||
if (i->b1() == 0xc0)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd0)
|
||||
count = 1;
|
||||
else // 0xd2
|
||||
if (i->b1() == 0xd2)
|
||||
count = CL;
|
||||
else // 0xc0 or 0xd0
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f;
|
||||
|
||||
@ -281,12 +271,10 @@ void BX_CPU_C::SHR_Eb(bxInstruction_c *i)
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xc0)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd0)
|
||||
count = 1;
|
||||
else // 0xd2
|
||||
if (i->b1() == 0xd2)
|
||||
count = CL;
|
||||
else // 0xc0 or 0xd0
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f;
|
||||
|
||||
@ -325,12 +313,10 @@ void BX_CPU_C::SAR_Eb(bxInstruction_c *i)
|
||||
Bit8u op1_8, result_8;
|
||||
unsigned count, cf;
|
||||
|
||||
if (i->b1() == 0xc0)
|
||||
count = i->Ib();
|
||||
else if (i->b1() == 0xd0)
|
||||
count = 1;
|
||||
else // 0xd2
|
||||
if (i->b1() == 0xd2)
|
||||
count = CL;
|
||||
else // 0xc0 or 0xd0
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x1f;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user