sepatate activity state from debug trap
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.261 2009-01-27 21:13:38 sshwarts Exp $
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// $Id: cpu.cc,v 1.262 2009-01-29 20:27:57 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -429,25 +429,25 @@ unsigned BX_CPU_C::handleAsyncEvent(void)
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//
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// This area is where we process special conditions and events.
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//
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if (BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_SPECIAL) {
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// I made up the bitmask above to mean HALT state.
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// for one processor, pass the time as quickly as possible until
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if (BX_CPU_THIS_PTR activity_state) {
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// For one processor, pass the time as quickly as possible until
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// an interrupt wakes up the CPU.
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while (1)
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{
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if ((BX_CPU_INTR && (BX_CPU_THIS_PTR get_IF() || (BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_MWAIT_IF))) ||
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if ((BX_CPU_INTR && (BX_CPU_THIS_PTR get_IF() ||
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(BX_CPU_THIS_PTR activity_state == BX_ACTIVITY_STATE_MWAIT_IF))) ||
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BX_CPU_THIS_PTR pending_NMI || BX_CPU_THIS_PTR pending_SMI)
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{
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// interrupt ends the HALT condition
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#if BX_SUPPORT_MONITOR_MWAIT
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if (BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_MWAIT)
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if (BX_CPU_THIS_PTR activity_state >= BX_ACTIVITY_STATE_MWAIT)
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BX_MEM(0)->clear_monitor(BX_CPU_THIS_PTR bx_cpuid);
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#endif
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BX_CPU_THIS_PTR debug_trap = 0; // clear traps for after resume
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BX_CPU_THIS_PTR activity_state = 0;
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BX_CPU_THIS_PTR inhibit_mask = 0; // clear inhibits for after resume
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break;
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}
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if ((BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_SPECIAL) == 0) {
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if (BX_CPU_THIS_PTR activity_state == BX_ACTIVITY_STATE_ACTIVE) {
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BX_INFO(("handleAsyncEvent: reset detected in HLT state"));
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break;
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}
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@ -821,8 +821,8 @@ void BX_CPU_C::boundaryFetch(const Bit8u *fetchPtr, unsigned remainingInPage, bx
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void BX_CPU_C::deliver_SIPI(unsigned vector)
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{
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if (BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_SPECIAL) {
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BX_CPU_THIS_PTR debug_trap &= ~BX_DEBUG_TRAP_SPECIAL;
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if (BX_CPU_THIS_PTR activity_state == BX_ACTIVITY_STATE_WAIT_FOR_SIPI) {
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BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_ACTIVE;
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RIP = 0;
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], vector*0x100);
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BX_INFO(("%s started up at %04X:%08X by APIC",
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.563 2009-01-27 21:13:38 sshwarts Exp $
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// $Id: cpu.h,v 1.564 2009-01-29 20:27:57 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -366,7 +366,6 @@ enum {
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#define BX_MODE_LONG_64 0x4 // EFER.LMA = 1, CR0.PE=1, CS.L=1
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extern const char* cpu_mode_string(unsigned cpu_mode);
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extern const char* cpu_state_string(Bit32u debug_trap);
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#if BX_SUPPORT_X86_64
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#define IsCanonical(offset) ((Bit64u)((((Bit64s)(offset)) >> (BX_LIN_ADDRESS_WIDTH-1)) + 1) < 2)
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@ -904,13 +903,13 @@ public: // for now...
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* 0 if current CS:IP caused exception */
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unsigned errorno; /* signal exception during instruction emulation */
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#define BX_DEBUG_TRAP_HALT (0x80000000)
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#define BX_DEBUG_TRAP_SHUTDOWN (0x40000000)
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#define BX_DEBUG_TRAP_WAIT_FOR_SIPI (0x20000000)
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#define BX_DEBUG_TRAP_MWAIT (0x10000000)
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#define BX_DEBUG_TRAP_MWAIT_IF (0x18000000)
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// combine all possible states
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#define BX_DEBUG_TRAP_SPECIAL (0xf8000000)
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#define BX_ACTIVITY_STATE_ACTIVE (0)
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#define BX_ACTIVITY_STATE_HLT (1)
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#define BX_ACTIVITY_STATE_SHUTDOWN (2)
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#define BX_ACTIVITY_STATE_WAIT_FOR_SIPI (3)
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#define BX_ACTIVITY_STATE_MWAIT (4)
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#define BX_ACTIVITY_STATE_MWAIT_IF (5)
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unsigned activity_state;
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Bit32u debug_trap; // holds DR6 value (16bit) to be set as well
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volatile Bit32u async_event;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: debugstuff.cc,v 1.101 2009-01-19 19:01:03 sshwarts Exp $
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// $Id: debugstuff.cc,v 1.102 2009-01-29 20:27:57 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -96,32 +96,26 @@ const char* cpu_mode_string(unsigned cpu_mode)
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return cpu_mode_name[cpu_mode];
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}
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const char* cpu_state_string(Bit32u debug_trap)
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const char* cpu_state_string(unsigned state)
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{
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unsigned cpu_state = 5; // unknown state
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static const char *cpu_state_name[] = {
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"active",
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"executing mwait",
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"waiting for SIPI",
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"in shutdown",
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"halted",
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"in shutdown",
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"waiting for SIPI",
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"executing mwait",
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"executing mwait inhibit interrups",
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"unknown state"
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};
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if(debug_trap & BX_DEBUG_TRAP_HALT) cpu_state = 4;
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else if (debug_trap & BX_DEBUG_TRAP_SHUTDOWN) cpu_state = 3;
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else if (debug_trap & BX_DEBUG_TRAP_WAIT_FOR_SIPI) cpu_state = 2;
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else if (debug_trap & BX_DEBUG_TRAP_MWAIT) cpu_state = 1;
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else if (debug_trap & BX_DEBUG_TRAP_SPECIAL) cpu_state = 5;
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else cpu_state = 0;
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return cpu_state_name[cpu_state];
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if(state >= 6) state = 6;
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return cpu_state_name[state];
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}
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void BX_CPU_C::debug(bx_address offset)
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{
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BX_INFO(("CPU is in %s (%s)", cpu_mode_string(BX_CPU_THIS_PTR get_cpu_mode()),
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cpu_state_string(BX_CPU_THIS_PTR debug_trap)));
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cpu_state_string(BX_CPU_THIS_PTR activity_state)));
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BX_INFO(("CS.d_b = %u bit",
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b ? 32 : 16));
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BX_INFO(("SS.d_b = %u bit",
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: init.cc,v 1.192 2009-01-23 17:48:38 sshwarts Exp $
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// $Id: init.cc,v 1.193 2009-01-29 20:27:57 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -318,6 +318,7 @@ void BX_CPU_C::register_state(void)
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BXRS_PARAM_SPECIAL32(cpu, cpuid_std, param_save_handler, param_restore_handler);
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BXRS_PARAM_SPECIAL32(cpu, cpuid_ext, param_save_handler, param_restore_handler);
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BXRS_DEC_PARAM_SIMPLE(cpu, cpu_mode);
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BXRS_HEX_PARAM_SIMPLE(cpu, activity_state);
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BXRS_HEX_PARAM_SIMPLE(cpu, inhibit_mask);
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BXRS_HEX_PARAM_SIMPLE(cpu, debug_trap);
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#if BX_SUPPORT_X86_64
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@ -733,6 +734,7 @@ void BX_CPU_C::reset(unsigned source)
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BX_CPU_THIS_PTR setEFlags(0x2); // Bit1 is always set
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BX_CPU_THIS_PTR inhibit_mask = 0;
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BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_ACTIVE;
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BX_CPU_THIS_PTR debug_trap = 0;
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/* instruction pointer */
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@ -1020,7 +1022,7 @@ void BX_CPU_C::reset(unsigned source)
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// it's an application processor, halt until IPI is heard.
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BX_CPU_THIS_PTR msr.apicbase &= ~0x0100; /* clear bit 8 BSP */
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BX_INFO(("CPU[%d] is an application processor. Halting until IPI.", apic_id));
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debug_trap |= BX_DEBUG_TRAP_WAIT_FOR_SIPI;
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activity_state = BX_ACTIVITY_STATE_WAIT_FOR_SIPI;
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async_event = 1;
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}
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#endif
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.277 2009-01-27 20:29:05 sshwarts Exp $
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// $Id: proc_ctrl.cc,v 1.278 2009-01-29 20:27:57 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -77,7 +77,7 @@ void BX_CPU_C::shutdown(void)
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BX_CPU_THIS_PTR clear_IF();
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// artificial trap bit, why use another variable.
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BX_CPU_THIS_PTR debug_trap |= BX_DEBUG_TRAP_SHUTDOWN; // artificial trap
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BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_HLT;
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BX_CPU_THIS_PTR async_event = 1; // so processor knows to check
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// Execution of this instruction completes. The processor
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// will remain in a halt state until one of the above conditions
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@ -115,7 +115,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HLT(bxInstruction_c *i)
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// following HLT.
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// artificial trap bit, why use another variable.
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BX_CPU_THIS_PTR debug_trap |= BX_DEBUG_TRAP_HALT; // artificial trap
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BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_HLT;
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BX_CPU_THIS_PTR async_event = 1; // so processor knows to check
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// Execution of this instruction completes. The processor
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// will remain in a halt state until one of the above conditions
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@ -1457,8 +1457,8 @@ void BX_CPU_C::check_monitor(bx_phy_address begin_addr, unsigned len)
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{
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if (is_monitor(begin_addr, len)) {
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// wakeup from MWAIT state
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BX_ASSERT(BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_MWAIT);
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BX_CPU_THIS_PTR debug_trap &= ~BX_DEBUG_TRAP_SPECIAL;
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BX_ASSERT(BX_CPU_THIS_PTR activity_state >= BX_ACTIVITY_STATE_MWAIT);
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BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_ACTIVE;
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// clear monitor
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BX_MEM(0)->clear_monitor(BX_CPU_THIS_PTR bx_cpuid);
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BX_CPU_THIS_PTR monitor.reset_monitor();
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@ -1581,10 +1581,11 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MWAIT(bxInstruction_c *i)
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// the execution. Any far control transfer between MONITOR and MWAIT
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// resets the monitoring logic.
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// artificial trap bit, why use another variable.
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BX_CPU_THIS_PTR debug_trap |= BX_DEBUG_TRAP_MWAIT; // artificial trap
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if (ECX & 1)
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BX_CPU_THIS_PTR debug_trap |= BX_DEBUG_TRAP_MWAIT_IF;
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BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_MWAIT_IF;
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else
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BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_MWAIT;
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BX_CPU_THIS_PTR async_event = 1; // so processor knows to check
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// Execution of this instruction completes. The processor
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// will remain in a optimized state until one of the above
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