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Merge patch [1153327] ignore segment bases in x86-64 by Avi Kivity

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This commit is contained in:
Stanislav Shwartsman 2005-02-28 18:56:05 +00:00
parent aeec5a6c5a
commit b25088bf2f
11 changed files with 97 additions and 80 deletions
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20
bochs/CHANGES
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@ -34,11 +34,15 @@ Changes to next release:
- several protected mode fixes by Kevin Lawton
- CPU (x86-64) (Stanislav)
- fetchdecode fixes for x86-64 and 3DNow!
- fixed CF flag handling for SHL instruction in x86-64 mode
- implemented CR8 register (aliased to APIC.TPR[7:4]) in x86-64 mode
- implemented NXE bit (No-Execute page protection) support for x86-64
- several x86-64 fixes by Avi Kivity
- fetchdecode fixes for x86-64 and 3DNow! (Stanislav)
- fixed CF flag handling for SHL instruction in x86-64 mode (Stanislav)
- implemented CR8 register (aliased to APIC.TPR[7:4]) (Stanislav)
- implemented NXE bit (No-Execute page protection) support (Stanislav)
- STOSQ instruction emulation fixed (Avi Kivity)
- allow null SS selector for MOV SS, POP SS, and LSS instructions
in long mode (Avi Kivity)
- ignore segment bases for all segments (except FS and GS) in long
mode (Avi Kivity)
- FPU
- totally rewritten all FPU code based on softfloat library
@ -207,6 +211,7 @@ Changes to next release:
[1123895] x86-64 gdb/debugger fixes by Avi Kivity
[1145423] stosq simulation bugfix by Avi Kivity
[1151012] allow null ss on x86-64 by Avi Kivity
[1153327] ignore segment bases in x86-64 by Avi Kivity
- SF patches partially applied
[896733] Lazy flags, for more instructions, only 1 src op
@ -219,6 +224,11 @@ Changes to next release:
- patch.v8086-exception.lightcone (LightCone)
- these S.F. bugs were closed
#1099294 VESA for Win98 bogus
#1112836 PGE-Bit crashes Bochs
#947586 The specification difference in x86-64 emulation
#1150781 Dissambly Error
#1117145 Push reset Button, APIC0 Error occur
#1123043 fpu stack pointer changed *despite* fault occured (e.g. #pf)
#1122066 PANIC: iret: IP > descriptor limit when installing os/2 warp
#809574 rm -f segfaults

26
bochs/cpu/access.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: access.cc,v 1.51 2005-01-25 20:41:43 sshwarts Exp $
// $Id: access.cc,v 1.52 2005-02-28 18:56:02 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -289,7 +289,7 @@ BX_CPU_C::write_virtual_byte(unsigned s, bx_address offset, Bit8u *data)
|| (offset <= seg->cache.u.segment.limit_scaled)) {
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 1, BX_WRITE);
pl = (CPL==3);
@ -339,7 +339,7 @@ BX_CPU_C::write_virtual_word(unsigned s, bx_address offset, Bit16u *data)
|| (offset < seg->cache.u.segment.limit_scaled)) {
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 2, BX_WRITE);
pl = (CPL==3);
@ -391,7 +391,7 @@ BX_CPU_C::write_virtual_dword(unsigned s, bx_address offset, Bit32u *data)
|| (offset < (seg->cache.u.segment.limit_scaled-2))) {
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 4, BX_WRITE);
pl = (CPL==3);
@ -443,7 +443,7 @@ BX_CPU_C::write_virtual_qword(unsigned s, bx_address offset, Bit64u *data)
|| (offset <= (seg->cache.u.segment.limit_scaled-7))) {
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 8, BX_WRITE);
pl = (CPL==3);
@ -495,7 +495,7 @@ BX_CPU_C::read_virtual_byte(unsigned s, bx_address offset, Bit8u *data)
|| (offset <= seg->cache.u.segment.limit_scaled)) {
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 1, BX_READ);
pl = (CPL==3);
@ -540,7 +540,7 @@ BX_CPU_C::read_virtual_word(unsigned s, bx_address offset, Bit16u *data)
|| (offset < seg->cache.u.segment.limit_scaled)) {
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 2, BX_READ);
pl = (CPL==3);
@ -586,7 +586,7 @@ BX_CPU_C::read_virtual_dword(unsigned s, bx_address offset, Bit32u *data)
|| (offset < (seg->cache.u.segment.limit_scaled-2))) {
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 4, BX_READ);
pl = (CPL==3);
@ -632,7 +632,7 @@ BX_CPU_C::read_virtual_qword(unsigned s, bx_address offset, Bit64u *data)
|| (offset <= (seg->cache.u.segment.limit_scaled-7))) {
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 8, BX_READ);
pl = (CPL==3);
@ -683,7 +683,7 @@ BX_CPU_C::read_RMW_virtual_byte(unsigned s, bx_address offset, Bit8u *data)
|| (offset <= seg->cache.u.segment.limit_scaled)) {
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 1, BX_RW);
pl = (CPL==3);
@ -736,7 +736,7 @@ BX_CPU_C::read_RMW_virtual_word(unsigned s, bx_address offset, Bit16u *data)
|| (offset < seg->cache.u.segment.limit_scaled)) {
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 2, BX_RW);
pl = (CPL==3);
@ -789,7 +789,7 @@ BX_CPU_C::read_RMW_virtual_dword(unsigned s, bx_address offset, Bit32u *data)
|| (offset < (seg->cache.u.segment.limit_scaled-2))) {
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 4, BX_RW);
pl = (CPL==3);
@ -842,7 +842,7 @@ BX_CPU_C::read_RMW_virtual_qword(unsigned s, bx_address offset, Bit64u *data)
|| (offset <= (seg->cache.u.segment.limit_scaled-7))) {
unsigned pl;
accessOK:
laddr = seg->cache.u.segment.base + offset;
laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset;
BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 8, BX_RW);
pl = (CPL==3);

10
bochs/cpu/cpu.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.98 2005-02-12 14:00:13 sshwarts Exp $
// $Id: cpu.cc,v 1.99 2005-02-28 18:56:03 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -166,7 +166,7 @@ printf("CPU_LOOP %d\n", bx_guard.special_unwind_stack);
if ( dbg_is_begin_instr_bpoint(
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
debug_eip,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base + debug_eip,
BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + debug_eip,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b) ) {
return;
}
@ -441,7 +441,7 @@ debugger_check:
if ( dbg_is_end_instr_bpoint(
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
debug_eip,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base + debug_eip,
BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + debug_eip,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b) ) {
return;
}
@ -636,7 +636,7 @@ unsigned BX_CPU_C::handleAsyncEvent(void)
// only bother comparing if any breakpoints enabled
if ( BX_CPU_THIS_PTR dr7 & 0x000000ff ) {
Bit32u iaddr =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base +
BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) +
BX_CPU_THIS_PTR prev_eip;
Bit32u dr6_bits;
if ( (dr6_bits = hwdebug_compare(iaddr, 1, BX_HWDebugInstruction,
@ -698,7 +698,7 @@ void BX_CPU_C::prefetch(void)
temp_rip = RIP;
temp_limit = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled;
laddr = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base + temp_rip;
laddr = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + temp_rip;
if (((Bit32u)temp_rip) > temp_limit) {
BX_PANIC(("prefetch: RIP > CS.limit"));

11
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.199 2005-02-27 17:41:26 sshwarts Exp $
// $Id: cpu.h,v 1.200 2005-02-28 18:56:03 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -2689,7 +2689,6 @@ public: // for now...
#endif
BX_SMF Bit16u read_flags(void);
BX_SMF Bit32u read_eflags(void);
BX_SMF Bit32u get_segment_base(unsigned seg);
BX_SMF Bit8u inp8(Bit16u addr) BX_CPP_AttrRegparmN(1);
BX_SMF void outp8(Bit16u addr, Bit8u value) BX_CPP_AttrRegparmN(2);
@ -2799,6 +2798,8 @@ public: // for now...
BX_CPP_INLINE Bit8u get_CPL(void);
BX_CPP_INLINE Bit32u get_EIP(void);
BX_SMF BX_CPP_INLINE bx_address get_segment_base(unsigned seg);
BX_SMF BX_CPP_INLINE bx_bool real_mode(void);
BX_SMF BX_CPP_INLINE bx_bool protected_mode(void);
BX_SMF BX_CPP_INLINE bx_bool v8086_mode(void);
@ -2873,8 +2874,12 @@ BX_CPP_INLINE Bit32u BX_CPU_C::get_EIP(void)
return (BX_CPU_THIS_PTR dword.eip);
}
BX_SMF BX_CPP_INLINE Bit32u BX_CPU_C_PREFIX get_segment_base(unsigned seg)
BX_CPP_INLINE bx_address BX_CPU_C::get_segment_base(unsigned seg)
{
#if BX_SUPPORT_X86_64
if (IsLongMode() && seg != BX_SEG_REG_FS && seg != BX_SEG_REG_GS)
return 0;
#endif
return (BX_CPU_THIS_PTR sregs[seg].cache.u.segment.base);
}

6
bochs/cpu/ctrl_xfer64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ctrl_xfer64.cc,v 1.27 2004-11-04 22:41:23 sshwarts Exp $
// $Id: ctrl_xfer64.cc,v 1.28 2005-02-28 18:56:04 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -56,7 +56,7 @@ BX_CPU_C::RETnear64_Iw(bxInstruction_c *i)
// /* ??? #SS(0) -or #GP(0) */
// }
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_RSP,
8, CPL==3, BX_READ, &return_RIP);
/* Pentium book says imm16 is number of words ??? */
@ -90,7 +90,7 @@ BX_CPU_C::RETnear64(bxInstruction_c *i)
// /* ??? #SS(0) -or #GP(0) */
// }
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_RSP,
8, CPL==3, BX_READ, &return_RIP);
RIP = return_RIP;

66
bochs/cpu/ctrl_xfer_pro.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ctrl_xfer_pro.cc,v 1.31 2005-02-27 17:41:27 sshwarts Exp $
// $Id: ctrl_xfer_pro.cc,v 1.32 2005-02-28 18:56:04 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -863,7 +863,7 @@ BX_CPU_C::call_protected(bxInstruction_c *i, Bit16u cs_raw, bx_address dispBig)
return_ESP = ESP;
else
return_ESP = SP;
return_ss_base = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base;
return_ss_base = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS);
// save return CS:eIP to be pushed on new stack
return_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
@ -920,14 +920,14 @@ BX_CPU_C::call_protected(bxInstruction_c *i, Bit16u cs_raw, bx_address dispBig)
if (gate_descriptor.type==4) {
for (i=param_count; i>0; i--) {
push_16(parameter_word[i-1]);
//access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + i*2,
//access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + i*2,
// 2, 0, BX_WRITE, &parameter_word[i]);
}
}
else {
for (i=param_count; i>0; i--) {
push_32(parameter_dword[i-1]);
//access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + i*4,
//access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + i*4,
// 4, 0, BX_WRITE, &parameter_dword[i]);
}
}
@ -1068,7 +1068,7 @@ BX_CPU_C::return_protected(bxInstruction_c *i, Bit16u pop_bytes)
else temp_ESP = SP;
// return selector RPL must be >= CPL, else #GP(return selector)
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP +
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP +
stack_cs_offset, 2, CPL==3, BX_READ, &raw_cs_selector);
parse_selector(raw_cs_selector, &cs_selector);
if ( cs_selector.rpl < CPL ) {
@ -1140,13 +1140,13 @@ BX_CPU_C::return_protected(bxInstruction_c *i, Bit16u pop_bytes)
#if BX_CPU_LEVEL >= 3
if (i->os32L()) {
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 0,
4, CPL==3, BX_READ, &return_EIP);
}
else
#endif
{
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 0,
2, CPL==3, BX_READ, &return_IP);
return_EIP = return_IP;
}
@ -1255,22 +1255,22 @@ BX_CPU_C::return_protected(bxInstruction_c *i, Bit16u pop_bytes)
/* examine return SS selector and associated descriptor: */
if (i->os32L()) {
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 12 + pop_bytes,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 12 + pop_bytes,
2, 0, BX_READ, &raw_ss_selector);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 8 + pop_bytes,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 8 + pop_bytes,
4, 0, BX_READ, &return_ESP);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 0,
4, 0, BX_READ, &return_EIP);
}
else {
Bit16u return_SP;
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 6 + pop_bytes,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 6 + pop_bytes,
2, 0, BX_READ, &raw_ss_selector);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 4 + pop_bytes,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 4 + pop_bytes,
2, 0, BX_READ, &return_SP);
return_ESP = return_SP;
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 0,
2, 0, BX_READ, &return_IP);
return_EIP = return_IP;
}
@ -1362,7 +1362,7 @@ BX_CPU_C::iret32_real(bxInstruction_c *i)
exception(BX_SS_EXCEPTION, 0, 0);
return 0;
}
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + ESP,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + ESP,
4, CPL == 3, BX_READ, &eip);
if (eip > 0xffff)
{
@ -1495,12 +1495,12 @@ BX_CPU_C::iret_protected(bxInstruction_c *i)
temp_RSP = RSP;
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + cs_offset,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_RSP + cs_offset,
2, CPL==3, BX_READ, &raw_cs_selector);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 0,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_RSP + 0,
8, CPL==3, BX_READ, &new_rip);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 16,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_RSP + 16,
8, CPL==3, BX_READ, &new_eflags);
// if VM=1 in flags image on stack then STACK_RETURN_TO_V86
@ -1605,7 +1605,7 @@ BX_CPU_C::iret_protected(bxInstruction_c *i)
}
/* examine return SS selector and associated descriptor */
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + ss_offset,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_RSP + ss_offset,
2, 0, BX_READ, &raw_ss_selector);
// long mode - allowed to be null
@ -1661,11 +1661,11 @@ BX_CPU_C::iret_protected(bxInstruction_c *i)
}
}
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 0,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_RSP + 0,
8, 0, BX_READ, &new_rip);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 16,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_RSP + 16,
4, 0, BX_READ, &new_eflags);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 24,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_RSP + 24,
8, 0, BX_READ, &new_rsp);
/* RIP must be in code segment limit, else #GP(0) */
@ -1750,13 +1750,13 @@ BX_CPU_C::iret_protected(bxInstruction_c *i)
else
temp_ESP = SP;
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + cs_offset,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + cs_offset,
2, CPL==3, BX_READ, &raw_cs_selector);
if (i->os32L()) {
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 0,
4, CPL==3, BX_READ, &new_eip);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 8,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 8,
4, CPL==3, BX_READ, &new_eflags);
// if VM=1 in flags image on stack then STACK_RETURN_TO_V86
@ -1768,9 +1768,9 @@ BX_CPU_C::iret_protected(bxInstruction_c *i)
}
}
else {
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 0,
2, CPL==3, BX_READ, &new_ip);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 4,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 4,
2, CPL==3, BX_READ, &new_flags);
}
@ -1893,7 +1893,7 @@ BX_CPU_C::iret_protected(bxInstruction_c *i)
}
/* examine return SS selector and associated descriptor */
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + ss_offset,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + ss_offset,
2, 0, BX_READ, &raw_ss_selector);
/* selector must be non-null, else #GP(0) */
@ -1946,19 +1946,19 @@ BX_CPU_C::iret_protected(bxInstruction_c *i)
}
if (i->os32L()) {
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 0,
4, 0, BX_READ, &new_eip);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 8,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 8,
4, 0, BX_READ, &new_eflags);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 12,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 12,
4, 0, BX_READ, &new_esp);
}
else {
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 0,
2, 0, BX_READ, &new_ip);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 4,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 4,
2, 0, BX_READ, &new_flags);
access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 6,
access_linear(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_SS) + temp_ESP + 6,
2, 0, BX_READ, &new_sp);
new_eip = new_ip;
new_esp = new_sp;

6
bochs/cpu/debugstuff.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: debugstuff.cc,v 1.32 2004-09-30 16:50:03 sshwarts Exp $
// $Id: debugstuff.cc,v 1.33 2005-02-28 18:56:04 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -155,13 +155,13 @@ BX_CPU_C::debug(Bit32u offset)
static disassembler bx_disassemble;
if (BX_CPU_THIS_PTR protectedMode) { // 16bit & 32bit protected mode
Base=BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base;
Base=BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS);
}
else {
Base=BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value<<4;
}
dbg_xlate_linear2phy(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base + offset,
dbg_xlate_linear2phy(BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + offset,
&phy_addr, &valid);
if (valid && BX_CPU_THIS_PTR mem!=NULL) {
BX_CPU_THIS_PTR mem->dbg_fetch_mem(phy_addr, 16, instr_buf);

4
bochs/cpu/extdb.cc
View File

@ -91,8 +91,8 @@ void bx_external_debugger(BX_CPU_C *cpu)
//regs.cr5 = cpu->cr5;
//regs.cr6 = cpu->cr6;
//regs.cr7 = cpu->cr7;
regs.fsbase = cpu->sregs[BX_SEG_REG_FS].cache.u.segment.base;
regs.gsbase = cpu->sregs[BX_SEG_REG_GS].cache.u.segment.base;
regs.fsbase = get_segment_base(BX_SEG_REG_FS);
regs.gsbase = get_segment_base(BX_SEG_REG_GS);
#if BX_SUPPORT_X86_64
regs.efer = (BX_CPU_THIS_PTR msr.sce << 0)
| (BX_CPU_THIS_PTR msr.lme << 8)

6
bochs/cpu/io.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: io.cc,v 1.24 2004-11-26 19:53:03 sshwarts Exp $
// $Id: io.cc,v 1.25 2005-02-28 18:56:04 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -180,7 +180,7 @@ BX_CPU_C::INSW_YvDX(bxInstruction_c *i)
// transfer, we can do the full segment limit check ourselves
// without generating an exception.
write_virtual_checks(dstSegPtr, edi, 2);
laddrDst = dstSegPtr->cache.u.segment.base + edi;
laddrDst = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_ES) + edi;
if (BX_CPU_THIS_PTR cr0.pg)
paddrDst = dtranslate_linear(laddrDst, CPL==3, BX_WRITE);
else
@ -486,7 +486,7 @@ BX_CPU_C::OUTSW_DXXv(bxInstruction_c *i)
// transfer, we can do the full segment limit check ourselves
// without generating an exception.
read_virtual_checks(srcSegPtr, esi, 2);
laddrSrc = srcSegPtr->cache.u.segment.base + esi;
laddrSrc = BX_CPU_THIS_PTR get_segment_base(seg) + esi;
if (BX_CPU_THIS_PTR cr0.pg)
paddrSrc = dtranslate_linear(laddrSrc, CPL==3, BX_READ);
else

6
bochs/cpu/paging.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: paging.cc,v 1.56 2005-02-23 21:18:23 sshwarts Exp $
// $Id: paging.cc,v 1.57 2005-02-28 18:56:04 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -578,7 +578,7 @@ void BX_CPU_C::INVLPG(bxInstruction_c* i)
}
#if BX_USE_TLB
laddr = BX_CPU_THIS_PTR sregs[i->seg()].cache.u.segment.base + RMAddr(i);
laddr = BX_CPU_THIS_PTR get_segment_base(i->seg()) + RMAddr(i);
Bit32u TLB_index = BX_TLB_INDEX_OF(laddr);
BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = BX_INVALID_TLB_ENTRY;
InstrTLB_Increment(tlbEntryInvlpg);
@ -994,8 +994,10 @@ BX_CPU_C::translate_linear(bx_address laddr, unsigned pl, unsigned rw, unsigned
#define ERROR_RESERVED 0x08
#define ERROR_CODE_ACCESS 0x10
#if BX_SUPPORT_X86_64 // keep compiler happy
page_fault_reserved:
error_code |= ERROR_RESERVED; // RSVD = 1
#endif
page_fault_access:
error_code |= ERROR_PROTECTION; // P = 1

16
bochs/cpu/string.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: string.cc,v 1.27 2005-02-22 18:24:19 sshwarts Exp $
// $Id: string.cc,v 1.28 2005-02-28 18:56:05 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -149,7 +149,7 @@ void BX_CPU_C::MOVSB_XbYb(bxInstruction_c *i)
// transfer, we can do the full segment limit check ourselves
// without generating an exception.
read_virtual_checks(srcSegPtr, si, 1);
laddrSrc = srcSegPtr->cache.u.segment.base + si;
laddrSrc = BX_CPU_THIS_PTR get_segment_base(seg) + si;
if (BX_CPU_THIS_PTR cr0.pg) {
paddrSrc = dtranslate_linear(laddrSrc, CPL==3, BX_READ);
}
@ -161,7 +161,7 @@ void BX_CPU_C::MOVSB_XbYb(bxInstruction_c *i)
paddrSrc = A20ADDR(paddrSrc);
write_virtual_checks(dstSegPtr, di, 1);
laddrDst = dstSegPtr->cache.u.segment.base + di;
laddrDst = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_ES) + di;
if (BX_CPU_THIS_PTR cr0.pg) {
paddrDst = dtranslate_linear(laddrDst, CPL==3, BX_WRITE);
}
@ -405,7 +405,7 @@ void BX_CPU_C::MOVSW_XwYw(bxInstruction_c *i)
// transfer, we can do the full segment limit check ourselves
// without generating an exception.
read_virtual_checks(srcSegPtr, si, 2);
laddrSrc = srcSegPtr->cache.u.segment.base + si;
laddrSrc = BX_CPU_THIS_PTR get_segment_base(seg) + si;
if (BX_CPU_THIS_PTR cr0.pg) {
paddrSrc = dtranslate_linear(laddrSrc, CPL==3, BX_READ);
}
@ -417,7 +417,7 @@ void BX_CPU_C::MOVSW_XwYw(bxInstruction_c *i)
paddrSrc = A20ADDR(paddrSrc);
write_virtual_checks(dstSegPtr, di, 2);
laddrDst = dstSegPtr->cache.u.segment.base + di;
laddrDst = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_ES) + di;
if (BX_CPU_THIS_PTR cr0.pg) {
paddrDst = dtranslate_linear(laddrDst, CPL==3, BX_WRITE);
}
@ -630,7 +630,7 @@ void BX_CPU_C::MOVSD_XdYd(bxInstruction_c *i)
// transfer, we can do the full segment limit check ourselves
// without generating an exception.
read_virtual_checks(srcSegPtr, esi, 4);
laddrSrc = srcSegPtr->cache.u.segment.base + esi;
laddrSrc = BX_CPU_THIS_PTR get_segment_base(seg) + esi;
if (BX_CPU_THIS_PTR cr0.pg) {
paddrSrc = dtranslate_linear(laddrSrc, CPL==3, BX_READ);
}
@ -642,7 +642,7 @@ void BX_CPU_C::MOVSD_XdYd(bxInstruction_c *i)
paddrSrc = A20ADDR(paddrSrc);
write_virtual_checks(dstSegPtr, edi, 4);
laddrDst = dstSegPtr->cache.u.segment.base + edi;
laddrDst = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_ES) + edi;
if (BX_CPU_THIS_PTR cr0.pg) {
paddrDst = dtranslate_linear(laddrDst, CPL==3, BX_WRITE);
}
@ -1561,7 +1561,7 @@ void BX_CPU_C::STOSB_YbAL(bxInstruction_c *i)
// transfer, we can do the full segment limit check ourselves
// without generating an exception.
write_virtual_checks(dstSegPtr, edi, 1);
laddrDst = dstSegPtr->cache.u.segment.base + edi;
laddrDst = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_ES) + edi;
if (BX_CPU_THIS_PTR cr0.pg) {
paddrDst = dtranslate_linear(laddrDst, CPL==3, BX_WRITE);
}