Speed simulation between 3 to 5% by eliminating several checks from cpu loop.
The checks were related to repeat instructions - handle them differently
This commit is contained in:
Stanislav Shwartsman
parent
b7be2eb0b1
commit
5c21f7821f
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: bochs.h,v 1.204 2006-10-31 19:26:34 vruppert Exp $
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// $Id: bochs.h,v 1.205 2007-01-05 13:40:46 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -208,6 +208,12 @@ void print_tree(bx_param_c *node, int level = 0);
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# define A20ADDR(x) (x)
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#endif
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#if BX_SUPPORT_SMP
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# define BX_TICK1_IF_SINGLE_PROCESSOR()
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#else
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# define BX_TICK1_IF_SINGLE_PROCESSOR() BX_TICK1()
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#endif
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// you can't use static member functions on the CPU, if there are going
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// to be 2 cpus. Check this early on.
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#if BX_SUPPORT_SMP
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202
bochs/cpu/cpu.cc
202
bochs/cpu/cpu.cc
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.168 2006-09-26 19:16:10 sshwarts Exp $
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// $Id: cpu.cc,v 1.169 2007-01-05 13:40:46 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -112,12 +112,6 @@ static unsigned iCacheMisses=0;
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if (count == 0) return; \
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}
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#if BX_SUPPORT_SMP
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# define BX_TICK1_IF_SINGLE_PROCESSOR()
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#else
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# define BX_TICK1_IF_SINGLE_PROCESSOR() BX_TICK1()
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#endif
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// Make code more tidy with a few macros.
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#if BX_SUPPORT_X86_64==0
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#define RIP EIP
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@ -290,93 +284,9 @@ void BX_CPU_C::cpu_loop(Bit32u max_instr_count)
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// decoding instruction compeleted -> continue with execution
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BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID, i);
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RIP += i->ilen();
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if ( !(i->repUsedL() && i->repeatableL()) ) {
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// non repeating instruction
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BX_CPU_CALL_METHOD(execute, (i));
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}
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else {
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repeat_loop:
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if (i->repeatableZFL()) {
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#if BX_SUPPORT_X86_64
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if (i->as64L()) {
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if (RCX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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RCX --;
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}
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if ((i->repUsedValue()==3) && (get_ZF()==0)) goto debugger_check;
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if ((i->repUsedValue()==2) && (get_ZF()!=0)) goto debugger_check;
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if (RCX == 0) goto debugger_check;
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}
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else
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#endif
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if (i->as32L()) {
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if (ECX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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ECX --;
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}
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if ((i->repUsedValue()==3) && (get_ZF()==0)) goto debugger_check;
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if ((i->repUsedValue()==2) && (get_ZF()!=0)) goto debugger_check;
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if (ECX == 0) goto debugger_check;
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}
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else {
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if (CX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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CX --;
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}
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if ((i->repUsedValue()==3) && (get_ZF()==0)) goto debugger_check;
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if ((i->repUsedValue()==2) && (get_ZF()!=0)) goto debugger_check;
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if (CX == 0) goto debugger_check;
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}
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}
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else { // normal repeat, no concern for ZF
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#if BX_SUPPORT_X86_64
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if (i->as64L()) {
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if (RCX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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RCX --;
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}
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if (RCX == 0) goto debugger_check;
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}
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else
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#endif
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if (i->as32L()) {
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if (ECX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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ECX --;
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}
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if (ECX == 0) goto debugger_check;
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}
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else { // 16bit addrsize
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if (CX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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CX --;
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}
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if (CX == 0) goto debugger_check;
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}
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}
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BX_TICK1_IF_SINGLE_PROCESSOR();
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#if BX_DEBUGGER == 0
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// when debugger is not enabled, directly jump to next iteration
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if (! BX_CPU_THIS_PTR async_event) goto repeat_loop;
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#endif
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// invalidate_prefetch_q(); // why do we need invalidate_prefetch_q ?
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RIP = BX_CPU_THIS_PTR prev_eip; // repeat loop not done, restore RIP
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goto debugger_check;
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}
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debugger_check:
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BX_CPU_THIS_PTR prev_eip = RIP; // commit new EIP
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BX_CPU_THIS_PTR prev_esp = RSP; // commit new ESP
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BX_CPU_CALL_METHOD(execute, (i)); // might iterate repeat instruction
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BX_CPU_THIS_PTR prev_eip = RIP; // commit new RIP
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BX_CPU_THIS_PTR prev_esp = RSP; // commit new RSP
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BX_INSTR_AFTER_EXECUTION(BX_CPU_ID, i);
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BX_TICK1_IF_SINGLE_PROCESSOR();
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@ -406,6 +316,110 @@ debugger_check:
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} // while (1)
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}
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void BX_CPU_C::repeat(bxInstruction_c *i, BxExecutePtr_t execute)
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{
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// non repeated instruction
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if (! i->repUsedL()) {
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BX_CPU_CALL_METHOD(execute, (i));
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return;
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}
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while(1) {
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#if BX_SUPPORT_X86_64
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if (i->as64L()) {
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if (RCX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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RCX --;
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}
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if (RCX == 0) return;
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}
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else
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#endif
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if (i->as32L()) {
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if (ECX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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ECX --;
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}
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if (ECX == 0) return;
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}
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else { // 16bit addrsize
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if (CX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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CX --;
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}
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if (CX == 0) return;
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}
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BX_TICK1_IF_SINGLE_PROCESSOR();
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#if BX_DEBUGGER == 0
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if (BX_CPU_THIS_PTR async_event)
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#endif
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break; // exit always if debugger enabled
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}
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RIP = BX_CPU_THIS_PTR prev_eip; // repeat loop not done, restore RIP
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}
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void BX_CPU_C::repeat_ZFL(bxInstruction_c *i, BxExecutePtr_t execute)
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{
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// non repeated instruction
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if (! i->repUsedL()) {
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BX_CPU_CALL_METHOD(execute, (i));
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return;
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}
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while(1) {
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#if BX_SUPPORT_X86_64
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if (i->as64L()) {
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if (RCX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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RCX --;
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}
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if ((i->repUsedValue()==3) && (get_ZF()==0)) return;
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if ((i->repUsedValue()==2) && (get_ZF()!=0)) return;
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if (RCX == 0) return;
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}
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else
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#endif
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if (i->as32L()) {
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if (ECX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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ECX --;
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}
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if ((i->repUsedValue()==3) && (get_ZF()==0)) return;
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if ((i->repUsedValue()==2) && (get_ZF()!=0)) return;
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if (ECX == 0) return;
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}
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else {
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if (CX != 0) {
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BX_CPU_CALL_METHOD(execute, (i));
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BX_INSTR_REPEAT_ITERATION(BX_CPU_ID, i);
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CX --;
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}
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if ((i->repUsedValue()==3) && (get_ZF()==0)) return;
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if ((i->repUsedValue()==2) && (get_ZF()!=0)) return;
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if (CX == 0) return;
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}
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BX_TICK1_IF_SINGLE_PROCESSOR();
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#if BX_DEBUGGER == 0
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if (BX_CPU_THIS_PTR async_event)
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#endif
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break; // exit always if debugger enabled
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}
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RIP = BX_CPU_THIS_PTR prev_eip; // repeat loop not done, restore RIP
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}
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unsigned BX_CPU_C::handleAsyncEvent(void)
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{
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//
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.306 2006-10-29 08:48:30 vruppert Exp $
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// $Id: cpu.h,v 1.307 2007-01-05 13:40:46 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -649,8 +649,8 @@ public:
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// 26..23 ilen (0..15). Leave this one on top so no mask is needed.
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// 22..22 mod==c0 (modrm)
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// 21..13 b1 (9bits of opcode; 1byte-op=0..255, 2byte-op=256..511.
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// 12..12 BxRepeatableZF (pass-thru from fetchdecode attributes)
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// 11..11 BxRepeatable (pass-thru from fetchdecode attributes)
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// 12..12 (unused)
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// 11..11 (unused)
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// 10...9 repUsed (0=none, 2=0xF2, 3=0xF3).
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// 8...8 extend8bit
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// 7...7 as64
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@ -846,20 +846,6 @@ public:
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BX_CPP_INLINE void setRepUsed(unsigned value) {
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metaInfo = (metaInfo & ~(3<<9)) | (value<<9);
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}
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BX_CPP_INLINE void setRepAttr(unsigned value) {
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// value is expected to be masked, and only contain bits
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// for BxRepeatable and BxRepeatableZF. We don't need to
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// keep masking out these bits before we add in new ones,
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// since the fetch process won't start with repeatable attributes
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// and then delete them.
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metaInfo |= value;
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}
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BX_CPP_INLINE unsigned repeatableL(void) {
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return metaInfo & (1<<11);
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}
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BX_CPP_INLINE unsigned repeatableZFL(void) {
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return metaInfo & (1<<12);
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}
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BX_CPP_INLINE unsigned b1(void) {
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return (metaInfo >> 13) & 0x1ff;
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@ -1408,6 +1394,7 @@ public: // for now...
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BX_SMF void ARPL_EwGw(bxInstruction_c *);
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BX_SMF void PUSH_Id(bxInstruction_c *);
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BX_SMF void PUSH_Iw(bxInstruction_c *);
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BX_SMF void INSB_YbDX(bxInstruction_c *);
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BX_SMF void INSW_YwDX(bxInstruction_c *);
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BX_SMF void INSD_YdDX(bxInstruction_c *);
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@ -1415,6 +1402,13 @@ public: // for now...
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BX_SMF void OUTSW_DXXw(bxInstruction_c *);
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BX_SMF void OUTSD_DXXd(bxInstruction_c *);
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BX_SMF void REP_INSB_YbDX(bxInstruction_c *);
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BX_SMF void REP_INSW_YwDX(bxInstruction_c *);
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BX_SMF void REP_INSD_YdDX(bxInstruction_c *);
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BX_SMF void REP_OUTSB_DXXb(bxInstruction_c *);
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BX_SMF void REP_OUTSW_DXXw(bxInstruction_c *);
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BX_SMF void REP_OUTSD_DXXd(bxInstruction_c *);
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BX_SMF void BOUND_GwMa(bxInstruction_c *);
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BX_SMF void BOUND_GdMa(bxInstruction_c *);
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@ -1481,6 +1475,22 @@ public: // for now...
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BX_SMF void LODSD_EAXXd(bxInstruction_c *);
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BX_SMF void SCASD_EAXXd(bxInstruction_c *);
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BX_SMF void REP_MOVSB_XbYb(bxInstruction_c *);
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BX_SMF void REP_MOVSW_XwYw(bxInstruction_c *);
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BX_SMF void REP_MOVSD_XdYd(bxInstruction_c *);
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BX_SMF void REP_CMPSB_XbYb(bxInstruction_c *);
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BX_SMF void REP_CMPSW_XwYw(bxInstruction_c *);
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BX_SMF void REP_CMPSD_XdYd(bxInstruction_c *);
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BX_SMF void REP_STOSB_YbAL(bxInstruction_c *);
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BX_SMF void REP_LODSB_ALXb(bxInstruction_c *);
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BX_SMF void REP_SCASB_ALXb(bxInstruction_c *);
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BX_SMF void REP_STOSW_YwAX(bxInstruction_c *);
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BX_SMF void REP_LODSW_AXXw(bxInstruction_c *);
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BX_SMF void REP_SCASW_AXXw(bxInstruction_c *);
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BX_SMF void REP_STOSD_YdEAX(bxInstruction_c *);
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BX_SMF void REP_LODSD_EAXXd(bxInstruction_c *);
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BX_SMF void REP_SCASD_EAXXd(bxInstruction_c *);
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BX_SMF void RETnear32(bxInstruction_c *);
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BX_SMF void RETnear16(bxInstruction_c *);
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BX_SMF void MOV_EbIb(bxInstruction_c *);
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@ -2371,11 +2381,16 @@ public: // for now...
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BX_SMF void MOVSQ_XqYq(bxInstruction_c *);
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BX_SMF void CMPSQ_XqYq(bxInstruction_c *);
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BX_SMF void STOSQ_YqRAX(bxInstruction_c *);
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BX_SMF void LODSQ_RAXXq(bxInstruction_c *);
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BX_SMF void SCASQ_RAXXq(bxInstruction_c *);
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BX_SMF void REP_MOVSQ_XqYq(bxInstruction_c *);
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BX_SMF void REP_CMPSQ_XqYq(bxInstruction_c *);
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BX_SMF void REP_STOSQ_YqRAX(bxInstruction_c *);
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BX_SMF void REP_LODSQ_RAXXq(bxInstruction_c *);
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BX_SMF void REP_SCASQ_RAXXq(bxInstruction_c *);
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BX_SMF void RETnear64(bxInstruction_c *);
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BX_SMF void ENTER64_IwIb(bxInstruction_c *);
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BX_SMF void LEAVE64(bxInstruction_c *);
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@ -2735,6 +2750,9 @@ public: // for now...
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Bit16u port, Bit32u wordCount);
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#endif
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BX_SMF void repeat(bxInstruction_c *i, BxExecutePtr_t execute);
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BX_SMF void repeat_ZFL(bxInstruction_c *i, BxExecutePtr_t execute);
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BX_SMF void access_linear(bx_address address, unsigned length, unsigned pl,
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unsigned rw, void *data) BX_CPP_AttrRegparmN(3);
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BX_SMF bx_phy_address translate_linear(bx_address laddr,
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@ -3324,9 +3342,6 @@ IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
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#define BxLockable 0x0200 // bit 9
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#define Bx3ByteOpcode 0x0400 // bit 10
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#define BxRepeatable 0x0800 // bit 11 (pass through to metaInfo field)
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#define BxRepeatableZF 0x1000 // bit 12 (pass through to metaInfo field)
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#define BxGroup1 BxGroupN
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#define BxGroup2 BxGroupN
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#define BxGroup3 BxGroupN
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.98 2006-06-09 22:29:07 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.99 2007-01-05 13:40:46 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -508,10 +508,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 69 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::IMUL_GwEwIw },
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/* 6A */ { BxImmediate_Ib_SE, &BX_CPU_C::PUSH_Iw },
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/* 6B */ { BxAnother | BxImmediate_Ib_SE, &BX_CPU_C::IMUL_GwEwIw },
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/* 6C */ { BxRepeatable, &BX_CPU_C::INSB_YbDX },
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/* 6D */ { BxRepeatable, &BX_CPU_C::INSW_YwDX },
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/* 6E */ { BxRepeatable, &BX_CPU_C::OUTSB_DXXb },
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/* 6F */ { BxRepeatable, &BX_CPU_C::OUTSW_DXXw },
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/* 6C */ { 0, &BX_CPU_C::REP_INSB_YbDX },
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/* 6D */ { 0, &BX_CPU_C::REP_INSW_YwDX },
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/* 6E */ { 0, &BX_CPU_C::REP_OUTSB_DXXb },
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/* 6F */ { 0, &BX_CPU_C::REP_OUTSW_DXXw },
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/* 70 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jw },
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/* 71 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jw },
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/* 72 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jw },
|
||||
@ -564,18 +564,18 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
|
||||
/* A1 */ { BxImmediate_O, &BX_CPU_C::MOV_AXOw },
|
||||
/* A2 */ { BxImmediate_O, &BX_CPU_C::MOV_ObAL },
|
||||
/* A3 */ { BxImmediate_O, &BX_CPU_C::MOV_OwAX },
|
||||
/* A4 */ { BxRepeatable, &BX_CPU_C::MOVSB_XbYb },
|
||||
/* A5 */ { BxRepeatable, &BX_CPU_C::MOVSW_XwYw },
|
||||
/* A6 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSB_XbYb },
|
||||
/* A7 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSW_XwYw },
|
||||
/* A4 */ { 0, &BX_CPU_C::REP_MOVSB_XbYb },
|
||||
/* A5 */ { 0, &BX_CPU_C::REP_MOVSW_XwYw },
|
||||
/* A6 */ { 0, &BX_CPU_C::REP_CMPSB_XbYb },
|
||||
/* A7 */ { 0, &BX_CPU_C::REP_CMPSW_XwYw },
|
||||
/* A8 */ { BxImmediate_Ib, &BX_CPU_C::TEST_ALIb },
|
||||
/* A9 */ { BxImmediate_Iv, &BX_CPU_C::TEST_AXIw },
|
||||
/* AA */ { BxRepeatable, &BX_CPU_C::STOSB_YbAL },
|
||||
/* AB */ { BxRepeatable, &BX_CPU_C::STOSW_YwAX },
|
||||
/* AC */ { BxRepeatable, &BX_CPU_C::LODSB_ALXb },
|
||||
/* AD */ { BxRepeatable, &BX_CPU_C::LODSW_AXXw },
|
||||
/* AE */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASB_ALXb },
|
||||
/* AF */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASW_AXXw },
|
||||
/* AA */ { 0, &BX_CPU_C::REP_STOSB_YbAL },
|
||||
/* AB */ { 0, &BX_CPU_C::REP_STOSW_YwAX },
|
||||
/* AC */ { 0, &BX_CPU_C::REP_LODSB_ALXb },
|
||||
/* AD */ { 0, &BX_CPU_C::REP_LODSW_AXXw },
|
||||
/* AE */ { 0, &BX_CPU_C::REP_SCASB_ALXb },
|
||||
/* AF */ { 0, &BX_CPU_C::REP_SCASW_AXXw },
|
||||
/* B0 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
/* B1 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
/* B2 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
@ -1066,10 +1066,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
|
||||
/* 69 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::IMUL_GdEdId },
|
||||
/* 6A */ { BxImmediate_Ib_SE, &BX_CPU_C::PUSH_Id },
|
||||
/* 6B */ { BxAnother | BxImmediate_Ib_SE, &BX_CPU_C::IMUL_GdEdId },
|
||||
/* 6C */ { BxRepeatable, &BX_CPU_C::INSB_YbDX },
|
||||
/* 6D */ { BxRepeatable, &BX_CPU_C::INSD_YdDX },
|
||||
/* 6E */ { BxRepeatable, &BX_CPU_C::OUTSB_DXXb },
|
||||
/* 6F */ { BxRepeatable, &BX_CPU_C::OUTSD_DXXd },
|
||||
/* 6C */ { 0, &BX_CPU_C::REP_INSB_YbDX },
|
||||
/* 6D */ { 0, &BX_CPU_C::REP_INSD_YdDX },
|
||||
/* 6E */ { 0, &BX_CPU_C::REP_OUTSB_DXXb },
|
||||
/* 6F */ { 0, &BX_CPU_C::REP_OUTSD_DXXd },
|
||||
/* 70 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jd },
|
||||
/* 71 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jd },
|
||||
/* 72 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jd },
|
||||
@ -1122,18 +1122,18 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
|
||||
/* A1 */ { BxImmediate_O, &BX_CPU_C::MOV_EAXOd },
|
||||
/* A2 */ { BxImmediate_O, &BX_CPU_C::MOV_ObAL },
|
||||
/* A3 */ { BxImmediate_O, &BX_CPU_C::MOV_OdEAX },
|
||||
/* A4 */ { BxRepeatable, &BX_CPU_C::MOVSB_XbYb },
|
||||
/* A5 */ { BxRepeatable, &BX_CPU_C::MOVSD_XdYd },
|
||||
/* A6 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSB_XbYb },
|
||||
/* A7 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSD_XdYd },
|
||||
/* A4 */ { 0, &BX_CPU_C::REP_MOVSB_XbYb },
|
||||
/* A5 */ { 0, &BX_CPU_C::REP_MOVSD_XdYd },
|
||||
/* A6 */ { 0, &BX_CPU_C::REP_CMPSB_XbYb },
|
||||
/* A7 */ { 0, &BX_CPU_C::REP_CMPSD_XdYd },
|
||||
/* A8 */ { BxImmediate_Ib, &BX_CPU_C::TEST_ALIb },
|
||||
/* A9 */ { BxImmediate_Iv, &BX_CPU_C::TEST_EAXId },
|
||||
/* AA */ { BxRepeatable, &BX_CPU_C::STOSB_YbAL },
|
||||
/* AB */ { BxRepeatable, &BX_CPU_C::STOSD_YdEAX },
|
||||
/* AC */ { BxRepeatable, &BX_CPU_C::LODSB_ALXb },
|
||||
/* AD */ { BxRepeatable, &BX_CPU_C::LODSD_EAXXd },
|
||||
/* AE */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASB_ALXb },
|
||||
/* AF */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASD_EAXXd },
|
||||
/* AA */ { 0, &BX_CPU_C::REP_STOSB_YbAL },
|
||||
/* AB */ { 0, &BX_CPU_C::REP_STOSD_YdEAX },
|
||||
/* AC */ { 0, &BX_CPU_C::REP_LODSB_ALXb },
|
||||
/* AD */ { 0, &BX_CPU_C::REP_LODSD_EAXXd },
|
||||
/* AE */ { 0, &BX_CPU_C::REP_SCASB_ALXb },
|
||||
/* AF */ { 0, &BX_CPU_C::REP_SCASD_EAXXd },
|
||||
/* B0 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
/* B1 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
/* B2 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
@ -1641,7 +1641,6 @@ fetch_b1:
|
||||
}
|
||||
|
||||
attr = BxOpcodeInfo[b1+offset].Attr;
|
||||
instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
|
||||
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
// handle 3-byte escape
|
||||
@ -1863,7 +1862,6 @@ modrm_done:
|
||||
}
|
||||
|
||||
instruction->execute = OpcodeInfoPtr->ExecutePtr;
|
||||
instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
|
||||
}
|
||||
else {
|
||||
// Opcode does not require a MODRM byte.
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: fetchdecode64.cc,v 1.100 2006-08-11 17:23:36 sshwarts Exp $
|
||||
// $Id: fetchdecode64.cc,v 1.101 2007-01-05 13:40:46 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -660,10 +660,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* 69 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::IMUL_GwEwIw },
|
||||
/* 6A */ { BxImmediate_Ib_SE, &BX_CPU_C::PUSH_Iw },
|
||||
/* 6B */ { BxAnother | BxImmediate_Ib_SE, &BX_CPU_C::IMUL_GwEwIw },
|
||||
/* 6C */ { BxRepeatable, &BX_CPU_C::INSB_YbDX },
|
||||
/* 6D */ { BxRepeatable, &BX_CPU_C::INSW_YwDX },
|
||||
/* 6E */ { BxRepeatable, &BX_CPU_C::OUTSB_DXXb },
|
||||
/* 6F */ { BxRepeatable, &BX_CPU_C::OUTSW_DXXw },
|
||||
/* 6C */ { 0, &BX_CPU_C::REP_INSB_YbDX },
|
||||
/* 6D */ { 0, &BX_CPU_C::REP_INSW_YwDX },
|
||||
/* 6E */ { 0, &BX_CPU_C::REP_OUTSB_DXXb },
|
||||
/* 6F */ { 0, &BX_CPU_C::REP_OUTSW_DXXw },
|
||||
/* 70 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
|
||||
/* 71 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
|
||||
/* 72 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
|
||||
@ -716,18 +716,18 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* A1 */ { BxImmediate_O, &BX_CPU_C::MOV_AXOq },
|
||||
/* A2 */ { BxImmediate_O, &BX_CPU_C::MOV_OqAL },
|
||||
/* A3 */ { BxImmediate_O, &BX_CPU_C::MOV_OqAX },
|
||||
/* A4 */ { BxRepeatable, &BX_CPU_C::MOVSB_XbYb },
|
||||
/* A5 */ { BxRepeatable, &BX_CPU_C::MOVSW_XwYw },
|
||||
/* A6 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSB_XbYb },
|
||||
/* A7 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSW_XwYw },
|
||||
/* A4 */ { 0, &BX_CPU_C::REP_MOVSB_XbYb },
|
||||
/* A5 */ { 0, &BX_CPU_C::REP_MOVSW_XwYw },
|
||||
/* A6 */ { 0, &BX_CPU_C::REP_CMPSB_XbYb },
|
||||
/* A7 */ { 0, &BX_CPU_C::REP_CMPSW_XwYw },
|
||||
/* A8 */ { BxImmediate_Ib, &BX_CPU_C::TEST_ALIb },
|
||||
/* A9 */ { BxImmediate_Iv, &BX_CPU_C::TEST_AXIw },
|
||||
/* AA */ { BxRepeatable, &BX_CPU_C::STOSB_YbAL },
|
||||
/* AB */ { BxRepeatable, &BX_CPU_C::STOSW_YwAX },
|
||||
/* AC */ { BxRepeatable, &BX_CPU_C::LODSB_ALXb },
|
||||
/* AD */ { BxRepeatable, &BX_CPU_C::LODSW_AXXw },
|
||||
/* AE */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASB_ALXb },
|
||||
/* AF */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASW_AXXw },
|
||||
/* AA */ { 0, &BX_CPU_C::REP_STOSB_YbAL },
|
||||
/* AB */ { 0, &BX_CPU_C::REP_STOSW_YwAX },
|
||||
/* AC */ { 0, &BX_CPU_C::REP_LODSB_ALXb },
|
||||
/* AD */ { 0, &BX_CPU_C::REP_LODSW_AXXw },
|
||||
/* AE */ { 0, &BX_CPU_C::REP_SCASB_ALXb },
|
||||
/* AF */ { 0, &BX_CPU_C::REP_SCASW_AXXw },
|
||||
/* B0 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
/* B1 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
/* B2 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
@ -1189,10 +1189,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* 69 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::IMUL_GdEdId },
|
||||
/* 6A */ { BxImmediate_Ib_SE, &BX_CPU_C::PUSH64_Id },
|
||||
/* 6B */ { BxAnother | BxImmediate_Ib_SE, &BX_CPU_C::IMUL_GdEdId },
|
||||
/* 6C */ { BxRepeatable, &BX_CPU_C::INSB_YbDX },
|
||||
/* 6D */ { BxRepeatable, &BX_CPU_C::INSD_YdDX },
|
||||
/* 6E */ { BxRepeatable, &BX_CPU_C::OUTSB_DXXb },
|
||||
/* 6F */ { BxRepeatable, &BX_CPU_C::OUTSD_DXXd },
|
||||
/* 6C */ { 0, &BX_CPU_C::REP_INSB_YbDX },
|
||||
/* 6D */ { 0, &BX_CPU_C::REP_INSD_YdDX },
|
||||
/* 6E */ { 0, &BX_CPU_C::REP_OUTSB_DXXb },
|
||||
/* 6F */ { 0, &BX_CPU_C::REP_OUTSD_DXXd },
|
||||
/* 70 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
|
||||
/* 71 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
|
||||
/* 72 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
|
||||
@ -1245,18 +1245,18 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* A1 */ { BxImmediate_O, &BX_CPU_C::MOV_EAXOq },
|
||||
/* A2 */ { BxImmediate_O, &BX_CPU_C::MOV_OqAL },
|
||||
/* A3 */ { BxImmediate_O, &BX_CPU_C::MOV_OqEAX },
|
||||
/* A4 */ { BxRepeatable, &BX_CPU_C::MOVSB_XbYb },
|
||||
/* A5 */ { BxRepeatable, &BX_CPU_C::MOVSD_XdYd },
|
||||
/* A6 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSB_XbYb },
|
||||
/* A7 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSD_XdYd },
|
||||
/* A4 */ { 0, &BX_CPU_C::REP_MOVSB_XbYb },
|
||||
/* A5 */ { 0, &BX_CPU_C::REP_MOVSD_XdYd },
|
||||
/* A6 */ { 0, &BX_CPU_C::REP_CMPSB_XbYb },
|
||||
/* A7 */ { 0, &BX_CPU_C::REP_CMPSD_XdYd },
|
||||
/* A8 */ { BxImmediate_Ib, &BX_CPU_C::TEST_ALIb },
|
||||
/* A9 */ { BxImmediate_Iv, &BX_CPU_C::TEST_EAXId },
|
||||
/* AA */ { BxRepeatable, &BX_CPU_C::STOSB_YbAL },
|
||||
/* AB */ { BxRepeatable, &BX_CPU_C::STOSD_YdEAX },
|
||||
/* AC */ { BxRepeatable, &BX_CPU_C::LODSB_ALXb },
|
||||
/* AD */ { BxRepeatable, &BX_CPU_C::LODSD_EAXXd },
|
||||
/* AE */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASB_ALXb },
|
||||
/* AF */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASD_EAXXd },
|
||||
/* AA */ { 0, &BX_CPU_C::REP_STOSB_YbAL },
|
||||
/* AB */ { 0, &BX_CPU_C::REP_STOSD_YdEAX },
|
||||
/* AC */ { 0, &BX_CPU_C::REP_LODSB_ALXb },
|
||||
/* AD */ { 0, &BX_CPU_C::REP_LODSD_EAXXd },
|
||||
/* AE */ { 0, &BX_CPU_C::REP_SCASB_ALXb },
|
||||
/* AF */ { 0, &BX_CPU_C::REP_SCASD_EAXXd },
|
||||
/* B0 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
/* B1 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
/* B2 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
@ -1718,10 +1718,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* 69 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::IMUL_GqEqId },
|
||||
/* 6A */ { BxImmediate_Ib_SE, &BX_CPU_C::PUSH64_Id },
|
||||
/* 6B */ { BxAnother | BxImmediate_Ib_SE, &BX_CPU_C::IMUL_GqEqId },
|
||||
/* 6C */ { BxRepeatable, &BX_CPU_C::INSB_YbDX },
|
||||
/* 6D */ { BxRepeatable, &BX_CPU_C::INSD_YdDX },
|
||||
/* 6E */ { BxRepeatable, &BX_CPU_C::OUTSB_DXXb },
|
||||
/* 6F */ { BxRepeatable, &BX_CPU_C::OUTSD_DXXd },
|
||||
/* 6C */ { 0, &BX_CPU_C::REP_INSB_YbDX },
|
||||
/* 6D */ { 0, &BX_CPU_C::REP_INSD_YdDX },
|
||||
/* 6E */ { 0, &BX_CPU_C::REP_OUTSB_DXXb },
|
||||
/* 6F */ { 0, &BX_CPU_C::REP_OUTSD_DXXd },
|
||||
/* 70 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
|
||||
/* 71 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
|
||||
/* 72 */ { BxImmediate_BrOff8, &BX_CPU_C::JCC_Jq },
|
||||
@ -1774,18 +1774,18 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* A1 */ { BxImmediate_O, &BX_CPU_C::MOV_RAXOq },
|
||||
/* A2 */ { BxImmediate_O, &BX_CPU_C::MOV_OqAL },
|
||||
/* A3 */ { BxImmediate_O, &BX_CPU_C::MOV_OqRAX },
|
||||
/* A4 */ { BxRepeatable, &BX_CPU_C::MOVSB_XbYb },
|
||||
/* A5 */ { BxRepeatable, &BX_CPU_C::MOVSQ_XqYq },
|
||||
/* A6 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSB_XbYb },
|
||||
/* A7 */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::CMPSQ_XqYq },
|
||||
/* A4 */ { 0, &BX_CPU_C::REP_MOVSB_XbYb },
|
||||
/* A5 */ { 0, &BX_CPU_C::REP_MOVSQ_XqYq },
|
||||
/* A6 */ { 0, &BX_CPU_C::REP_CMPSB_XbYb },
|
||||
/* A7 */ { 0, &BX_CPU_C::REP_CMPSQ_XqYq },
|
||||
/* A8 */ { BxImmediate_Ib, &BX_CPU_C::TEST_ALIb },
|
||||
/* A9 */ { BxImmediate_Iv, &BX_CPU_C::TEST_RAXId },
|
||||
/* AA */ { BxRepeatable, &BX_CPU_C::STOSB_YbAL },
|
||||
/* AB */ { BxRepeatable, &BX_CPU_C::STOSQ_YqRAX },
|
||||
/* AC */ { BxRepeatable, &BX_CPU_C::LODSB_ALXb },
|
||||
/* AD */ { BxRepeatable, &BX_CPU_C::LODSQ_RAXXq },
|
||||
/* AE */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASB_ALXb },
|
||||
/* AF */ { BxRepeatable | BxRepeatableZF, &BX_CPU_C::SCASQ_RAXXq },
|
||||
/* AA */ { 0, &BX_CPU_C::REP_STOSB_YbAL },
|
||||
/* AB */ { 0, &BX_CPU_C::REP_STOSQ_YqRAX },
|
||||
/* AC */ { 0, &BX_CPU_C::REP_LODSB_ALXb },
|
||||
/* AD */ { 0, &BX_CPU_C::REP_LODSQ_RAXXq },
|
||||
/* AE */ { 0, &BX_CPU_C::REP_SCASB_ALXb },
|
||||
/* AF */ { 0, &BX_CPU_C::REP_SCASQ_RAXXq },
|
||||
/* B0 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
/* B1 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
/* B2 */ { BxImmediate_Ib, &BX_CPU_C::MOV_RLIb },
|
||||
@ -2276,7 +2276,6 @@ fetch_b1:
|
||||
}
|
||||
|
||||
attr = BxOpcodeInfo64[b1+offset].Attr;
|
||||
instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
|
||||
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
// handle 3-byte escape
|
||||
@ -2553,7 +2552,6 @@ modrm_done:
|
||||
}
|
||||
|
||||
instruction->execute = OpcodeInfoPtr->ExecutePtr;
|
||||
instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
|
||||
}
|
||||
else {
|
||||
// Opcode does not require a MODRM byte.
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: io.cc,v 1.36 2006-08-01 17:09:05 vruppert Exp $
|
||||
// $Id: io.cc,v 1.37 2007-01-05 13:40:47 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -39,6 +39,10 @@
|
||||
#define RAX EAX
|
||||
#endif
|
||||
|
||||
//
|
||||
// Repeat Speedups methods
|
||||
//
|
||||
|
||||
#if BX_SupportRepeatSpeedups
|
||||
Bit32u BX_CPU_C::FastRepINSW(bxInstruction_c *i, bx_address dstOff, Bit16u port, Bit32u wordCount)
|
||||
{
|
||||
@ -281,6 +285,29 @@ Bit32u BX_CPU_C::FastRepOUTSW(bxInstruction_c *i, unsigned srcSeg, bx_address sr
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// REP INS methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::REP_INSB_YbDX(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::INSB_YbDX);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_INSW_YwDX(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::INSW_YwDX);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_INSD_YdDX(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::INSD_YdDX);
|
||||
}
|
||||
|
||||
//
|
||||
// INSB/INSW/INSD methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::INSB_YbDX(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u value8=0;
|
||||
@ -502,6 +529,29 @@ void BX_CPU_C::INSD_YdDX(bxInstruction_c *i)
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// REP OUTS methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::REP_OUTSB_DXXb(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::OUTSB_DXXb);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_OUTSW_DXXw(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::OUTSW_DXXw);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_OUTSD_DXXd(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::OUTSD_DXXd);
|
||||
}
|
||||
|
||||
//
|
||||
// OUTSB/OUTSW/OUTSD methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::OUTSB_DXXb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u value8;
|
||||
@ -701,6 +751,10 @@ void BX_CPU_C::OUTSD_DXXd(bxInstruction_c *i)
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// non repeatable IN/OUT methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::IN_ALIb(bxInstruction_c *i)
|
||||
{
|
||||
AL = BX_CPU_THIS_PTR inp8(i->Ib());
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: string.cc,v 1.35 2006-05-24 20:57:37 sshwarts Exp $
|
||||
// $Id: string.cc,v 1.36 2007-01-05 13:40:47 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -38,6 +38,9 @@
|
||||
#define RAX EAX
|
||||
#endif
|
||||
|
||||
//
|
||||
// Repeat Speedups methods
|
||||
//
|
||||
|
||||
#if BX_SupportRepeatSpeedups
|
||||
Bit32u BX_CPU_C::FastRepMOVSB(bxInstruction_c *i, unsigned srcSeg, bx_address srcOff, unsigned dstSeg, bx_address dstOff, Bit32u count)
|
||||
@ -739,6 +742,35 @@ Bit32u BX_CPU_C::FastRepSTOSD(bxInstruction_c *i, unsigned dstSeg, bx_address ds
|
||||
}
|
||||
#endif
|
||||
|
||||
//
|
||||
// REP MOVS methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::REP_MOVSB_XbYb(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::MOVSB_XbYb);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_MOVSW_XwYw(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::MOVSW_XwYw);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_MOVSD_XdYd(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::MOVSD_XdYd);
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
void BX_CPU_C::REP_MOVSQ_XqYq(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::MOVSQ_XqYq);
|
||||
}
|
||||
#endif
|
||||
|
||||
//
|
||||
// MOVSB/MOVSW/MOVSD/MOVSQ methods
|
||||
//
|
||||
|
||||
/* MOVSB ES:[EDI], DS:[ESI] DS may be overridden
|
||||
* mov string from DS:[ESI] into ES:[EDI]
|
||||
@ -1121,6 +1153,36 @@ void BX_CPU_C::MOVSQ_XqYq(bxInstruction_c *i)
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// REP CMPS methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::REP_CMPSB_XbYb(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat_ZFL(i, &BX_CPU_C::CMPSB_XbYb);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_CMPSW_XwYw(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat_ZFL(i, &BX_CPU_C::CMPSW_XwYw);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_CMPSD_XdYd(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat_ZFL(i, &BX_CPU_C::CMPSD_XdYd);
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
void BX_CPU_C::REP_CMPSQ_XqYq(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat_ZFL(i, &BX_CPU_C::CMPSQ_XqYq);
|
||||
}
|
||||
#endif
|
||||
|
||||
//
|
||||
// CMPSB/CMPSW/CMPSD/CMPSQ methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::CMPSB_XbYb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8, op2_8, diff_8;
|
||||
@ -1423,6 +1485,36 @@ void BX_CPU_C::CMPSQ_XqYq(bxInstruction_c *i)
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// REP SCAS methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::REP_SCASB_ALXb(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat_ZFL(i, &BX_CPU_C::SCASB_ALXb);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_SCASW_AXXw(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat_ZFL(i, &BX_CPU_C::SCASW_AXXw);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_SCASD_EAXXd(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat_ZFL(i, &BX_CPU_C::SCASD_EAXXd);
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
void BX_CPU_C::REP_SCASQ_RAXXq(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat_ZFL(i, &BX_CPU_C::SCASQ_RAXXq);
|
||||
}
|
||||
#endif
|
||||
|
||||
//
|
||||
// SCASB/SCASW/SCASD/SCASQ methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::SCASB_ALXb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8 = AL, op2_8, diff_8;
|
||||
@ -1661,6 +1753,36 @@ void BX_CPU_C::SCASQ_RAXXq(bxInstruction_c *i)
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// REP STOS methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::REP_STOSB_YbAL(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::STOSB_YbAL);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_STOSW_YwAX(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::STOSW_YwAX);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_STOSD_YdEAX(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::STOSD_YdEAX);
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
void BX_CPU_C::REP_STOSQ_YqRAX(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::STOSQ_YqRAX);
|
||||
}
|
||||
#endif
|
||||
|
||||
//
|
||||
// STOSB/STOSW/STOSD/STOSQ methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::STOSB_YbAL(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u al = AL;
|
||||
@ -1906,6 +2028,36 @@ void BX_CPU_C::STOSQ_YqRAX(bxInstruction_c *i)
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// REP LODS methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::REP_LODSB_ALXb(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::LODSB_ALXb);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_LODSW_AXXw(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::LODSW_AXXw);
|
||||
}
|
||||
|
||||
void BX_CPU_C::REP_LODSD_EAXXd(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::LODSD_EAXXd);
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
void BX_CPU_C::REP_LODSQ_RAXXq(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR repeat(i, &BX_CPU_C::LODSQ_RAXXq);
|
||||
}
|
||||
#endif
|
||||
|
||||
//
|
||||
// LODSB/LODSW/LODSD/LODSQ methods
|
||||
//
|
||||
|
||||
void BX_CPU_C::LODSB_ALXb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u al;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user