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This commit is the first commit in long series of changes the have several purposes:

Browse Source 
1. Review and commit patch

	[ 896733 ] Lazy flags, for more instructions, only 1 src op

   May be partially, but I hope to get all ideas from patch in

2. Get Bochs speedup after lazy flags optimization

3. Most important for me: improve correctness of emulation by handling several
   undocumented EFLAGS modifications. And finally pass

	UFLAGS - Undefined Flags Test v 3.0
	Copyright (C) Potemkin's Hackers Group (PHG) 1989,1995

   The test still fails on > 50% of its checks.
This commit is contained in:
Stanislav Shwartsman 2004-08-09 21:28:47 +00:00
parent d06c80cee3
commit 8f0cf91fff
22 changed files with 289 additions and 693 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
bochs/cpu/Makefile.in
View File

@ -107,8 +107,7 @@ OBJS = \
bit.o \
string.o \
paging.o \
$(EXT_DEBUG_OBJS) \
$(EXT_DEBUG_OBJS)
# Objects which are only used for x86-64 code
OBJS64 = \
@ -120,8 +119,7 @@ OBJS64 = \
mult64.o \
resolve64.o \
shift64.o \
stack64.o \
stack64.o
BX_INCLUDES = ../bochs.h ../config.h

69
bochs/cpu/arith16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith16.cc,v 1.29 2004-02-15 17:57:43 cbothamy Exp $
// $Id: arith16.cc,v 1.30 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -38,13 +38,11 @@ BX_CPU_C::INC_RX(bxInstruction_c *i)
{
#if defined(BX_HostAsm_Inc16)
Bit32u flags32;
asmInc16(BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].word.rx, flags32);
setEFlagsOSZAP(flags32);
#else
Bit16u rx;
rx = ++ BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].word.rx;
SET_FLAGS_OSZAP_16(0, 0, rx, BX_INSTR_INC16);
#endif
}
@ -54,14 +52,11 @@ BX_CPU_C::DEC_RX(bxInstruction_c *i)
{
#if defined(BX_HostAsm_Dec16)
Bit32u flags32;
asmDec16(BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].word.rx, flags32);
setEFlagsOSZAP(flags32);
#else
Bit16u rx;
rx = -- BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].word.rx;
SET_FLAGS_OSZAP_16(0, 0, rx, BX_INSTR_DEC16);
#endif
}
@ -101,7 +96,6 @@ BX_CPU_C::ADD_GwEEw(bxInstruction_c *i)
#if defined(BX_HostAsm_Add16)
Bit32u flags32;
asmAdd16(sum_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -159,10 +153,9 @@ BX_CPU_C::ADD_AXIw(bxInstruction_c *i)
void
BX_CPU_C::ADC_EwGw(bxInstruction_c *i)
{
bx_bool temp_CF;
Bit16u op2_16, op1_16, sum_16;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op2_16 = BX_READ_16BIT_REG(i->nnn());
@ -177,19 +170,15 @@ BX_CPU_C::ADC_EwGw(bxInstruction_c *i)
Write_RMW_virtual_word(sum_16);
}
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16,
temp_CF);
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16, temp_CF);
}
void
BX_CPU_C::ADC_GwEw(bxInstruction_c *i)
{
bx_bool temp_CF;
Bit16u op1_16, op2_16, sum_16;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op1_16 = BX_READ_16BIT_REG(i->nnn());
@ -204,18 +193,15 @@ BX_CPU_C::ADC_GwEw(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), sum_16);
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16,
temp_CF);
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16, temp_CF);
}
void
BX_CPU_C::ADC_AXIw(bxInstruction_c *i)
{
bx_bool temp_CF;
Bit16u op1_16, op2_16, sum_16;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op1_16 = AX;
op2_16 = i->Iw();
@ -224,13 +210,10 @@ BX_CPU_C::ADC_AXIw(bxInstruction_c *i)
AX = sum_16;
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16,
temp_CF);
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16, temp_CF);
}
void
BX_CPU_C::SBB_EwGw(bxInstruction_c *i)
{
@ -260,11 +243,8 @@ BX_CPU_C::SBB_EwGw(bxInstruction_c *i)
void
BX_CPU_C::SBB_GwEw(bxInstruction_c *i)
{
bx_bool temp_CF;
temp_CF = getB_CF();
Bit16u op1_16, op2_16, diff_16;
bx_bool temp_CF = getB_CF();
op1_16 = BX_READ_16BIT_REG(i->nnn());
@ -287,10 +267,8 @@ BX_CPU_C::SBB_GwEw(bxInstruction_c *i)
void
BX_CPU_C::SBB_AXIw(bxInstruction_c *i)
{
bx_bool temp_CF;
Bit16u op1_16, op2_16, diff_16;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op1_16 = AX;
op2_16 = i->Iw();
@ -303,15 +281,11 @@ BX_CPU_C::SBB_AXIw(bxInstruction_c *i)
temp_CF);
}
void
BX_CPU_C::SBB_EwIw(bxInstruction_c *i)
{
bx_bool temp_CF;
Bit16u op2_16, op1_16, diff_16;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op2_16 = i->Iw();
@ -342,7 +316,6 @@ BX_CPU_C::SUB_EwGw(bxInstruction_c *i)
op1_16 = BX_READ_16BIT_REG(i->rm());
#if defined(BX_HostAsm_Sub16)
Bit32u flags32;
asmSub16(diff_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -354,7 +327,6 @@ BX_CPU_C::SUB_EwGw(bxInstruction_c *i)
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
#if defined(BX_HostAsm_Sub16)
Bit32u flags32;
asmSub16(diff_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -386,7 +358,6 @@ BX_CPU_C::SUB_GwEw(bxInstruction_c *i)
#if defined(BX_HostAsm_Sub16)
Bit32u flags32;
asmSub16(diff_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -410,7 +381,6 @@ BX_CPU_C::SUB_AXIw(bxInstruction_c *i)
#if defined(BX_HostAsm_Sub16)
Bit32u flags32;
asmSub16(diff_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -491,7 +461,6 @@ BX_CPU_C::CMP_AXIw(bxInstruction_c *i)
#if defined(BX_HostAsm_Cmp16)
Bit32u flags32;
asmCmp16(op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -565,7 +534,6 @@ BX_CPU_C::XADD_EwGw(bxInstruction_c *i)
}
void
BX_CPU_C::ADD_EEwIw(bxInstruction_c *i)
{
@ -577,7 +545,6 @@ BX_CPU_C::ADD_EEwIw(bxInstruction_c *i)
#if defined(BX_HostAsm_Add16)
Bit32u flags32;
asmAdd16(sum_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -601,7 +568,6 @@ BX_CPU_C::ADD_EGwIw(bxInstruction_c *i)
#if defined(BX_HostAsm_Add16)
Bit32u flags32;
asmAdd16(sum_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -617,10 +583,8 @@ BX_CPU_C::ADD_EGwIw(bxInstruction_c *i)
void
BX_CPU_C::ADC_EwIw(bxInstruction_c *i)
{
bx_bool temp_CF;
Bit16u op2_16, op1_16, sum_16;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op2_16 = i->Iw();
@ -635,8 +599,7 @@ BX_CPU_C::ADC_EwIw(bxInstruction_c *i)
Write_RMW_virtual_word(sum_16);
}
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16,
temp_CF);
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16, temp_CF);
}
@ -645,7 +608,6 @@ BX_CPU_C::SUB_EwIw(bxInstruction_c *i)
{
Bit16u op2_16, op1_16, diff_16;
op2_16 = i->Iw();
if (i->modC0()) {
@ -694,7 +656,6 @@ BX_CPU_C::CMP_EwIw(bxInstruction_c *i)
#if defined(BX_HostAsm_Cmp16)
Bit32u flags32;
asmCmp16(op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -712,7 +673,6 @@ BX_CPU_C::NEG_Ew(bxInstruction_c *i)
{
Bit16u op1_16, diff_16;
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
diff_16 = 0 - op1_16;
@ -756,7 +716,6 @@ BX_CPU_C::DEC_Ew(bxInstruction_c *i)
if (i->modC0()) {
#if defined(BX_HostAsm_Dec16)
Bit32u flags32;
asmDec16(BX_CPU_THIS_PTR gen_reg[i->rm()].word.rx, flags32);
setEFlagsOSZAP(flags32);
#else
@ -788,7 +747,6 @@ BX_CPU_C::DEC_Ew(bxInstruction_c *i)
BX_CPU_C::CMPXCHG_EwGw(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit16u op2_16, op1_16, diff_16;
if (i->modC0()) {
@ -823,6 +781,7 @@ BX_CPU_C::CMPXCHG_EwGw(bxInstruction_c *i)
}
#else
BX_PANIC(("CMPXCHG_EwGw:"));
BX_INFO(("CMPXCHG_EwGw: not supported for cpulevel <= 3"));
UndefinedOpcode(i);
#endif
}

103
bochs/cpu/arith32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith32.cc,v 1.32 2004-02-15 17:57:43 cbothamy Exp $
// $Id: arith32.cc,v 1.33 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -45,12 +45,10 @@ BX_CPU_C::INC_ERX(bxInstruction_c *i)
{
#if defined(BX_HostAsm_Inc32)
Bit32u flags32;
asmInc32(BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].dword.erx, flags32);
setEFlagsOSZAP(flags32);
#else
Bit32u erx;
erx = ++ BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].dword.erx;
#endif
@ -68,12 +66,10 @@ BX_CPU_C::DEC_ERX(bxInstruction_c *i)
{
#if defined(BX_HostAsm_Dec32)
Bit32u flags32;
asmDec32(BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].dword.erx, flags32);
setEFlagsOSZAP(flags32);
#else
Bit32u erx;
erx = -- BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].dword.erx;
#endif
@ -86,9 +82,6 @@ BX_CPU_C::DEC_ERX(bxInstruction_c *i)
#endif
}
void
BX_CPU_C::ADD_EdGd(bxInstruction_c *i)
{
@ -123,7 +116,6 @@ BX_CPU_C::ADD_GdEEd(bxInstruction_c *i)
#if defined(BX_HostAsm_Add32)
Bit32u flags32;
asmAdd32(sum_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -148,7 +140,6 @@ BX_CPU_C::ADD_GdEGd(bxInstruction_c *i)
#if defined(BX_HostAsm_Add32)
Bit32u flags32;
asmAdd32(sum_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -181,9 +172,7 @@ BX_CPU_C::ADD_EAXId(bxInstruction_c *i)
void
BX_CPU_C::ADC_EdGd(bxInstruction_c *i)
{
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
Bit32u op2_32, op1_32, sum_32;
@ -200,17 +189,14 @@ BX_CPU_C::ADC_EdGd(bxInstruction_c *i)
Write_RMW_virtual_dword(sum_32);
}
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32,
temp_CF);
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32, temp_CF);
}
void
BX_CPU_C::ADC_GdEd(bxInstruction_c *i)
{
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
Bit32u op1_32, op2_32, sum_32;
@ -227,17 +213,14 @@ BX_CPU_C::ADC_GdEd(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32,
temp_CF);
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32, temp_CF);
}
void
BX_CPU_C::ADC_EAXId(bxInstruction_c *i)
{
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
Bit32u op1_32, op2_32, sum_32;
@ -248,19 +231,13 @@ BX_CPU_C::ADC_EAXId(bxInstruction_c *i)
RAX = sum_32;
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32,
temp_CF);
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32, temp_CF);
}
void
BX_CPU_C::SBB_EdGd(bxInstruction_c *i)
{
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
Bit32u op2_32, op1_32, diff_32;
@ -277,17 +254,14 @@ BX_CPU_C::SBB_EdGd(bxInstruction_c *i)
Write_RMW_virtual_dword(diff_32);
}
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32,
temp_CF);
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32, temp_CF);
}
void
BX_CPU_C::SBB_GdEd(bxInstruction_c *i)
{
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
Bit32u op1_32, op2_32, diff_32;
@ -304,17 +278,14 @@ BX_CPU_C::SBB_GdEd(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->nnn(), diff_32);
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32,
temp_CF);
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32, temp_CF);
}
void
BX_CPU_C::SBB_EAXId(bxInstruction_c *i)
{
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
Bit32u op1_32, op2_32, diff_32;
@ -325,18 +296,13 @@ BX_CPU_C::SBB_EAXId(bxInstruction_c *i)
RAX = diff_32;
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32,
temp_CF);
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32, temp_CF);
}
void
BX_CPU_C::SBB_EdId(bxInstruction_c *i)
{
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
Bit32u op2_32, op1_32, diff_32;
@ -353,8 +319,7 @@ BX_CPU_C::SBB_EdId(bxInstruction_c *i)
Write_RMW_virtual_dword(diff_32);
}
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32,
temp_CF);
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32, temp_CF);
}
@ -397,7 +362,6 @@ BX_CPU_C::SUB_GdEd(bxInstruction_c *i)
#if defined(BX_HostAsm_Sub32)
Bit32u flags32;
asmSub32(diff_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -443,13 +407,11 @@ BX_CPU_C::CMP_EdGd(bxInstruction_c *i)
#if defined(BX_HostAsm_Cmp32)
Bit32u flags32;
asmCmp32(op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit32u diff_32;
diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
#endif
}
@ -471,13 +433,11 @@ BX_CPU_C::CMP_GdEd(bxInstruction_c *i)
#if defined(BX_HostAsm_Cmp32)
Bit32u flags32;
asmCmp32(op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit32u diff_32;
diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
#endif
}
@ -493,13 +453,11 @@ BX_CPU_C::CMP_EAXId(bxInstruction_c *i)
#if defined(BX_HostAsm_Cmp32)
Bit32u flags32;
asmCmp32(op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit32u diff_32;
diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
#endif
}
@ -509,9 +467,7 @@ BX_CPU_C::CMP_EAXId(bxInstruction_c *i)
BX_CPU_C::CWDE(bxInstruction_c *i)
{
/* CBW: no flags are effected */
Bit32u temp;
temp = (Bit16s) AX;
Bit32u temp = (Bit16s) AX;
RAX = temp;
}
@ -596,8 +552,6 @@ BX_CPU_C::XADD_EdGd(bxInstruction_c *i)
#endif
}
void
BX_CPU_C::ADD_EEdId(bxInstruction_c *i)
{
@ -609,7 +563,6 @@ BX_CPU_C::ADD_EEdId(bxInstruction_c *i)
#if defined(BX_HostAsm_Add32)
Bit32u flags32;
asmAdd32(sum_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -633,7 +586,6 @@ BX_CPU_C::ADD_EGdId(bxInstruction_c *i)
#if defined(BX_HostAsm_Add32)
Bit32u flags32;
asmAdd32(sum_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -650,9 +602,7 @@ BX_CPU_C::ADD_EGdId(bxInstruction_c *i)
void
BX_CPU_C::ADC_EdId(bxInstruction_c *i)
{
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
Bit32u op2_32, op1_32, sum_32;
@ -669,8 +619,7 @@ BX_CPU_C::ADC_EdId(bxInstruction_c *i)
Write_RMW_virtual_dword(sum_32);
}
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32,
temp_CF);
SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32, temp_CF);
}
@ -711,20 +660,15 @@ BX_CPU_C::CMP_EdId(bxInstruction_c *i)
#if defined(BX_HostAsm_Cmp32)
Bit32u flags32;
asmCmp32(op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit32u diff_32;
diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_CMP32);
#endif
}
void
BX_CPU_C::NEG_Ed(bxInstruction_c *i)
{
@ -789,7 +733,6 @@ BX_CPU_C::DEC_Ed(bxInstruction_c *i)
BX_CPU_C::CMPXCHG_EdGd(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit32u op2_32, op1_32, diff_32;
if (i->modC0()) {
@ -823,7 +766,8 @@ BX_CPU_C::CMPXCHG_EdGd(bxInstruction_c *i)
RAX = op1_32;
}
#else
BX_PANIC(("CMPXCHG_EdGd:"));
BX_INFO(("CMPXCHG_EdGd: not supported for cpulevel <= 3"));
UndefinedOpcode(i);
#endif
}
@ -831,7 +775,6 @@ BX_CPU_C::CMPXCHG_EdGd(bxInstruction_c *i)
BX_CPU_C::CMPXCHG8B(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 5) || (BX_CPU_LEVEL_HACKED >= 5)
Bit32u op1_64_lo, op1_64_hi, diff;
if (i->modC0()) {
@ -842,11 +785,9 @@ BX_CPU_C::CMPXCHG8B(bxInstruction_c *i)
read_virtual_dword(i->seg(), RMAddr(i), &op1_64_lo);
read_RMW_virtual_dword(i->seg(), RMAddr(i) + 4, &op1_64_hi);
diff = EAX - op1_64_lo;
diff = EAX - op1_64_lo;
diff |= EDX - op1_64_hi;
// SET_FLAGS_OSZAPC_32(EAX, op1_32, diff_32, BX_INSTR_CMP32);
if (diff == 0) { // if accumulator == dest
// ZF = 1
set_ZF(1);
@ -863,7 +804,7 @@ BX_CPU_C::CMPXCHG8B(bxInstruction_c *i)
}
#else
BX_INFO(("CMPXCHG8B: not implemented in CPU_LEVEL < 5"));
BX_INFO(("CMPXCHG8B: not supported for cpulevel <= 4"));
UndefinedOpcode(i);
#endif
}

29
bochs/cpu/arith64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith64.cc,v 1.15 2004-04-07 19:22:59 sshwarts Exp $
// $Id: arith64.cc,v 1.16 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -99,7 +99,6 @@ BX_CPU_C::ADD_RAXId(bxInstruction_c *i)
Bit64u op1_64, op2_64, sum_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
sum_64 = op1_64 + op2_64;
@ -140,8 +139,7 @@ BX_CPU_C::ADC_EqGq(bxInstruction_c *i)
Write_RMW_virtual_qword(sum_64);
}
SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, sum_64, BX_INSTR_ADC64,
temp_CF);
SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, sum_64, BX_INSTR_ADC64, temp_CF);
}
void
@ -182,9 +180,7 @@ BX_CPU_C::ADC_RAXId(bxInstruction_c *i)
Bit64u op1_64, op2_64, sum_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
sum_64 = op1_64 + op2_64 + temp_CF;
/* now write sum back to destination */
@ -224,8 +220,7 @@ BX_CPU_C::SBB_EqGq(bxInstruction_c *i)
Write_RMW_virtual_qword(diff_64);
}
SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, diff_64, BX_INSTR_SBB64,
temp_CF);
SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, diff_64, BX_INSTR_SBB64, temp_CF);
}
void
@ -253,8 +248,7 @@ BX_CPU_C::SBB_GqEq(bxInstruction_c *i)
/* now write diff back to destination */
BX_WRITE_64BIT_REG(i->nnn(), diff_64);
SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, diff_64, BX_INSTR_SBB64,
temp_CF);
SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, diff_64, BX_INSTR_SBB64, temp_CF);
}
void
@ -266,16 +260,13 @@ BX_CPU_C::SBB_RAXId(bxInstruction_c *i)
Bit64u op1_64, op2_64, diff_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
diff_64 = op1_64 - (op2_64 + temp_CF);
/* now write diff back to destination */
RAX = diff_64;
SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, diff_64, BX_INSTR_SBB64,
temp_CF);
SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, diff_64, BX_INSTR_SBB64, temp_CF);
}
void
@ -307,8 +298,7 @@ BX_CPU_C::SBB_EqId(bxInstruction_c *i)
Write_RMW_virtual_qword(diff_64);
}
SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, diff_64, BX_INSTR_SBB64,
temp_CF);
SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, diff_64, BX_INSTR_SBB64, temp_CF);
}
void
@ -375,9 +365,7 @@ BX_CPU_C::SUB_RAXId(bxInstruction_c *i)
Bit64u op1_64, op2_64, diff_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
diff_64 = op1_64 - op2_64;
/* now write diff back to destination */
@ -440,9 +428,7 @@ BX_CPU_C::CMP_RAXId(bxInstruction_c *i)
Bit64u op1_64, op2_64, diff_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_CMP64);
@ -569,8 +555,7 @@ BX_CPU_C::ADC_EqId(bxInstruction_c *i)
Write_RMW_virtual_qword(sum_64);
}
SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, sum_64, BX_INSTR_ADC64,
temp_CF);
SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, sum_64, BX_INSTR_ADC64, temp_CF);
}
void

85
bochs/cpu/arith8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith8.cc,v 1.25 2004-02-15 17:57:43 cbothamy Exp $
// $Id: arith8.cc,v 1.26 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -34,8 +34,6 @@
void
BX_CPU_C::ADD_EbGb(bxInstruction_c *i)
{
@ -58,7 +56,6 @@ BX_CPU_C::ADD_EbGb(bxInstruction_c *i)
}
void
BX_CPU_C::ADD_GbEb(bxInstruction_c *i)
{
@ -86,12 +83,9 @@ BX_CPU_C::ADD_ALIb(bxInstruction_c *i)
{
Bit8u op1, op2, sum;
op1 = AL;
op2 = i->Ib();
sum = op1 + op2;
AL = sum;
SET_FLAGS_OSZAPC_8(op1, op2, sum, BX_INSTR_ADD8);
@ -102,9 +96,7 @@ BX_CPU_C::ADD_ALIb(bxInstruction_c *i)
BX_CPU_C::ADC_EbGb(bxInstruction_c *i)
{
Bit8u op2, op1, sum;
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
@ -127,9 +119,7 @@ BX_CPU_C::ADC_EbGb(bxInstruction_c *i)
BX_CPU_C::ADC_GbEb(bxInstruction_c *i)
{
Bit8u op1, op2, sum;
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op1 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
@ -153,20 +143,14 @@ BX_CPU_C::ADC_GbEb(bxInstruction_c *i)
BX_CPU_C::ADC_ALIb(bxInstruction_c *i)
{
Bit8u op1, op2, sum;
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op1 = AL;
op2 = i->Ib();
sum = op1 + op2 + temp_CF;
AL = sum;
SET_FLAGS_OSZAPC_8_CF(op1, op2, sum, BX_INSTR_ADC8,
temp_CF);
SET_FLAGS_OSZAPC_8_CF(op1, op2, sum, BX_INSTR_ADC8, temp_CF);
}
@ -174,10 +158,7 @@ BX_CPU_C::ADC_ALIb(bxInstruction_c *i)
BX_CPU_C::SBB_EbGb(bxInstruction_c *i)
{
Bit8u op2_8, op1_8, diff_8;
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op2_8 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
@ -192,8 +173,7 @@ BX_CPU_C::SBB_EbGb(bxInstruction_c *i)
Write_RMW_virtual_byte(diff_8);
}
SET_FLAGS_OSZAPC_8_CF(op1_8, op2_8, diff_8, BX_INSTR_SBB8,
temp_CF);
SET_FLAGS_OSZAPC_8_CF(op1_8, op2_8, diff_8, BX_INSTR_SBB8, temp_CF);
}
@ -201,9 +181,7 @@ BX_CPU_C::SBB_EbGb(bxInstruction_c *i)
BX_CPU_C::SBB_GbEb(bxInstruction_c *i)
{
Bit8u op1_8, op2_8, diff_8;
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op1_8 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
@ -218,8 +196,7 @@ BX_CPU_C::SBB_GbEb(bxInstruction_c *i)
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), diff_8);
SET_FLAGS_OSZAPC_8_CF(op1_8, op2_8, diff_8, BX_INSTR_SBB8,
temp_CF);
SET_FLAGS_OSZAPC_8_CF(op1_8, op2_8, diff_8, BX_INSTR_SBB8, temp_CF);
}
@ -227,19 +204,14 @@ BX_CPU_C::SBB_GbEb(bxInstruction_c *i)
BX_CPU_C::SBB_ALIb(bxInstruction_c *i)
{
Bit8u op1_8, op2_8, diff_8;
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op1_8 = AL;
op2_8 = i->Ib();
diff_8 = op1_8 - (op2_8 + temp_CF);
AL = diff_8;
SET_FLAGS_OSZAPC_8_CF(op1_8, op2_8, diff_8, BX_INSTR_SBB8,
temp_CF);
SET_FLAGS_OSZAPC_8_CF(op1_8, op2_8, diff_8, BX_INSTR_SBB8, temp_CF);
}
@ -247,9 +219,7 @@ BX_CPU_C::SBB_ALIb(bxInstruction_c *i)
BX_CPU_C::SBB_EbIb(bxInstruction_c *i)
{
Bit8u op2_8, op1_8, diff_8;
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op2_8 = i->Ib();
@ -264,12 +234,10 @@ BX_CPU_C::SBB_EbIb(bxInstruction_c *i)
Write_RMW_virtual_byte(diff_8);
}
SET_FLAGS_OSZAPC_8_CF(op1_8, op2_8, diff_8, BX_INSTR_SBB8,
temp_CF);
SET_FLAGS_OSZAPC_8_CF(op1_8, op2_8, diff_8, BX_INSTR_SBB8, temp_CF);
}
void
BX_CPU_C::SUB_EbGb(bxInstruction_c *i)
{
@ -321,16 +289,13 @@ BX_CPU_C::SUB_ALIb(bxInstruction_c *i)
op1_8 = AL;
op2_8 = i->Ib();
diff_8 = op1_8 - op2_8;
AL = diff_8;
SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_SUB8);
}
void
BX_CPU_C::CMP_EbGb(bxInstruction_c *i)
{
@ -347,13 +312,11 @@ BX_CPU_C::CMP_EbGb(bxInstruction_c *i)
#if defined(BX_HostAsm_Cmp8)
Bit32u flags32;
asmCmp8(op1_8, op2_8, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit8u diff_8;
diff_8 = op1_8 - op2_8;
SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_CMP8);
#endif
}
@ -375,37 +338,31 @@ BX_CPU_C::CMP_GbEb(bxInstruction_c *i)
#if defined(BX_HostAsm_Cmp8)
Bit32u flags32;
asmCmp8(op1_8, op2_8, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit8u diff_8;
diff_8 = op1_8 - op2_8;
SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_CMP8);
#endif
}
void
BX_CPU_C::CMP_ALIb(bxInstruction_c *i)
{
Bit8u op1_8, op2_8;
op1_8 = AL;
op2_8 = i->Ib();
#if defined(BX_HostAsm_Cmp8)
Bit32u flags32;
asmCmp8(op1_8, op2_8, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit8u diff_8;
diff_8 = op1_8 - op2_8;
SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_CMP8);
#endif
}
@ -415,7 +372,6 @@ BX_CPU_C::CMP_ALIb(bxInstruction_c *i)
BX_CPU_C::XADD_EbGb(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit8u op2, op1, sum;
/* XADD dst(r/m8), src(r8)
@ -446,7 +402,8 @@ BX_CPU_C::XADD_EbGb(bxInstruction_c *i)
SET_FLAGS_OSZAPC_8(op1, op2, sum, BX_INSTR_XADD8);
#else
BX_PANIC(("XADD_EbGb: not supported on < 80486"));
BX_INFO(("XADD_EbGb: not supported on < 80486"));
UndefinedOpcode(i);
#endif
}
@ -476,9 +433,7 @@ BX_CPU_C::ADD_EbIb(bxInstruction_c *i)
BX_CPU_C::ADC_EbIb(bxInstruction_c *i)
{
Bit8u op2, op1, sum;
bx_bool temp_CF;
temp_CF = getB_CF();
bx_bool temp_CF = getB_CF();
op2 = i->Ib();
@ -493,8 +448,7 @@ BX_CPU_C::ADC_EbIb(bxInstruction_c *i)
Write_RMW_virtual_byte(sum);
}
SET_FLAGS_OSZAPC_8_CF(op1, op2, sum, BX_INSTR_ADC8,
temp_CF);
SET_FLAGS_OSZAPC_8_CF(op1, op2, sum, BX_INSTR_ADC8, temp_CF);
}
@ -535,13 +489,11 @@ BX_CPU_C::CMP_EbIb(bxInstruction_c *i)
#if defined(BX_HostAsm_Cmp8)
Bit32u flags32;
asmCmp8(op1_8, op2_8, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit8u diff_8;
diff_8 = op1_8 - op2_8;
SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_CMP8);
#endif
}
@ -613,7 +565,6 @@ BX_CPU_C::CMPXCHG_EbGb(bxInstruction_c *i)
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit8u op2_8, op1_8, diff_8;
if (i->modC0()) {
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
@ -646,6 +597,6 @@ BX_CPU_C::CMPXCHG_EbGb(bxInstruction_c *i)
}
#else
BX_PANIC(("CMPXCHG_EbGb:"));
BX_PANIC(("CMPXCHG_EbGb: not supported for cpulevel <= 3"));
#endif
}

100
bochs/cpu/bit.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bit.cc,v 1.16 2004-07-08 20:15:22 sshwarts Exp $
// $Id: bit.cc,v 1.17 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -26,8 +26,6 @@
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
@ -51,7 +49,8 @@
BX_CPU_C::SETO_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETO: not available on < 386"));
BX_INFO(("SETO: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -74,7 +73,8 @@ BX_CPU_C::SETO_Eb(bxInstruction_c *i)
BX_CPU_C::SETNO_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETNO: not available on < 386"));
BX_INFO(("SETNO: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -97,7 +97,8 @@ BX_CPU_C::SETNO_Eb(bxInstruction_c *i)
BX_CPU_C::SETB_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETB: not available on < 386"));
BX_INFO(("SETB: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -120,7 +121,8 @@ BX_CPU_C::SETB_Eb(bxInstruction_c *i)
BX_CPU_C::SETNB_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETNB: not available on < 386"));
BX_INFO(("SETNB: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -143,7 +145,8 @@ BX_CPU_C::SETNB_Eb(bxInstruction_c *i)
BX_CPU_C::SETZ_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETZ: not available on < 386"));
BX_INFO(("SETZ: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -166,7 +169,8 @@ BX_CPU_C::SETZ_Eb(bxInstruction_c *i)
BX_CPU_C::SETNZ_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETNZ: not available on < 386"));
BX_INFO(("SETNZ: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -189,7 +193,8 @@ BX_CPU_C::SETNZ_Eb(bxInstruction_c *i)
BX_CPU_C::SETBE_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETBE: not available on < 386"));
BX_INFO(("SETBE: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -212,7 +217,8 @@ BX_CPU_C::SETBE_Eb(bxInstruction_c *i)
BX_CPU_C::SETNBE_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETNBE: not available on < 386"));
BX_INFO(("SETNBE: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -235,7 +241,8 @@ BX_CPU_C::SETNBE_Eb(bxInstruction_c *i)
BX_CPU_C::SETS_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETS: not available on < 386"));
BX_INFO(("SETS: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -258,7 +265,8 @@ BX_CPU_C::SETS_Eb(bxInstruction_c *i)
BX_CPU_C::SETNS_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETNL: not available on < 386"));
BX_INFO(("SETNL: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -281,7 +289,8 @@ BX_CPU_C::SETNS_Eb(bxInstruction_c *i)
BX_CPU_C::SETP_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETP: not available on < 386"));
BX_INFO(("SETP: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -304,7 +313,8 @@ BX_CPU_C::SETP_Eb(bxInstruction_c *i)
BX_CPU_C::SETNP_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETNP: not available on < 386"));
BX_INFO(("SETNP: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -327,7 +337,8 @@ BX_CPU_C::SETNP_Eb(bxInstruction_c *i)
BX_CPU_C::SETL_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETL: not available on < 386"));
BX_INFO(("SETL: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -350,7 +361,8 @@ BX_CPU_C::SETL_Eb(bxInstruction_c *i)
BX_CPU_C::SETNL_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETNL: not available on < 386"));
BX_INFO(("SETNL: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -373,7 +385,8 @@ BX_CPU_C::SETNL_Eb(bxInstruction_c *i)
BX_CPU_C::SETLE_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETLE: not available on < 386"));
BX_INFO(("SETLE: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -396,7 +409,8 @@ BX_CPU_C::SETLE_Eb(bxInstruction_c *i)
BX_CPU_C::SETNLE_Eb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("SETNLE: not available on < 386"));
BX_INFO(("SETNLE: not available on < 386"));
UndefinedOpcode(i);
#else
Bit8u result_8;
@ -419,7 +433,8 @@ BX_CPU_C::SETNLE_Eb(bxInstruction_c *i)
BX_CPU_C::BSF_GvEv(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("BSF_GvEv(): not supported on < 386"));
BX_INFO(("BSF_GvEv(): not supported on < 386"));
UndefinedOpcode(i);
#else
#if BX_SUPPORT_X86_64
@ -515,7 +530,8 @@ BX_CPU_C::BSF_GvEv(bxInstruction_c *i)
BX_CPU_C::BSR_GvEv(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("BSR_GvEv(): not supported on < 386"));
BX_INFO(("BSR_GvEv(): not supported on < 386"));
UndefinedOpcode(i);
#else
#if BX_SUPPORT_X86_64
@ -543,7 +559,7 @@ BX_CPU_C::BSR_GvEv(bxInstruction_c *i)
op2_64 <<= 1;
}
set_ZF(0);
/* now write result back to destination */
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
}
@ -621,7 +637,7 @@ BX_CPU_C::BSWAP_EAX(bxInstruction_c *i)
RAX = (b0<<24) | (b1<<16) | (b2<<8) | b3; // zero extended
#else
BX_PANIC(("BSWAP_EAX: not implemented CPU <= 3"));
BX_INFO(("BSWAP_EAX: not implemented CPU <= 3"));
UndefinedOpcode(i);
#endif
}
@ -640,7 +656,7 @@ BX_CPU_C::BSWAP_ECX(bxInstruction_c *i)
RCX = (b0<<24) | (b1<<16) | (b2<<8) | b3;
#else
BX_PANIC(("BSWAP_ECX: not implemented CPU <= 3"));
BX_INFO(("BSWAP_ECX: not implemented CPU <= 3"));
UndefinedOpcode(i);
#endif
}
@ -659,7 +675,7 @@ BX_CPU_C::BSWAP_EDX(bxInstruction_c *i)
RDX = (b0<<24) | (b1<<16) | (b2<<8) | b3;
#else
BX_PANIC(("BSWAP_EDX: not implemented CPU <= 3"));
BX_INFO(("BSWAP_EDX: not implemented CPU <= 3"));
UndefinedOpcode(i);
#endif
}
@ -678,7 +694,7 @@ BX_CPU_C::BSWAP_EBX(bxInstruction_c *i)
RBX = (b0<<24) | (b1<<16) | (b2<<8) | b3;
#else
BX_PANIC(("BSWAP_EBX: not implemented CPU <= 3"));
BX_INFO(("BSWAP_EBX: not implemented CPU <= 3"));
UndefinedOpcode(i);
#endif
}
@ -698,7 +714,7 @@ BX_CPU_C::BSWAP_ESP(bxInstruction_c *i)
RSP = (b0<<24) | (b1<<16) | (b2<<8) | b3;
#else
BX_PANIC(("BSWAP_ESP: not implemented CPU <= 3"));
BX_INFO(("BSWAP_ESP: not implemented CPU <= 3"));
UndefinedOpcode(i);
#endif
}
@ -718,7 +734,7 @@ BX_CPU_C::BSWAP_EBP(bxInstruction_c *i)
RBP = (b0<<24) | (b1<<16) | (b2<<8) | b3;
#else
BX_PANIC(("BSWAP_EBP: not implemented CPU <= 3"));
BX_INFO(("BSWAP_EBP: not implemented CPU <= 3"));
UndefinedOpcode(i);
#endif
}
@ -738,7 +754,7 @@ BX_CPU_C::BSWAP_ESI(bxInstruction_c *i)
RSI = (b0<<24) | (b1<<16) | (b2<<8) | b3;
#else
BX_PANIC(("BSWAP_ESI: not implemented CPU <= 3"));
BX_INFO(("BSWAP_ESI: not implemented CPU <= 3"));
UndefinedOpcode(i);
#endif
}
@ -758,7 +774,7 @@ BX_CPU_C::BSWAP_EDI(bxInstruction_c *i)
RDI = (b0<<24) | (b1<<16) | (b2<<8) | b3;
#else
BX_PANIC(("BSWAP_EDI: not implemented CPU <= 3"));
BX_INFO(("BSWAP_EDI: not implemented CPU <= 3"));
UndefinedOpcode(i);
#endif
}
@ -914,7 +930,8 @@ BX_CPU_C::BSWAP_RDI(bxInstruction_c *i)
BX_CPU_C::BT_EvGv(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("BT_EvGv: not available on <386"));
BX_INFO(("BT_EvGv: not available on <386"));
UndefinedOpcode(i);
#else
bx_address op1_addr;
@ -1003,7 +1020,8 @@ BX_CPU_C::BT_EvGv(bxInstruction_c *i)
BX_CPU_C::BTS_EvGv(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("BTS_EvGv: not available on <386"));
BX_INFO(("BTS_EvGv: not available on <386"));
UndefinedOpcode(i);
#else
bx_address op1_addr;
@ -1119,7 +1137,8 @@ BX_CPU_C::BTS_EvGv(bxInstruction_c *i)
BX_CPU_C::BTR_EvGv(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("BTR_EvGv: not available on <386"));
BX_INFO(("BTR_EvGv: not available on <386"));
UndefinedOpcode(i);
#else
bx_address op1_addr;
@ -1238,7 +1257,8 @@ BX_CPU_C::BTR_EvGv(bxInstruction_c *i)
BX_CPU_C::BTC_EvGv(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("BTC_EvGv: not available on <386"));
BX_INFO(("BTC_EvGv: not available on <386"));
UndefinedOpcode(i);
#else
bx_address op1_addr;
@ -1353,7 +1373,8 @@ BX_CPU_C::BTC_EvGv(bxInstruction_c *i)
BX_CPU_C::BT_EvIb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("BT_EvIb: not available on <386"));
BX_INFO(("BT_EvIb: not available on <386"));
UndefinedOpcode(i);
#else
#if BX_SUPPORT_X86_64
@ -1422,7 +1443,8 @@ BX_CPU_C::BT_EvIb(bxInstruction_c *i)
BX_CPU_C::BTS_EvIb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("BTS_EvIb: not available on <386"));
BX_INFO(("BTS_EvIb: not available on <386"));
UndefinedOpcode(i);
#else
#if BX_SUPPORT_X86_64
@ -1521,7 +1543,8 @@ BX_CPU_C::BTS_EvIb(bxInstruction_c *i)
BX_CPU_C::BTC_EvIb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("BTC_EvIb: not available on <386"));
BX_INFO(("BTC_EvIb: not available on <386"));
UndefinedOpcode(i);
#else
#if BX_SUPPORT_X86_64
@ -1627,7 +1650,8 @@ BX_CPU_C::BTC_EvIb(bxInstruction_c *i)
BX_CPU_C::BTR_EvIb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("BTR_EvIb: not available on <386"));
BX_INFO(("BTR_EvIb: not available on <386"));
UndefinedOpcode(i);
#else
#if BX_SUPPORT_X86_64

5
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.167 2004-07-29 20:15:17 sshwarts Exp $
// $Id: cpu.h,v 1.168 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -3243,9 +3243,6 @@ IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
#define BX_REPE_PREFIX 10
#define BX_REPNE_PREFIX 11

18
bochs/cpu/data_xfer32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer32.cc,v 1.28 2004-06-18 14:11:06 sshwarts Exp $
// $Id: data_xfer32.cc,v 1.29 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -35,9 +35,8 @@
void
BX_CPU_C::XCHG_ERXEAX(bxInstruction_c *i)
{
Bit32u temp32;
Bit32u temp32 = EAX;
temp32 = EAX;
#if BX_SUPPORT_X86_64
RAX = BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].dword.erx;
BX_CPU_THIS_PTR gen_reg[i->opcodeReg()].dword.erx = temp32;
@ -84,7 +83,6 @@ BX_CPU_C::MOV_GdEEd(bxInstruction_c *i)
// 2nd modRM operand Ex, is known to be a memory operand, Ed.
BX_CLEAR_64BIT_HIGH(i->nnn());
read_virtual_dword(i->seg(), RMAddr(i), &BX_READ_32BIT_REG(i->nnn()));
}
@ -145,7 +143,8 @@ BX_CPU_C::MOV_EdId(bxInstruction_c *i)
BX_CPU_C::MOVZX_GdEb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("MOVZX_GvEb: not supported on < 386"));
BX_INFO(("MOVZX_GvEb: not supported on < 386"));
UndefinedOpcode(i);
#else
Bit8u op2_8;
@ -166,7 +165,8 @@ BX_CPU_C::MOVZX_GdEb(bxInstruction_c *i)
BX_CPU_C::MOVZX_GdEw(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("MOVZX_GvEw: not supported on < 386"));
BX_INFO(("MOVZX_GvEw: not supported on < 386"));
UndefinedOpcode(i);
#else
Bit16u op2_16;
@ -187,7 +187,8 @@ BX_CPU_C::MOVZX_GdEw(bxInstruction_c *i)
BX_CPU_C::MOVSX_GdEb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("MOVSX_GvEb: not supported on < 386"));
BX_INFO(("MOVSX_GvEb: not supported on < 386"));
UndefinedOpcode(i);
#else
Bit8u op2_8;
@ -208,7 +209,8 @@ BX_CPU_C::MOVSX_GdEb(bxInstruction_c *i)
BX_CPU_C::MOVSX_GdEw(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("MOVSX_GvEw: not supported on < 386"));
BX_INFO(("MOVSX_GvEw: not supported on < 386"));
UndefinedOpcode(i);
#else
Bit16u op2_16;

8
bochs/cpu/data_xfer8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer8.cc,v 1.18 2004-02-26 19:17:40 sshwarts Exp $
// $Id: data_xfer8.cc,v 1.19 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,10 +25,6 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
@ -71,7 +67,6 @@ BX_CPU_C::MOV_GbEEb(bxInstruction_c *i)
BX_CPU_C::MOV_GbEGb(bxInstruction_c *i)
{
Bit8u op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op2);
}
@ -93,7 +88,6 @@ BX_CPU_C::MOV_ALOb(bxInstruction_c *i)
void
BX_CPU_C::MOV_ObAL(bxInstruction_c *i)
{
Bit8u temp_8;
bx_address addr = i->Id();
/* write to memory address and write to register */

145
bochs/cpu/lazy_flags.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: lazy_flags.cc,v 1.12 2002-10-25 11:44:35 bdenney Exp $
// $Id: lazy_flags.cc,v 1.13 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -32,13 +32,7 @@
#define LOG_THIS BX_CPU_THIS_PTR
bx_bool
BX_CPU_C::get_CFLazy(void)
bx_bool BX_CPU_C::get_CFLazy(void)
{
unsigned cf;
@ -175,24 +169,12 @@ BX_CPU_C::get_CFLazy(void)
cf = BX_CPU_THIS_PTR oszapc.op1_64 != 0;
break;
#endif
case BX_INSTR_OR8:
case BX_INSTR_OR16:
case BX_INSTR_OR32:
case BX_INSTR_LOGIC8:
case BX_INSTR_LOGIC16:
case BX_INSTR_LOGIC32:
#if BX_SUPPORT_X86_64
case BX_INSTR_OR64:
case BX_INSTR_AND64:
case BX_INSTR_TEST64:
case BX_INSTR_XOR64:
case BX_INSTR_LOGIC64:
#endif
case BX_INSTR_AND8:
case BX_INSTR_AND16:
case BX_INSTR_AND32:
case BX_INSTR_TEST8:
case BX_INSTR_TEST16:
case BX_INSTR_TEST32:
case BX_INSTR_XOR8:
case BX_INSTR_XOR16:
case BX_INSTR_XOR32:
cf = 0;
break;
case BX_INSTR_SHR8:
@ -266,8 +248,7 @@ BX_CPU_C::get_CFLazy(void)
}
bx_bool
BX_CPU_C::get_AFLazy(void)
bx_bool BX_CPU_C::get_AFLazy(void)
{
unsigned af;
@ -342,26 +323,14 @@ BX_CPU_C::get_AFLazy(void)
af = (BX_CPU_THIS_PTR oszapc.op1_64 & 0x0f) > 0;
break;
#endif
case BX_INSTR_OR8:
case BX_INSTR_OR16:
case BX_INSTR_OR32:
case BX_INSTR_LOGIC8:
case BX_INSTR_LOGIC16:
case BX_INSTR_LOGIC32:
#if BX_SUPPORT_X86_64
case BX_INSTR_OR64:
case BX_INSTR_AND64:
case BX_INSTR_TEST64:
case BX_INSTR_XOR64:
case BX_INSTR_LOGIC64:
case BX_INSTR_SHR64:
case BX_INSTR_SHL64:
#endif
case BX_INSTR_AND8:
case BX_INSTR_AND16:
case BX_INSTR_AND32:
case BX_INSTR_TEST8:
case BX_INSTR_TEST16:
case BX_INSTR_TEST32:
case BX_INSTR_XOR8:
case BX_INSTR_XOR16:
case BX_INSTR_XOR32:
case BX_INSTR_SHR8:
case BX_INSTR_SHR16:
case BX_INSTR_SHR32:
@ -428,14 +397,14 @@ BX_CPU_C::get_AFLazy(void)
}
bx_bool
BX_CPU_C::get_ZFLazy(void)
bx_bool BX_CPU_C::get_ZFLazy(void)
{
unsigned zf;
switch ( (BX_CPU_THIS_PTR lf_flags_status>>12) & 0x00000f ) {
case BX_LF_INDEX_OSZAPC:
switch (BX_CPU_THIS_PTR oszapc.instr) {
case BX_INSTR_LOGIC8:
case BX_INSTR_ADD8:
case BX_INSTR_ADC8:
case BX_INSTR_SUB8:
@ -443,16 +412,13 @@ BX_CPU_C::get_ZFLazy(void)
case BX_INSTR_CMP8:
case BX_INSTR_NEG8:
case BX_INSTR_XADD8:
case BX_INSTR_OR8:
case BX_INSTR_AND8:
case BX_INSTR_TEST8:
case BX_INSTR_XOR8:
case BX_INSTR_CMPS8:
case BX_INSTR_SCAS8:
case BX_INSTR_SHR8:
case BX_INSTR_SHL8:
zf = (BX_CPU_THIS_PTR oszapc.result_8 == 0);
break;
case BX_INSTR_LOGIC16:
case BX_INSTR_ADD16:
case BX_INSTR_ADC16:
case BX_INSTR_SUB16:
@ -460,16 +426,13 @@ BX_CPU_C::get_ZFLazy(void)
case BX_INSTR_CMP16:
case BX_INSTR_NEG16:
case BX_INSTR_XADD16:
case BX_INSTR_OR16:
case BX_INSTR_AND16:
case BX_INSTR_TEST16:
case BX_INSTR_XOR16:
case BX_INSTR_CMPS16:
case BX_INSTR_SCAS16:
case BX_INSTR_SHR16:
case BX_INSTR_SHL16:
zf = (BX_CPU_THIS_PTR oszapc.result_16 == 0);
break;
case BX_INSTR_LOGIC32:
case BX_INSTR_ADD32:
case BX_INSTR_ADC32:
case BX_INSTR_SUB32:
@ -477,10 +440,6 @@ BX_CPU_C::get_ZFLazy(void)
case BX_INSTR_CMP32:
case BX_INSTR_NEG32:
case BX_INSTR_XADD32:
case BX_INSTR_OR32:
case BX_INSTR_AND32:
case BX_INSTR_TEST32:
case BX_INSTR_XOR32:
case BX_INSTR_CMPS32:
case BX_INSTR_SCAS32:
case BX_INSTR_SHR32:
@ -488,6 +447,7 @@ BX_CPU_C::get_ZFLazy(void)
zf = (BX_CPU_THIS_PTR oszapc.result_32 == 0);
break;
#if BX_SUPPORT_X86_64
case BX_INSTR_LOGIC64:
case BX_INSTR_ADD64:
case BX_INSTR_ADC64:
case BX_INSTR_SUB64:
@ -495,10 +455,6 @@ BX_CPU_C::get_ZFLazy(void)
case BX_INSTR_CMP64:
case BX_INSTR_NEG64:
case BX_INSTR_XADD64:
case BX_INSTR_OR64:
case BX_INSTR_AND64:
case BX_INSTR_TEST64:
case BX_INSTR_XOR64:
case BX_INSTR_CMPS64:
case BX_INSTR_SCAS64:
case BX_INSTR_SHR64:
@ -551,14 +507,14 @@ BX_CPU_C::get_ZFLazy(void)
}
bx_bool
BX_CPU_C::get_SFLazy(void)
bx_bool BX_CPU_C::get_SFLazy(void)
{
unsigned sf;
switch ( (BX_CPU_THIS_PTR lf_flags_status>>16) & 0x00000f ) {
case BX_LF_INDEX_OSZAPC:
switch (BX_CPU_THIS_PTR oszapc.instr) {
case BX_INSTR_LOGIC8:
case BX_INSTR_ADD8:
case BX_INSTR_ADC8:
case BX_INSTR_SUB8:
@ -566,16 +522,13 @@ BX_CPU_C::get_SFLazy(void)
case BX_INSTR_CMP8:
case BX_INSTR_NEG8:
case BX_INSTR_XADD8:
case BX_INSTR_OR8:
case BX_INSTR_AND8:
case BX_INSTR_TEST8:
case BX_INSTR_XOR8:
case BX_INSTR_CMPS8:
case BX_INSTR_SCAS8:
case BX_INSTR_SHR8:
case BX_INSTR_SHL8:
sf = (BX_CPU_THIS_PTR oszapc.result_8 >= 0x80);
break;
case BX_INSTR_LOGIC16:
case BX_INSTR_ADD16:
case BX_INSTR_ADC16:
case BX_INSTR_SUB16:
@ -583,16 +536,13 @@ BX_CPU_C::get_SFLazy(void)
case BX_INSTR_CMP16:
case BX_INSTR_NEG16:
case BX_INSTR_XADD16:
case BX_INSTR_OR16:
case BX_INSTR_AND16:
case BX_INSTR_TEST16:
case BX_INSTR_XOR16:
case BX_INSTR_CMPS16:
case BX_INSTR_SCAS16:
case BX_INSTR_SHR16:
case BX_INSTR_SHL16:
sf = (BX_CPU_THIS_PTR oszapc.result_16 >= 0x8000);
break;
case BX_INSTR_LOGIC32:
case BX_INSTR_ADD32:
case BX_INSTR_ADC32:
case BX_INSTR_SUB32:
@ -600,10 +550,6 @@ BX_CPU_C::get_SFLazy(void)
case BX_INSTR_CMP32:
case BX_INSTR_NEG32:
case BX_INSTR_XADD32:
case BX_INSTR_OR32:
case BX_INSTR_AND32:
case BX_INSTR_TEST32:
case BX_INSTR_XOR32:
case BX_INSTR_CMPS32:
case BX_INSTR_SCAS32:
case BX_INSTR_SHR32:
@ -611,6 +557,7 @@ BX_CPU_C::get_SFLazy(void)
sf = (BX_CPU_THIS_PTR oszapc.result_32 >= 0x80000000);
break;
#if BX_SUPPORT_X86_64
case BX_INSTR_LOGIC64:
case BX_INSTR_ADD64:
case BX_INSTR_ADC64:
case BX_INSTR_SUB64:
@ -618,10 +565,6 @@ BX_CPU_C::get_SFLazy(void)
case BX_INSTR_CMP64:
case BX_INSTR_NEG64:
case BX_INSTR_XADD64:
case BX_INSTR_OR64:
case BX_INSTR_AND64:
case BX_INSTR_TEST64:
case BX_INSTR_XOR64:
case BX_INSTR_CMPS64:
case BX_INSTR_SCAS64:
case BX_INSTR_SHR64:
@ -673,8 +616,7 @@ BX_CPU_C::get_SFLazy(void)
}
}
bx_bool
BX_CPU_C::get_OFLazy(void)
bx_bool BX_CPU_C::get_OFLazy(void)
{
Bit8u op1_b7, op2_b7, result_b7;
Bit16u op1_b15, op2_b15, result_b15;
@ -785,24 +727,12 @@ BX_CPU_C::get_OFLazy(void)
of = (BX_CPU_THIS_PTR oszapc.op1_64 == BX_CONST64(0x8000000000000000));
break;
#endif
case BX_INSTR_OR8:
case BX_INSTR_OR16:
case BX_INSTR_OR32:
case BX_INSTR_LOGIC8:
case BX_INSTR_LOGIC16:
case BX_INSTR_LOGIC32:
#if BX_SUPPORT_X86_64
case BX_INSTR_OR64:
case BX_INSTR_AND64:
case BX_INSTR_TEST64:
case BX_INSTR_XOR64:
case BX_INSTR_LOGIC64:
#endif
case BX_INSTR_AND8:
case BX_INSTR_AND16:
case BX_INSTR_AND32:
case BX_INSTR_TEST8:
case BX_INSTR_TEST16:
case BX_INSTR_TEST32:
case BX_INSTR_XOR8:
case BX_INSTR_XOR16:
case BX_INSTR_XOR32:
of = 0;
break;
case BX_INSTR_SHR8:
@ -915,14 +845,14 @@ BX_CPU_C::get_OFLazy(void)
}
}
bx_bool
BX_CPU_C::get_PFLazy(void)
bx_bool BX_CPU_C::get_PFLazy(void)
{
unsigned pf;
switch ( (BX_CPU_THIS_PTR lf_flags_status>>4) & 0x00000f ) {
case BX_LF_INDEX_OSZAPC:
switch (BX_CPU_THIS_PTR oszapc.instr) {
case BX_INSTR_LOGIC8:
case BX_INSTR_ADD8:
case BX_INSTR_ADC8:
case BX_INSTR_SUB8:
@ -930,16 +860,13 @@ BX_CPU_C::get_PFLazy(void)
case BX_INSTR_CMP8:
case BX_INSTR_NEG8:
case BX_INSTR_XADD8:
case BX_INSTR_OR8:
case BX_INSTR_AND8:
case BX_INSTR_TEST8:
case BX_INSTR_XOR8:
case BX_INSTR_CMPS8:
case BX_INSTR_SCAS8:
case BX_INSTR_SHR8:
case BX_INSTR_SHL8:
pf = bx_parity_lookup[BX_CPU_THIS_PTR oszapc.result_8];
break;
case BX_INSTR_LOGIC16:
case BX_INSTR_ADD16:
case BX_INSTR_ADC16:
case BX_INSTR_SUB16:
@ -947,16 +874,13 @@ BX_CPU_C::get_PFLazy(void)
case BX_INSTR_CMP16:
case BX_INSTR_NEG16:
case BX_INSTR_XADD16:
case BX_INSTR_OR16:
case BX_INSTR_AND16:
case BX_INSTR_TEST16:
case BX_INSTR_XOR16:
case BX_INSTR_CMPS16:
case BX_INSTR_SCAS16:
case BX_INSTR_SHR16:
case BX_INSTR_SHL16:
pf = bx_parity_lookup[(Bit8u) BX_CPU_THIS_PTR oszapc.result_16];
break;
case BX_INSTR_LOGIC32:
case BX_INSTR_ADD32:
case BX_INSTR_ADC32:
case BX_INSTR_SUB32:
@ -964,10 +888,6 @@ BX_CPU_C::get_PFLazy(void)
case BX_INSTR_CMP32:
case BX_INSTR_NEG32:
case BX_INSTR_XADD32:
case BX_INSTR_OR32:
case BX_INSTR_AND32:
case BX_INSTR_TEST32:
case BX_INSTR_XOR32:
case BX_INSTR_CMPS32:
case BX_INSTR_SCAS32:
case BX_INSTR_SHR32:
@ -975,6 +895,7 @@ BX_CPU_C::get_PFLazy(void)
pf = bx_parity_lookup[(Bit8u) BX_CPU_THIS_PTR oszapc.result_32];
break;
#if BX_SUPPORT_X86_64
case BX_INSTR_LOGIC64:
case BX_INSTR_ADD64:
case BX_INSTR_ADC64:
case BX_INSTR_SUB64:
@ -982,10 +903,6 @@ BX_CPU_C::get_PFLazy(void)
case BX_INSTR_CMP64:
case BX_INSTR_NEG64:
case BX_INSTR_XADD64:
case BX_INSTR_OR64:
case BX_INSTR_AND64:
case BX_INSTR_TEST64:
case BX_INSTR_XOR64:
case BX_INSTR_CMPS64:
case BX_INSTR_SCAS64:
case BX_INSTR_SHR64:

159
bochs/cpu/lazy_flags.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: lazy_flags.h,v 1.6 2002-10-25 11:44:35 bdenney Exp $
// $Id: lazy_flags.h,v 1.7 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,97 +25,108 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#if BX_PROVIDE_CPU_MEMORY==1
#define BX_INSTR_ADD8 1
#define BX_INSTR_ADD16 2
#define BX_INSTR_ADD32 3
#define BX_INSTR_ADD8 1
#define BX_INSTR_ADD16 2
#define BX_INSTR_ADD32 3
#define BX_INSTR_SUB8 4
#define BX_INSTR_SUB16 5
#define BX_INSTR_SUB32 6
#define BX_INSTR_SUB8 4
#define BX_INSTR_SUB16 5
#define BX_INSTR_SUB32 6
#define BX_INSTR_ADC8 7
#define BX_INSTR_ADC16 8
#define BX_INSTR_ADC32 9
#define BX_INSTR_ADC8 7
#define BX_INSTR_ADC16 8
#define BX_INSTR_ADC32 9
#define BX_INSTR_SBB8 10
#define BX_INSTR_SBB16 11
#define BX_INSTR_SBB32 12
#define BX_INSTR_SBB8 10
#define BX_INSTR_SBB16 11
#define BX_INSTR_SBB32 12
#define BX_INSTR_CMP8 13
#define BX_INSTR_CMP16 14
#define BX_INSTR_CMP32 15
#define BX_INSTR_CMP8 13
#define BX_INSTR_CMP16 14
#define BX_INSTR_CMP32 15
#define BX_INSTR_INC8 16
#define BX_INSTR_INC16 17
#define BX_INSTR_INC32 18
#define BX_INSTR_INC8 16
#define BX_INSTR_INC16 17
#define BX_INSTR_INC32 18
#define BX_INSTR_DEC8 19
#define BX_INSTR_DEC16 20
#define BX_INSTR_DEC32 21
#define BX_INSTR_DEC8 19
#define BX_INSTR_DEC16 20
#define BX_INSTR_DEC32 21
#define BX_INSTR_NEG8 22
#define BX_INSTR_NEG16 23
#define BX_INSTR_NEG32 24
#define BX_INSTR_NEG8 22
#define BX_INSTR_NEG16 23
#define BX_INSTR_NEG32 24
#define BX_INSTR_XADD8 25
#define BX_INSTR_XADD16 26
#define BX_INSTR_XADD32 27
#define BX_INSTR_XADD8 25
#define BX_INSTR_XADD16 26
#define BX_INSTR_XADD32 27
#define BX_INSTR_OR8 28
#define BX_INSTR_OR16 29
#define BX_INSTR_OR32 30
#define BX_INSTR_CMPS8 28
#define BX_INSTR_CMPS16 29
#define BX_INSTR_CMPS32 30
#define BX_INSTR_AND8 31
#define BX_INSTR_AND16 32
#define BX_INSTR_AND32 33
#define BX_INSTR_SCAS8 31
#define BX_INSTR_SCAS16 32
#define BX_INSTR_SCAS32 33
#define BX_INSTR_TEST8 34
#define BX_INSTR_TEST16 35
#define BX_INSTR_TEST32 36
#define BX_INSTR_SHR8 34
#define BX_INSTR_SHR16 35
#define BX_INSTR_SHR32 36
#define BX_INSTR_XOR8 37
#define BX_INSTR_XOR16 38
#define BX_INSTR_XOR32 39
#define BX_INSTR_SHL8 37
#define BX_INSTR_SHL16 38
#define BX_INSTR_SHL32 39
#define BX_INSTR_CMPS8 40
#define BX_INSTR_CMPS16 41
#define BX_INSTR_CMPS32 42
#define BX_INSTR_SCAS8 43
#define BX_INSTR_SCAS16 44
#define BX_INSTR_SCAS32 45
#define BX_INSTR_SHR8 46
#define BX_INSTR_SHR16 47
#define BX_INSTR_SHR32 48
#define BX_INSTR_SHL8 49
#define BX_INSTR_SHL16 50
#define BX_INSTR_SHL32 51
#define BX_INSTR_BSF 40
#define BX_INSTR_BSR 41
#define BX_INSTR_LOGIC8 42
#define BX_INSTR_LOGIC16 43
#define BX_INSTR_LOGIC32 44
#if BX_SUPPORT_X86_64
#define BX_INSTR_ADD64 52
#define BX_INSTR_SUB64 53
#define BX_INSTR_ADC64 54
#define BX_INSTR_SBB64 55
#define BX_INSTR_CMP64 56
#define BX_INSTR_INC64 57
#define BX_INSTR_DEC64 58
#define BX_INSTR_NEG64 59
#define BX_INSTR_XADD64 60
#define BX_INSTR_OR64 61
#define BX_INSTR_AND64 62
#define BX_INSTR_TEST64 63
#define BX_INSTR_XOR64 64
#define BX_INSTR_CMPS64 65
#define BX_INSTR_SCAS64 66
#define BX_INSTR_SHR64 67
#define BX_INSTR_SHL64 68
#define BX_INSTR_LOGIC64 45
#endif
#if BX_SUPPORT_X86_64
#define BX_INSTR_ADD64 46
#define BX_INSTR_SUB64 47
#define BX_INSTR_ADC64 48
#define BX_INSTR_SBB64 49
#define BX_INSTR_CMP64 50
#define BX_INSTR_INC64 51
#define BX_INSTR_DEC64 52
#define BX_INSTR_NEG64 53
#define BX_INSTR_XADD64 54
#define BX_INSTR_TEST64 55
#define BX_INSTR_CMPS64 56
#define BX_INSTR_SCAS64 57
#define BX_INSTR_SHR64 58
#define BX_INSTR_SHL64 59
#endif
#define BX_INSTR_TEST8 BX_INSTR_LOGIC8
#define BX_INSTR_OR8 BX_INSTR_LOGIC8
#define BX_INSTR_AND8 BX_INSTR_LOGIC8
#define BX_INSTR_XOR8 BX_INSTR_LOGIC8
#define BX_INSTR_TEST16 BX_INSTR_LOGIC16
#define BX_INSTR_OR16 BX_INSTR_LOGIC16
#define BX_INSTR_AND16 BX_INSTR_LOGIC16
#define BX_INSTR_XOR16 BX_INSTR_LOGIC16
#define BX_INSTR_TEST32 BX_INSTR_LOGIC32
#define BX_INSTR_OR32 BX_INSTR_LOGIC32
#define BX_INSTR_AND32 BX_INSTR_LOGIC32
#define BX_INSTR_XOR32 BX_INSTR_LOGIC32
#if BX_SUPPORT_X86_64
#define BX_INSTR_TEST32 BX_INSTR_LOGIC64
#define BX_INSTR_OR64 BX_INSTR_LOGIC64
#define BX_INSTR_AND64 BX_INSTR_LOGIC64
#define BX_INSTR_XOR64 BX_INSTR_LOGIC64
#endif
#define BX_LF_INDEX_KNOWN 0
#define BX_LF_INDEX_OSZAPC 1
@ -146,7 +157,7 @@ typedef struct {
bx_bool prev_CF;
unsigned instr;
} bx_lf_flags_entry;
} bx_lf_flags_entry;
#endif /* BX_PROVIDE_CPU_MEMORY==1 */

31
bochs/cpu/logical16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: logical16.cc,v 1.19 2004-02-15 17:57:44 cbothamy Exp $
// $Id: logical16.cc,v 1.20 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,17 +25,11 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
void
BX_CPU_C::XOR_EwGw(bxInstruction_c *i)
{
@ -48,7 +42,6 @@ BX_CPU_C::XOR_EwGw(bxInstruction_c *i)
#if defined(BX_HostAsm_Xor16)
Bit32u flags32;
asmXor16(result_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -60,7 +53,6 @@ BX_CPU_C::XOR_EwGw(bxInstruction_c *i)
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
#if defined(BX_HostAsm_Xor16)
Bit32u flags32;
asmXor16(result_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -105,9 +97,7 @@ BX_CPU_C::XOR_AXIw(bxInstruction_c *i)
op1_16 = AX;
op2_16 = i->Iw();
sum_16 = op1_16 ^ op2_16;
AX = sum_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_XOR16);
@ -118,7 +108,6 @@ BX_CPU_C::XOR_EwIw(bxInstruction_c *i)
{
Bit16u op2_16, op1_16, result_16;
op2_16 = i->Iw();
if (i->modC0()) {
@ -141,7 +130,6 @@ BX_CPU_C::OR_EwIw(bxInstruction_c *i)
{
Bit16u op2_16, op1_16, result_16;
op2_16 = i->Iw();
if (i->modC0()) {
@ -215,7 +203,6 @@ BX_CPU_C::OR_GwEw(bxInstruction_c *i)
#if defined(BX_HostAsm_Or16)
Bit32u flags32;
asmOr16(result_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -229,7 +216,6 @@ BX_CPU_C::OR_GwEw(bxInstruction_c *i)
#endif
}
void
BX_CPU_C::OR_AXIw(bxInstruction_c *i)
{
@ -237,16 +223,12 @@ BX_CPU_C::OR_AXIw(bxInstruction_c *i)
op1_16 = AX;
op2_16 = i->Iw();
sum_16 = op1_16 | op2_16;
AX = sum_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_OR16);
}
void
BX_CPU_C::AND_EwGw(bxInstruction_c *i)
{
@ -259,7 +241,6 @@ BX_CPU_C::AND_EwGw(bxInstruction_c *i)
#if defined(BX_HostAsm_And16)
Bit32u flags32;
asmAnd16(result_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -273,7 +254,6 @@ BX_CPU_C::AND_EwGw(bxInstruction_c *i)
#if defined(BX_HostAsm_And16)
Bit32u flags32;
asmAnd16(result_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -305,7 +285,6 @@ BX_CPU_C::AND_GwEw(bxInstruction_c *i)
#if defined(BX_HostAsm_And16)
Bit32u flags32;
asmAnd16(result_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -330,7 +309,6 @@ BX_CPU_C::AND_AXIw(bxInstruction_c *i)
#if defined(BX_HostAsm_And16)
Bit32u flags32;
asmAnd16(result_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -356,7 +334,6 @@ BX_CPU_C::AND_EwIw(bxInstruction_c *i)
#if defined(BX_HostAsm_And16)
Bit32u flags32;
asmAnd16(result_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -370,7 +347,6 @@ BX_CPU_C::AND_EwIw(bxInstruction_c *i)
#if defined(BX_HostAsm_And16)
Bit32u flags32;
asmAnd16(result_16, op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -402,7 +378,6 @@ BX_CPU_C::TEST_EwGw(bxInstruction_c *i)
#if defined(BX_HostAsm_Test16)
Bit32u flags32;
asmTest16(op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -425,13 +400,11 @@ BX_CPU_C::TEST_AXIw(bxInstruction_c *i)
#if defined(BX_HostAsm_Test16)
Bit32u flags32;
asmTest16(op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit16u result_16;
result_16 = op1_16 & op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
#endif
}
@ -453,13 +426,11 @@ BX_CPU_C::TEST_EwIw(bxInstruction_c *i)
#if defined(BX_HostAsm_Test16)
Bit32u flags32;
asmTest16(op1_16, op2_16, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit16u result_16;
result_16 = op1_16 & op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_TEST16);
#endif
}

21
bochs/cpu/logical32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: logical32.cc,v 1.20 2004-02-15 17:57:45 cbothamy Exp $
// $Id: logical32.cc,v 1.21 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,17 +25,11 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
void
BX_CPU_C::XOR_EdGd(bxInstruction_c *i)
{
@ -199,7 +193,6 @@ BX_CPU_C::OR_GdEd(bxInstruction_c *i)
#if defined(BX_HostAsm_Or32)
Bit32u flags32;
asmOr32(result_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -221,7 +214,6 @@ BX_CPU_C::OR_EAXId(bxInstruction_c *i)
op1_32 = EAX;
op2_32 = i->Id();
sum_32 = op1_32 | op2_32;
#if BX_SUPPORT_X86_64
@ -247,7 +239,6 @@ BX_CPU_C::AND_EdGd(bxInstruction_c *i)
#if defined(BX_HostAsm_And32)
Bit32u flags32;
asmAnd32(result_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -255,13 +246,12 @@ BX_CPU_C::AND_EdGd(bxInstruction_c *i)
#endif
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
#if defined(BX_HostAsm_And32)
Bit32u flags32;
asmAnd32(result_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -293,7 +283,6 @@ BX_CPU_C::AND_GdEd(bxInstruction_c *i)
#if defined(BX_HostAsm_And32)
Bit32u flags32;
asmAnd32(result_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -362,7 +351,6 @@ BX_CPU_C::AND_EdId(bxInstruction_c *i)
#if defined(BX_HostAsm_And32)
Bit32u flags32;
asmAnd32(result_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -394,7 +382,6 @@ BX_CPU_C::TEST_EdGd(bxInstruction_c *i)
#if defined(BX_HostAsm_Test32)
Bit32u flags32;
asmTest32(op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -417,13 +404,11 @@ BX_CPU_C::TEST_EAXId(bxInstruction_c *i)
#if defined(BX_HostAsm_Test32)
Bit32u flags32;
asmTest32(op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit32u result_32;
result_32 = op1_32 & op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
#endif
}
@ -445,13 +430,11 @@ BX_CPU_C::TEST_EdId(bxInstruction_c *i)
#if defined(BX_HostAsm_Test32)
Bit32u flags32;
asmTest32(op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit32u result_32;
result_32 = op1_32 & op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
#endif
}

14
bochs/cpu/logical64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: logical64.cc,v 1.8 2004-04-07 19:23:06 sshwarts Exp $
// $Id: logical64.cc,v 1.9 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,18 +25,12 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_X86_64
void
BX_CPU_C::XOR_EqGq(bxInstruction_c *i)
{
@ -100,9 +94,7 @@ BX_CPU_C::XOR_RAXId(bxInstruction_c *i)
Bit64u op1_64, op2_64, sum_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
sum_64 = op1_64 ^ op2_64;
/* now write sum back to destination */
@ -254,9 +246,7 @@ BX_CPU_C::OR_RAXId(bxInstruction_c *i)
Bit64u op1_64, op2_64, sum_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
sum_64 = op1_64 | op2_64;
/* now write sum back to destination */
@ -325,9 +315,7 @@ BX_CPU_C::AND_RAXId(bxInstruction_c *i)
Bit64u op1_64, op2_64, sum_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
sum_64 = op1_64 & op2_64;
/* now write sum back to destination */

19
bochs/cpu/logical8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: logical8.cc,v 1.22 2004-02-15 17:57:45 cbothamy Exp $
// $Id: logical8.cc,v 1.23 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,16 +25,11 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
void
BX_CPU_C::XOR_EbGb(bxInstruction_c *i)
{
@ -85,9 +80,7 @@ BX_CPU_C::XOR_ALIb(bxInstruction_c *i)
op1 = AL;
op2 = i->Ib();
sum = op1 ^ op2;
AL = sum;
SET_FLAGS_OSZAPC_8(op1, op2, sum, BX_INSTR_XOR8);
@ -195,7 +188,6 @@ BX_CPU_C::OR_GbEb(bxInstruction_c *i)
#if defined(BX_HostAsm_Or8)
Bit32u flags32;
asmOr8(result, op1, op2, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -248,7 +240,6 @@ BX_CPU_C::AND_EbGb(bxInstruction_c *i)
#if defined(BX_HostAsm_And8)
Bit32u flags32;
asmAnd8(result, op1, op2, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -262,7 +253,6 @@ BX_CPU_C::AND_EbGb(bxInstruction_c *i)
#if defined(BX_HostAsm_And8)
Bit32u flags32;
asmAnd8(result, op1, op2, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -294,7 +284,6 @@ BX_CPU_C::AND_GbEb(bxInstruction_c *i)
#if defined(BX_HostAsm_And8)
Bit32u flags32;
asmAnd8(result, op1, op2, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -320,7 +309,6 @@ BX_CPU_C::AND_ALIb(bxInstruction_c *i)
#if defined(BX_HostAsm_And8)
Bit32u flags32;
asmAnd8(result, op1, op2, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -342,7 +330,6 @@ BX_CPU_C::AND_EbIb(bxInstruction_c *i)
{
Bit8u op2, op1, result;
op2 = i->Ib();
if (i->modC0()) {
@ -350,7 +337,6 @@ BX_CPU_C::AND_EbIb(bxInstruction_c *i)
#if defined(BX_HostAsm_And8)
Bit32u flags32;
asmAnd8(result, op1, op2, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -364,7 +350,6 @@ BX_CPU_C::AND_EbIb(bxInstruction_c *i)
#if defined(BX_HostAsm_And8)
Bit32u flags32;
asmAnd8(result, op1, op2, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -396,7 +381,6 @@ BX_CPU_C::TEST_EbGb(bxInstruction_c *i)
#if defined(BX_HostAsm_Test8)
Bit32u flags32;
asmTest8(op1, op2, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -447,7 +431,6 @@ BX_CPU_C::TEST_EbIb(bxInstruction_c *i)
#if defined(BX_HostAsm_Test8)
Bit32u flags32;
asmTest8(op1, op2, flags32);
setEFlagsOSZAPC(flags32);
#else

22
bochs/cpu/mult16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: mult16.cc,v 1.10 2002-10-25 11:44:35 bdenney Exp $
// $Id: mult16.cc,v 1.11 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,17 +25,11 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
void
BX_CPU_C::MUL_AXEw(bxInstruction_c *i)
{
@ -73,7 +67,6 @@ BX_CPU_C::MUL_AXEw(bxInstruction_c *i)
}
void
BX_CPU_C::IMUL_AXEw(bxInstruction_c *i)
{
@ -209,11 +202,6 @@ BX_CPU_C::IDIV_AXEw(bxInstruction_c *i)
void
BX_CPU_C::IMUL_GwEwIw(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 2
BX_PANIC(("IMUL_GvEvIv() unsupported on 8086!"));
#else
Bit16u product_16l;
Bit16s op2_16, op3_16;
Bit32s product_32;
@ -230,7 +218,6 @@ BX_CPU_C::IMUL_GwEwIw(bxInstruction_c *i)
}
product_32 = op2_16 * op3_16;
product_16l = (product_32 & 0xFFFF);
/* now write product back to destination */
@ -248,16 +235,11 @@ BX_CPU_C::IMUL_GwEwIw(bxInstruction_c *i)
else {
SET_FLAGS_OxxxxC(1, 1);
}
#endif
}
void
BX_CPU_C::IMUL_GwEw(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("IMUL_GvEv() unsupported on 8086!"));
#else
Bit16u product_16l;
Bit16s op1_16, op2_16;
Bit32s product_32;
@ -274,7 +256,6 @@ BX_CPU_C::IMUL_GwEw(bxInstruction_c *i)
op1_16 = BX_READ_16BIT_REG(i->nnn());
product_32 = op1_16 * op2_16;
product_16l = (product_32 & 0xFFFF);
/* now write product back to destination */
@ -292,5 +273,4 @@ BX_CPU_C::IMUL_GwEw(bxInstruction_c *i)
else {
SET_FLAGS_OxxxxC(1, 1);
}
#endif
}

34
bochs/cpu/mult32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: mult32.cc,v 1.11 2002-10-25 11:44:35 bdenney Exp $
// $Id: mult32.cc,v 1.12 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,10 +25,6 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
@ -78,7 +74,6 @@ BX_CPU_C::MUL_EAXEd(bxInstruction_c *i)
}
void
BX_CPU_C::IMUL_EAXEd(bxInstruction_c *i)
{
@ -144,14 +139,16 @@ BX_CPU_C::DIV_EAXEd(bxInstruction_c *i)
if (op2_32 == 0) {
exception(BX_DE_EXCEPTION, 0, 0);
}
}
quotient_64 = op1_64 / op2_32;
remainder_32 = (Bit32u) (op1_64 % op2_32);
quotient_32l = (Bit32u) (quotient_64 & 0xFFFFFFFF);
if (quotient_64 != quotient_32l) {
if (quotient_64 != quotient_32l)
{
exception(BX_DE_EXCEPTION, 0, 0);
}
}
/* set EFLAGS:
* DIV affects the following flags: O,S,Z,A,P,C are undefined
@ -183,14 +180,16 @@ BX_CPU_C::IDIV_EAXEd(bxInstruction_c *i)
if (op2_32 == 0) {
exception(BX_DE_EXCEPTION, 0, 0);
}
}
quotient_64 = op1_64 / op2_32;
remainder_32 = (Bit32s) (op1_64 % op2_32);
quotient_32l = (Bit32s) (quotient_64 & 0xFFFFFFFF);
if (quotient_64 != quotient_32l) {
if (quotient_64 != quotient_32l)
{
exception(BX_DE_EXCEPTION, 0, 0);
}
}
/* set EFLAGS:
* IDIV affects the following flags: O,S,Z,A,P,C are undefined
@ -206,11 +205,6 @@ BX_CPU_C::IDIV_EAXEd(bxInstruction_c *i)
void
BX_CPU_C::IMUL_GdEdId(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 2
BX_PANIC(("IMUL_GdEdId() unsupported on 8086!"));
#else
Bit32s op2_32, op3_32, product_32;
Bit64s product_64;
@ -243,17 +237,12 @@ BX_CPU_C::IMUL_GdEdId(bxInstruction_c *i)
else {
SET_FLAGS_OxxxxC(1, 1);
}
#endif
}
void
BX_CPU_C::IMUL_GdEd(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("IMUL_GvEv() unsupported on 8086!"));
#else
Bit32s op1_32, op2_32, product_32;
Bit64s product_64;
@ -286,5 +275,4 @@ BX_CPU_C::IMUL_GdEd(bxInstruction_c *i)
else {
SET_FLAGS_OxxxxC(1, 1);
}
#endif
}

21
bochs/cpu/mult8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: mult8.cc,v 1.11 2002-10-25 11:44:35 bdenney Exp $
// $Id: mult8.cc,v 1.12 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,10 +25,6 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
@ -63,7 +59,6 @@ BX_CPU_C::MUL_ALEb(bxInstruction_c *i)
SET_FLAGS_OxxxxC(temp_flag, temp_flag);
/* now write product back to destination */
AX = product_16;
}
@ -75,7 +70,6 @@ BX_CPU_C::IMUL_ALEb(bxInstruction_c *i)
Bit16s product_16;
Bit16u upper_bits;
op1 = AL;
/* op2 is a register or memory reference */
@ -90,7 +84,6 @@ BX_CPU_C::IMUL_ALEb(bxInstruction_c *i)
product_16 = op1 * op2;
/* now write product back to destination */
AX = product_16;
/* set EFLAGS:
@ -108,14 +101,12 @@ BX_CPU_C::IMUL_ALEb(bxInstruction_c *i)
}
void
BX_CPU_C::DIV_ALEb(bxInstruction_c *i)
{
Bit8u op2, quotient_8l, remainder_8;
Bit16u quotient_16, op1;
op1 = AX;
/* op2 is a register or memory reference */
@ -129,14 +120,16 @@ BX_CPU_C::DIV_ALEb(bxInstruction_c *i)
if (op2 == 0) {
exception(BX_DE_EXCEPTION, 0, 0);
}
}
quotient_16 = op1 / op2;
remainder_8 = op1 % op2;
quotient_8l = quotient_16 & 0xFF;
if (quotient_16 != quotient_8l) {
if (quotient_16 != quotient_8l)
{
exception(BX_DE_EXCEPTION, 0, 0);
}
}
/* set EFLAGS:
* DIV affects the following flags: O,S,Z,A,P,C are undefined
@ -159,10 +152,8 @@ BX_CPU_C::IDIV_ALEb(bxInstruction_c *i)
Bit8s op2, quotient_8l, remainder_8;
Bit16s quotient_16, op1;
op1 = AX;
/* op2 is a register or memory reference */
if (i->modC0()) {
op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());

33
bochs/cpu/shift16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: shift16.cc,v 1.18 2004-02-15 17:57:45 cbothamy Exp $
// $Id: shift16.cc,v 1.19 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,16 +25,11 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
void
BX_CPU_C::SHLD_EwGw(bxInstruction_c *i)
{
@ -50,7 +45,6 @@ BX_CPU_C::SHLD_EwGw(bxInstruction_c *i)
count &= 0x1f; // use only 5 LSB's
if (!count) return; /* NOP */
// count is 1..31
@ -97,7 +91,8 @@ BX_CPU_C::SHLD_EwGw(bxInstruction_c *i)
BX_CPU_C::SHRD_EwGw(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("shrd_evgvib: not supported on < 386"));
BX_INFO(("SHRD_EwGw: not supported on < 386"));
UndefinedOpcode(i)
#else
Bit16u op1_16, op2_16, result_16;
Bit32u temp_32, result_32;
@ -155,12 +150,10 @@ BX_CPU_C::SHRD_EwGw(bxInstruction_c *i)
}
void
BX_CPU_C::ROL_Ew(bxInstruction_c *i)
{
Bit16u op1_16, result_16;
Bit16u op1_16, result_16;
unsigned count;
if ( i->b1() == 0xc1 )
@ -202,13 +195,10 @@ BX_CPU_C::ROL_Ew(bxInstruction_c *i)
}
}
void
BX_CPU_C::ROR_Ew(bxInstruction_c *i)
{
Bit16u op1_16, result_16, result_b15;
Bit16u op1_16, result_16, result_b15;
unsigned count;
if ( i->b1() == 0xc1 )
@ -251,8 +241,6 @@ BX_CPU_C::ROR_Ew(bxInstruction_c *i)
}
}
void
BX_CPU_C::RCL_Ew(bxInstruction_c *i)
{
@ -312,7 +300,6 @@ BX_CPU_C::RCL_Ew(bxInstruction_c *i)
}
void
BX_CPU_C::RCR_Ew(bxInstruction_c *i)
{
@ -362,8 +349,6 @@ BX_CPU_C::RCR_Ew(bxInstruction_c *i)
}
void
BX_CPU_C::SHL_Ew(bxInstruction_c *i)
{
@ -403,9 +388,6 @@ BX_CPU_C::SHL_Ew(bxInstruction_c *i)
SET_FLAGS_OSZAPC_16(op1_16, count, result_16, BX_INSTR_SHL16);
}
void
BX_CPU_C::SHR_Ew(bxInstruction_c *i)
{
@ -434,14 +416,12 @@ BX_CPU_C::SHR_Ew(bxInstruction_c *i)
#if defined(BX_HostAsm_Shr16)
Bit32u flags32;
asmShr16(result_16, op1_16, count, flags32);
setEFlagsOSZAPC(flags32);
#else
result_16 = (op1_16 >> count);
#endif
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), result_16);
@ -456,7 +436,6 @@ BX_CPU_C::SHR_Ew(bxInstruction_c *i)
}
void
BX_CPU_C::SAR_Ew(bxInstruction_c *i)
{
@ -500,8 +479,6 @@ BX_CPU_C::SAR_Ew(bxInstruction_c *i)
}
}
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), result_16);

31
bochs/cpu/shift32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: shift32.cc,v 1.19 2004-02-15 17:57:45 cbothamy Exp $
// $Id: shift32.cc,v 1.20 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,10 +25,6 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
@ -85,7 +81,8 @@ BX_CPU_C::SHLD_EdGd(bxInstruction_c *i)
BX_CPU_C::SHRD_EdGd(bxInstruction_c *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("shrd_evgvib: not supported on < 386"));
BX_PANIC(("SHRD_EdGd: not supported on < 386"));
UndefinedOpcode(i)
#else
Bit32u op1_32, op2_32, result_32;
unsigned count;
@ -97,7 +94,6 @@ BX_CPU_C::SHRD_EdGd(bxInstruction_c *i)
if (!count) return; /* NOP */
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
@ -133,11 +129,9 @@ BX_CPU_C::SHRD_EdGd(bxInstruction_c *i)
}
void
BX_CPU_C::ROL_Ed(bxInstruction_c *i)
{
Bit32u op1_32, result_32;
unsigned count;
@ -178,13 +172,10 @@ BX_CPU_C::ROL_Ed(bxInstruction_c *i)
}
}
void
BX_CPU_C::ROR_Ed(bxInstruction_c *i)
{
Bit32u op1_32, result_32, result_b31;
Bit32u op1_32, result_32, result_b31;
unsigned count;
if (i->b1() == 0xc1)
@ -225,8 +216,6 @@ BX_CPU_C::ROR_Ed(bxInstruction_c *i)
}
}
void
BX_CPU_C::RCL_Ed(bxInstruction_c *i)
{
@ -240,7 +229,6 @@ BX_CPU_C::RCL_Ed(bxInstruction_c *i)
else // (i->b1() == 0xd3)
count = CL & 0x1f;
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
@ -278,7 +266,6 @@ BX_CPU_C::RCL_Ed(bxInstruction_c *i)
}
void
BX_CPU_C::RCR_Ed(bxInstruction_c *i)
{
@ -292,7 +279,6 @@ BX_CPU_C::RCR_Ed(bxInstruction_c *i)
else // (i->b1() == 0xd3)
count = CL & 0x1f;
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
@ -330,9 +316,6 @@ BX_CPU_C::RCR_Ed(bxInstruction_c *i)
set_OF(((op1_32 ^ result_32) & 0x80000000) > 0);
}
void
BX_CPU_C::SHL_Ed(bxInstruction_c *i)
{
@ -370,9 +353,6 @@ BX_CPU_C::SHL_Ed(bxInstruction_c *i)
SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHL32);
}
void
BX_CPU_C::SHR_Ed(bxInstruction_c *i)
{
@ -399,7 +379,6 @@ BX_CPU_C::SHR_Ed(bxInstruction_c *i)
#if defined(BX_HostAsm_Shr32)
Bit32u flags32;
asmShr32(result_32, op1_32, count, flags32);
setEFlagsOSZAPC(flags32);
#else
@ -419,8 +398,6 @@ BX_CPU_C::SHR_Ed(bxInstruction_c *i)
#endif
}
void
BX_CPU_C::SAR_Ed(bxInstruction_c *i)
{

9
bochs/cpu/shift64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: shift64.cc,v 1.11 2004-04-07 19:23:06 sshwarts Exp $
// $Id: shift64.cc,v 1.12 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,14 +25,11 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_X86_64
void
@ -41,7 +38,7 @@ BX_CPU_C::SHLD_EqGq(bxInstruction_c *i)
Bit64u op1_64, op2_64, result_64;
unsigned count;
/* op1:op2 << count. result stored in op1 */
/* op1:op2 << count. result stored in op1 */
if (i->b1() == 0x1a4)
count = i->Ib() & 0x3f;

20
bochs/cpu/shift8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: shift8.cc,v 1.14 2002-10-25 18:26:29 sshwarts Exp $
// $Id: shift8.cc,v 1.15 2004-08-09 21:28:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -25,18 +25,11 @@
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
void
BX_CPU_C::ROL_Eb(bxInstruction_c *i)
{
@ -83,8 +76,6 @@ BX_CPU_C::ROL_Eb(bxInstruction_c *i)
}
void
BX_CPU_C::ROR_Eb(bxInstruction_c *i)
{
@ -134,7 +125,6 @@ BX_CPU_C::ROR_Eb(bxInstruction_c *i)
}
void
BX_CPU_C::RCL_Eb(bxInstruction_c *i)
{
@ -150,7 +140,6 @@ BX_CPU_C::RCL_Eb(bxInstruction_c *i)
count = (count & 0x1F) % 9;
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
@ -183,7 +172,6 @@ BX_CPU_C::RCL_Eb(bxInstruction_c *i)
}
void
BX_CPU_C::RCR_Eb(bxInstruction_c *i)
{
@ -232,8 +220,6 @@ BX_CPU_C::RCR_Eb(bxInstruction_c *i)
}
void
BX_CPU_C::SHL_Eb(bxInstruction_c *i)
{
@ -274,7 +260,6 @@ BX_CPU_C::SHL_Eb(bxInstruction_c *i)
}
void
BX_CPU_C::SHR_Eb(bxInstruction_c *i)
{
@ -314,9 +299,6 @@ BX_CPU_C::SHR_Eb(bxInstruction_c *i)
SET_FLAGS_OSZAPC_8(op1_8, count, result_8, BX_INSTR_SHR8);
}
void
BX_CPU_C::SAR_Eb(bxInstruction_c *i)
{