mirror of https://github.com/bochs-emu/Bochs
make sreg index tables static in fetchdecode and remove them from init.cc/cpu.h
This commit is contained in:
Stanislav Shwartsman
parent
1e0db62984
commit
30f42d74f1
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.367 2007-11-18 19:46:14 sshwarts Exp $
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// $Id: cpu.h,v 1.368 2007-11-18 21:07:40 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1199,21 +1199,6 @@ public: // for now...
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volatile bx_bool smi_pending;
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volatile bx_bool nmi_pending;
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// <TAG-CLASS-CPU-START>
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// for decoding instructions; accessing seg reg's by index
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unsigned sreg_mod00_rm16[8];
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unsigned sreg_mod01or10_rm16[8];
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#if BX_SUPPORT_X86_64
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unsigned sreg_mod01or10_rm32[16];
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unsigned sreg_mod0_base32[16];
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unsigned sreg_mod1or2_base32[16];
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#else
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unsigned sreg_mod01or10_rm32[8];
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unsigned sreg_mod0_base32[8];
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unsigned sreg_mod1or2_base32[8];
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#endif
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// <TAG-CLASS-CPU-END>
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// for exceptions
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jmp_buf jmp_buf_env;
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Bit8u curr_exception[2];
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.132 2007-11-18 19:46:14 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.133 2007-11-18 21:07:40 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -78,10 +78,6 @@ static const bx_bool BxOpcodeHasModrm32[512] = {
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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};
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// UD2 opcode (according to Intel manuals):
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// Use the 0F0B opcode (UD2 instruction) or the 0FB9H opcode when deliberately
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// trying to generate an invalid opcode exception (#UD).
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/* *********** */
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// LOCK PREFIX //
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/* *********** */
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@ -154,6 +150,63 @@ static BxExecutePtr_tR Resolve32BaseIndex[8] = {
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&BX_CPU_C::BxResolve32BaseIndex,
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};
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// decoding instructions; accessing seg reg's by index
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static unsigned sreg_mod00_rm16[8] = {
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_SS,
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BX_SEG_REG_SS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS
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};
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static unsigned sreg_mod01or10_rm16[8] = {
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_SS,
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BX_SEG_REG_SS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_SS,
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BX_SEG_REG_DS
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};
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// decoding instructions; accessing seg reg's by index
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static unsigned sreg_mod01or10_rm32[8] = {
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_NULL, // escape to SIB-byte
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BX_SEG_REG_SS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS
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};
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static unsigned sreg_mod0_base32[8] = {
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_SS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS
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};
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static unsigned sreg_mod1or2_base32[8] = {
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_SS,
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BX_SEG_REG_SS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS
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};
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// common fetchdecode32/64 opcode tables
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#include "fetchdecode.h"
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@ -2614,7 +2667,7 @@ fetch_b1:
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if (mod == 0x40) { // mod == 01b
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instruction->ResolveModrm = BxResolve32Rm;
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01or10_rm32[rm]);
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instruction->setSeg(sreg_mod01or10_rm32[rm]);
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get_8bit_displ:
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if (ilen < remain) {
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// 8 sign extended to 32
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@ -2627,7 +2680,7 @@ get_8bit_displ:
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// (mod == 0x80) mod == 10b
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instruction->ResolveModrm = BxResolve32Rm;
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01or10_rm32[rm]);
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instruction->setSeg(sreg_mod01or10_rm32[rm]);
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get_32bit_displ:
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if ((ilen+3) < remain) {
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instruction->modRMForm.displ32u = FetchDWORD(iptr);
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@ -2658,7 +2711,7 @@ get_32bit_displ:
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else
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instruction->ResolveModrm = Resolve32BaseIndex[base];
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod0_base32[base]);
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instruction->setSeg(sreg_mod0_base32[base]);
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if (base == 0x05)
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goto get_32bit_displ;
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// mod==00b, rm==4, base!=5
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@ -2670,7 +2723,7 @@ get_32bit_displ:
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else
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instruction->ResolveModrm = BxResolve32BaseIndex;
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
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instruction->setSeg(sreg_mod1or2_base32[base]);
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goto get_8bit_displ;
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}
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// (mod == 0x80), mod==10b, rm==4
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@ -2679,7 +2732,7 @@ get_32bit_displ:
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else
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instruction->ResolveModrm = BxResolve32BaseIndex;
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
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instruction->setSeg(sreg_mod1or2_base32[base]);
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goto get_32bit_displ;
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}
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}
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@ -2688,7 +2741,7 @@ get_32bit_displ:
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if (mod == 0x40) { // mod == 01b
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instruction->ResolveModrm = Resolve16Mod1or2[rm];
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01or10_rm16[rm]);
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instruction->setSeg(sreg_mod01or10_rm16[rm]);
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if (ilen < remain) {
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// 8 sign extended to 16
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instruction->modRMForm.displ16u = (Bit8s) *iptr++;
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@ -2700,7 +2753,7 @@ get_32bit_displ:
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if (mod == 0x80) { // mod == 10b
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instruction->ResolveModrm = Resolve16Mod1or2[rm];
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01or10_rm16[rm]);
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instruction->setSeg(sreg_mod01or10_rm16[rm]);
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if ((ilen+1) < remain) {
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instruction->modRMForm.displ16u = FetchWORD(iptr);
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iptr += 2;
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@ -2712,7 +2765,7 @@ get_32bit_displ:
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// mod must be 00b at this point
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instruction->ResolveModrm = Resolve16Mod0[rm];
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod00_rm16[rm]);
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instruction->setSeg(sreg_mod00_rm16[rm]);
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if (rm == 0x06) {
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if ((ilen+1) < remain) {
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instruction->modRMForm.displ16u = FetchWORD(iptr);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode64.cc,v 1.140 2007-11-18 20:21:34 sshwarts Exp $
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// $Id: fetchdecode64.cc,v 1.141 2007-11-18 21:07:40 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -84,10 +84,6 @@ static const bx_bool BxOpcodeHasModrm64[512] = {
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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};
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// UD2 opcode (according to Intel manuals):
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// Use the 0F0B opcode (UD2 instruction) or the 0FB9H opcode when deliberately
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// trying to generate an invalid opcode exception (#UD).
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/* *********** */
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// LOCK PREFIX //
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/* *********** */
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@ -200,6 +196,63 @@ static BxExecutePtr_tR Resolve64BaseIndex[16] = {
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&BX_CPU_C::BxResolve64BaseIndex,
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};
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// decoding instructions; accessing seg reg's by index
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static unsigned sreg_mod01or10_rm32[16] = {
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_NULL, // escape to SIB-byte
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BX_SEG_REG_SS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_NULL, // escape to SIB-byte
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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};
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static unsigned sreg_mod0_base32[16] = {
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_SS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS
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};
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static unsigned sreg_mod1or2_base32[16] = {
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_SS,
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BX_SEG_REG_SS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS,
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BX_SEG_REG_DS
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};
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// common fetchdecode32/64 opcode tables
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#include "fetchdecode.h"
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@ -3596,7 +3649,7 @@ fetch_b1:
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if (mod == 0x40) { // mod == 01b
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instruction->ResolveModrm = BxResolve64Rm;
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01or10_rm32[rm]);
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instruction->setSeg(sreg_mod01or10_rm32[rm]);
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if (ilen < remain) {
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// 8 sign extended to 32
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instruction->modRMForm.displ32u = (Bit8s) *iptr++;
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@ -3608,7 +3661,7 @@ fetch_b1:
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// (mod == 0x80) mod == 10b
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instruction->ResolveModrm = BxResolve64Rm;
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01or10_rm32[rm]);
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instruction->setSeg(sreg_mod01or10_rm32[rm]);
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if ((ilen+3) < remain) {
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instruction->modRMForm.displ32u = FetchDWORD(iptr);
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iptr += 4;
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@ -3638,7 +3691,7 @@ fetch_b1:
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else
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instruction->ResolveModrm = Resolve64BaseIndex[base];
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod0_base32[base]);
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instruction->setSeg(sreg_mod0_base32[base]);
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if ((base & 0x7) == 5)
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goto get_32bit_displ;
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// mod==00b, rm==4, base!=5
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@ -3650,7 +3703,7 @@ fetch_b1:
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else
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instruction->ResolveModrm = BxResolve64BaseIndex;
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
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instruction->setSeg(sreg_mod1or2_base32[base]);
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goto get_8bit_displ;
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}
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// (mod == 0x80), mod==10b, rm==4
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@ -3659,7 +3712,7 @@ fetch_b1:
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else
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instruction->ResolveModrm = BxResolve64BaseIndex;
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
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instruction->setSeg(sreg_mod1or2_base32[base]);
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goto get_32bit_displ;
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}
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}
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@ -3685,7 +3738,7 @@ fetch_b1:
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if (mod == 0x40) { // mod == 01b
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instruction->ResolveModrm = BxResolve32Rm;
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01or10_rm32[rm]);
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instruction->setSeg(sreg_mod01or10_rm32[rm]);
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get_8bit_displ:
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if (ilen < remain) {
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// 8 sign extended to 32
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@ -3698,7 +3751,7 @@ get_8bit_displ:
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// (mod == 0x80) mod == 10b
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instruction->ResolveModrm = BxResolve32Rm;
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01or10_rm32[rm]);
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instruction->setSeg(sreg_mod01or10_rm32[rm]);
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get_32bit_displ:
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if ((ilen+3) < remain) {
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instruction->modRMForm.displ32u = FetchDWORD(iptr);
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@ -3729,7 +3782,7 @@ get_32bit_displ:
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else
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instruction->ResolveModrm = Resolve32BaseIndex[base];
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod0_base32[base]);
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instruction->setSeg(sreg_mod0_base32[base]);
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if ((base & 0x7) == 5)
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goto get_32bit_displ;
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// mod==00b, rm==4, base!=5
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@ -3741,7 +3794,7 @@ get_32bit_displ:
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else
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instruction->ResolveModrm = BxResolve32BaseIndex;
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
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instruction->setSeg(sreg_mod1or2_base32[base]);
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goto get_8bit_displ;
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}
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// (mod == 0x80), mod==10b, rm==4
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@ -3750,7 +3803,7 @@ get_32bit_displ:
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else
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instruction->ResolveModrm = BxResolve32BaseIndex;
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
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instruction->setSeg(sreg_mod1or2_base32[base]);
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goto get_32bit_displ;
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}
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: init.cc,v 1.143 2007-11-11 20:44:07 sshwarts Exp $
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// $Id: init.cc,v 1.144 2007-11-18 21:07:40 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -163,95 +163,9 @@ void BX_CPU_C::initialize(BX_MEM_C *addrspace)
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// in SMP mode, the prefix of the CPU will be changed to [CPUn] in
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// bx_local_apic_c::set_id as soon as the apic ID is assigned.
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// <TAG-INIT-CPU-START>
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// for decoding instructions: access to seg reg's via index number
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sreg_mod00_rm16[0] = BX_SEG_REG_DS;
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sreg_mod00_rm16[1] = BX_SEG_REG_DS;
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sreg_mod00_rm16[2] = BX_SEG_REG_SS;
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sreg_mod00_rm16[3] = BX_SEG_REG_SS;
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sreg_mod00_rm16[4] = BX_SEG_REG_DS;
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sreg_mod00_rm16[5] = BX_SEG_REG_DS;
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sreg_mod00_rm16[6] = BX_SEG_REG_DS;
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sreg_mod00_rm16[7] = BX_SEG_REG_DS;
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|
||||
sreg_mod01or10_rm16[0] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm16[1] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm16[2] = BX_SEG_REG_SS;
|
||||
sreg_mod01or10_rm16[3] = BX_SEG_REG_SS;
|
||||
sreg_mod01or10_rm16[4] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm16[5] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm16[6] = BX_SEG_REG_SS;
|
||||
sreg_mod01or10_rm16[7] = BX_SEG_REG_DS;
|
||||
|
||||
// the default segment to use for a one-byte modrm with
|
||||
// mod==01b or mod==10b and rm == i
|
||||
sreg_mod01or10_rm32[0] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm32[1] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm32[2] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm32[3] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm32[4] = BX_SEG_REG_NULL;
|
||||
// this entry should never be accessed
|
||||
// (escape to 2-byte)
|
||||
sreg_mod01or10_rm32[5] = BX_SEG_REG_SS;
|
||||
sreg_mod01or10_rm32[6] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm32[7] = BX_SEG_REG_DS;
|
||||
#if BX_SUPPORT_X86_64
|
||||
sreg_mod01or10_rm32[8] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm32[9] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm32[10] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm32[11] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm32[12] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm32[13] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm32[14] = BX_SEG_REG_DS;
|
||||
sreg_mod01or10_rm32[15] = BX_SEG_REG_DS;
|
||||
#endif
|
||||
|
||||
// the default segment to use for a two-byte modrm with
|
||||
// mod==00b and base == i
|
||||
sreg_mod0_base32[0] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[1] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[2] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[3] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[4] = BX_SEG_REG_SS;
|
||||
sreg_mod0_base32[5] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[6] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[7] = BX_SEG_REG_DS;
|
||||
#if BX_SUPPORT_X86_64
|
||||
sreg_mod0_base32[8] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[9] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[10] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[11] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[12] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[13] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[14] = BX_SEG_REG_DS;
|
||||
sreg_mod0_base32[15] = BX_SEG_REG_DS;
|
||||
#endif
|
||||
|
||||
// the default segment to use for a two-byte modrm with
|
||||
// mod==01b or mod==10b and base == i
|
||||
sreg_mod1or2_base32[0] = BX_SEG_REG_DS;
|
||||
sreg_mod1or2_base32[1] = BX_SEG_REG_DS;
|
||||
sreg_mod1or2_base32[2] = BX_SEG_REG_DS;
|
||||
sreg_mod1or2_base32[3] = BX_SEG_REG_DS;
|
||||
sreg_mod1or2_base32[4] = BX_SEG_REG_SS;
|
||||
sreg_mod1or2_base32[5] = BX_SEG_REG_SS;
|
||||
sreg_mod1or2_base32[6] = BX_SEG_REG_DS;
|
||||
sreg_mod1or2_base32[7] = BX_SEG_REG_DS;
|
||||
#if BX_SUPPORT_X86_64
|
||||
sreg_mod1or2_base32[8] = BX_SEG_REG_DS;
|
||||
sreg_mod1or2_base32[9] = BX_SEG_REG_DS;
|
||||
sreg_mod1or2_base32[10] = BX_SEG_REG_DS;
|
||||
sreg_mod1or2_base32[11] = BX_SEG_REG_DS;
|
||||
sreg_mod1or2_base32[12] = BX_SEG_REG_DS;
|
||||
sreg_mod1or2_base32[13] = BX_SEG_REG_DS;
|
||||
sreg_mod1or2_base32[14] = BX_SEG_REG_DS;
|
||||
sreg_mod1or2_base32[15] = BX_SEG_REG_DS;
|
||||
#endif
|
||||
// <TAG-INIT-CPU-END>
|
||||
sprintf(name, "CPU %d", BX_CPU_ID);
|
||||
|
||||
mem = addrspace;
|
||||
sprintf(name, "CPU %d", BX_CPU_ID);
|
||||
|
||||
#if BX_WITH_WX
|
||||
register_wx_state();
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: main.cc,v 1.365 2007-11-18 18:27:09 sshwarts Exp $
|
||||
// $Id: main.cc,v 1.366 2007-11-18 21:07:40 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2002 MandrakeSoft S.A.
|
||||
|
|
@ -1234,8 +1234,8 @@ void bx_signal_handler(int signum)
|
|||
bx_gui->show_ips((Bit32u) ips_count);
|
||||
ticks_count = bx_pc_system.time_ticks();
|
||||
counts++;
|
||||
// printf("MIPS: %u\tticks/counts = %u\t(%us)\n",
|
||||
// (unsigned) ips_count, (unsigned) (ticks_count/counts), (unsigned) counts);
|
||||
printf("MIPS: %u\tticks/counts = %u\t\t(%us)\n",
|
||||
(unsigned) ips_count, (unsigned) (ticks_count/counts), (unsigned) counts);
|
||||
}
|
||||
#if !defined(__MINGW32__) && !defined(_MSC_VER)
|
||||
signal(SIGALRM, bx_signal_handler);
|
||||
|
|
|
|||
Loading…
Reference in New Issue