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First step of access bits cleanup and optimization - no perf gain yet

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This commit is contained in:
Stanislav Shwartsman 2008-08-03 19:53:09 +00:00
parent 2e8bc558d1
commit 6398ebb1d4
16 changed files with 117 additions and 155 deletions
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10
bochs/cpu/access.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: access.cc,v 1.115 2008-08-02 10:16:46 sshwarts Exp $
// $Id: access.cc,v 1.116 2008-08-03 19:53:08 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -274,7 +274,7 @@ int BX_CPU_C::int_number(unsigned s)
#if BX_SupportGuest2HostTLB
Bit8u* BX_CPP_AttrRegparmN(2)
BX_CPU_C::v2h_read_byte(bx_address laddr, unsigned curr_pl)
BX_CPU_C::v2h_read_byte(bx_address laddr, bx_bool user)
{
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 0);
bx_address lpf = LPFOf(laddr);
@ -282,7 +282,7 @@ BX_CPU_C::v2h_read_byte(bx_address laddr, unsigned curr_pl)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<curr_pl)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + user)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
@ -294,7 +294,7 @@ BX_CPU_C::v2h_read_byte(bx_address laddr, unsigned curr_pl)
}
Bit8u* BX_CPP_AttrRegparmN(2)
BX_CPU_C::v2h_write_byte(bx_address laddr, unsigned curr_pl)
BX_CPU_C::v2h_write_byte(bx_address laddr, bx_bool user)
{
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 0);
bx_address lpf = LPFOf(laddr);
@ -303,7 +303,7 @@ BX_CPU_C::v2h_write_byte(bx_address laddr, unsigned curr_pl)
{
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << curr_pl)) {
if (tlbEntry->accessBits & (0x04 << user)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset);

44
bochs/cpu/access32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: access32.cc,v 1.5 2008-08-02 10:16:47 sshwarts Exp $
// $Id: access32.cc,v 1.6 2008-08-03 19:53:08 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008 Stanislav Shwartsman
@ -45,7 +45,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, BX_WRITE);
@ -93,7 +93,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_WRITE);
@ -149,7 +149,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_WRITE);
@ -205,7 +205,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_WRITE);
@ -261,7 +261,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 16, BX_WRITE);
@ -318,7 +318,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 16, BX_WRITE);
@ -372,7 +372,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, BX_READ);
@ -418,7 +418,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_READ);
@ -472,7 +472,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_READ);
@ -526,7 +526,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_READ);
@ -579,7 +579,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 16, BX_READ);
@ -633,7 +633,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 16, BX_READ);
@ -689,7 +689,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, BX_RW);
@ -739,7 +739,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_RW);
@ -797,7 +797,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_RW);
@ -855,7 +855,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_RW);
@ -1071,6 +1071,7 @@ void BX_CPU_C::write_new_stack_word_32(bx_segment_reg_t *seg, Bit32u offset, uns
if (seg->cache.valid & SegAccessWOK4G) {
accessOK:
laddr = (Bit32u)(seg->cache.u.segment.base + offset);
bx_bool user = (curr_pl == 3);
#if BX_SupportGuest2HostTLB
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 1);
Bit32u lpf = AlignedAccessLPFOf(laddr, 1) & (BX_CPU_THIS_PTR alignment_check_mask);
@ -1078,7 +1079,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << user)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_WRITE);
@ -1094,7 +1095,7 @@ accessOK:
}
#endif
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
if (BX_CPU_THIS_PTR alignment_check() && curr_pl == 3) {
if (BX_CPU_THIS_PTR alignment_check() && user) {
if (laddr & 1) {
BX_ERROR(("write_new_stack_word_32(): #AC misaligned access"));
exception(BX_AC_EXCEPTION, 0, 0);
@ -1126,6 +1127,7 @@ void BX_CPU_C::write_new_stack_dword_32(bx_segment_reg_t *seg, Bit32u offset, un
if (seg->cache.valid & SegAccessWOK4G) {
accessOK:
laddr = (Bit32u)(seg->cache.u.segment.base + offset);
bx_bool user = (curr_pl == 3);
#if BX_SupportGuest2HostTLB
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 3);
Bit32u lpf = AlignedAccessLPFOf(laddr, 3) & (BX_CPU_THIS_PTR alignment_check_mask);
@ -1133,7 +1135,7 @@ accessOK:
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << user)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_WRITE);
@ -1149,7 +1151,7 @@ accessOK:
}
#endif
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
if (BX_CPU_THIS_PTR alignment_check() && curr_pl == 3) {
if (BX_CPU_THIS_PTR alignment_check() && user) {
if (laddr & 3) {
BX_ERROR(("write_new_stack_dword_32(): #AC misaligned access"));
exception(BX_AC_EXCEPTION, 0, 0);

39
bochs/cpu/access64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: access64.cc,v 1.10 2008-08-02 10:16:47 sshwarts Exp $
// $Id: access64.cc,v 1.11 2008-08-03 19:53:08 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008 Stanislav Shwartsman
@ -43,7 +43,7 @@ BX_CPU_C::write_virtual_byte_64(unsigned s, Bit64u offset, Bit8u data)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, BX_WRITE);
@ -82,7 +82,7 @@ BX_CPU_C::write_virtual_word_64(unsigned s, Bit64u offset, Bit16u data)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_WRITE);
@ -130,7 +130,7 @@ BX_CPU_C::write_virtual_dword_64(unsigned s, Bit64u offset, Bit32u data)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_WRITE);
@ -178,7 +178,7 @@ BX_CPU_C::write_virtual_qword_64(unsigned s, Bit64u offset, Bit64u data)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_WRITE);
@ -226,7 +226,7 @@ BX_CPU_C::write_virtual_dqword_64(unsigned s, Bit64u offset, const BxPackedXmmRe
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 16, BX_WRITE);
@ -275,7 +275,7 @@ BX_CPU_C::write_virtual_dqword_aligned_64(unsigned s, Bit64u offset, const BxPac
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 16, BX_WRITE);
@ -320,7 +320,7 @@ BX_CPU_C::read_virtual_byte_64(unsigned s, Bit64u offset)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, BX_READ);
@ -357,7 +357,7 @@ BX_CPU_C::read_virtual_word_64(unsigned s, Bit64u offset)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_READ);
@ -403,7 +403,7 @@ BX_CPU_C::read_virtual_dword_64(unsigned s, Bit64u offset)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_READ);
@ -449,7 +449,7 @@ BX_CPU_C::read_virtual_qword_64(unsigned s, Bit64u offset)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_READ);
@ -493,7 +493,7 @@ BX_CPU_C::read_virtual_dqword_64(unsigned s, Bit64u offset, BxPackedXmmRegister
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 16, BX_READ);
@ -537,7 +537,7 @@ BX_CPU_C::read_virtual_dqword_aligned_64(unsigned s, Bit64u offset, BxPackedXmmR
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (tlbEntry->accessBits & (1<<CPL)) { // Read this pl OK.
if (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 16, BX_READ);
@ -584,7 +584,7 @@ BX_CPU_C::read_RMW_virtual_byte_64(unsigned s, Bit64u offset)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 1, BX_RW);
@ -625,7 +625,7 @@ BX_CPU_C::read_RMW_virtual_word_64(unsigned s, Bit64u offset)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_RW);
@ -675,7 +675,7 @@ BX_CPU_C::read_RMW_virtual_dword_64(unsigned s, Bit64u offset)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 4, BX_RW);
@ -725,7 +725,7 @@ BX_CPU_C::read_RMW_virtual_qword_64(unsigned s, Bit64u offset)
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << BX_CPU_THIS_PTR user_pl)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_RW);
@ -763,13 +763,14 @@ BX_CPU_C::read_RMW_virtual_qword_64(unsigned s, Bit64u offset)
void BX_CPU_C::write_new_stack_qword_64(Bit64u laddr, unsigned curr_pl, Bit64u data)
{
#if BX_SupportGuest2HostTLB
bx_bool user = (curr_pl == 3);
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 7);
Bit64u lpf = AlignedAccessLPFOf(laddr, 7) & (BX_CPU_THIS_PTR alignment_check_mask);
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (tlbEntry->accessBits & (0x10 << CPL)) {
if (tlbEntry->accessBits & (0x04 << user)) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 8, BX_WRITE);
@ -791,7 +792,7 @@ void BX_CPU_C::write_new_stack_qword_64(Bit64u laddr, unsigned curr_pl, Bit64u d
}
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
if (BX_CPU_THIS_PTR alignment_check() && curr_pl == 3) {
if (BX_CPU_THIS_PTR alignment_check() && user) {
if (laddr & 7) {
BX_ERROR(("write_new_stack_qword_64(): #AC misaligned access"));
exception(BX_AC_EXCEPTION, 0, 0);

4
bochs/cpu/bit64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bit64.cc,v 1.14 2008-07-13 15:52:55 sshwarts Exp $
// $Id: bit64.cc,v 1.15 2008-08-03 19:53:08 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -34,7 +34,6 @@
void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GqEq(bxInstruction_c *i)
{
/* for 64 bit operand size mode */
Bit64u op1_64, op2_64;
/* op2_64 is a register or memory reference */
@ -67,7 +66,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GqEq(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GqEq(bxInstruction_c *i)
{
/* for 64 bit operand size mode */
Bit64u op1_64, op2_64;
/* op2_64 is a register or memory reference */

4
bochs/cpu/cpu.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.233 2008-06-23 02:56:30 sshwarts Exp $
// $Id: cpu.cc,v 1.234 2008-08-03 19:53:08 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -644,7 +644,7 @@ void BX_CPU_C::prefetch(void)
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
Bit8u *fetchPtr = 0;
if (tlbEntry->lpf == lpf && (tlbEntry->accessBits & (0x01 << CPL))) {
if (tlbEntry->lpf == lpf && (tlbEntry->accessBits & (0x01 + BX_CPU_THIS_PTR user_pl))) {
pAddr = A20ADDR(tlbEntry->ppf | pageOffset);
#if BX_SupportGuest2HostTLB
fetchPtr = (Bit8u*) (tlbEntry->hostPageAddr);

16
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.498 2008-08-02 10:16:47 sshwarts Exp $
// $Id: cpu.h,v 1.499 2008-08-03 19:53:08 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -881,6 +881,7 @@ public: // for now...
bx_phy_address pAddrA20Page; // Guest physical address of current instruction
// page with A20() already applied.
unsigned cpu_mode;
bx_bool user_pl;
bx_bool in_smm;
bx_bool nmi_disable;
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
@ -930,7 +931,6 @@ public: // for now...
bxICache_c iCache BX_CPP_AlignN(32);
Bit32u fetchModeMask;
const Bit32u *currPageWriteStampPtr;
BX_SMF void updateFetchModeMask(void);
#endif
struct {
@ -2794,6 +2794,7 @@ public: // for now...
#endif
#endif
BX_SMF void prefetch(void);
BX_SMF void updateFetchModeMask(void);
BX_SMF BX_CPP_INLINE void invalidate_prefetch_q(void)
{
BX_CPU_THIS_PTR eipPageWindowSize = 0;
@ -3001,8 +3002,8 @@ public: // for now...
#endif
#if BX_SupportGuest2HostTLB
BX_SMF Bit8u* v2h_read_byte(bx_address laddr, unsigned curr_pl) BX_CPP_AttrRegparmN(2);
BX_SMF Bit8u* v2h_write_byte(bx_address laddr, unsigned curr_pl) BX_CPP_AttrRegparmN(2);
BX_SMF Bit8u* v2h_read_byte(bx_address laddr, bx_bool user) BX_CPP_AttrRegparmN(2);
BX_SMF Bit8u* v2h_write_byte(bx_address laddr, bx_bool user) BX_CPP_AttrRegparmN(2);
#endif
BX_SMF void branch_near16(Bit16u new_IP) BX_CPP_AttrRegparmN(1);
@ -3329,8 +3330,6 @@ BX_CPP_INLINE void BX_CPU_C::prepareXSAVE(void)
#include "stack.h"
#endif
#if BX_SUPPORT_ICACHE
BX_CPP_INLINE void BX_CPU_C::updateFetchModeMask(void)
{
BX_CPU_THIS_PTR fetchModeMask =
@ -3338,9 +3337,10 @@ BX_CPP_INLINE void BX_CPU_C::updateFetchModeMask(void)
((BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)<<30) |
#endif
(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b << 31);
}
#endif
BX_CPU_THIS_PTR user_pl = // CPL == 3
(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl == 3);
}
#if BX_X86_DEBUGGER
#define BX_HWDebugInstruction 0x00

6
bochs/cpu/ctrl_xfer_pro.cc
View File

@ -1,5 +1,5 @@
////////////////////////////////////////////////////////////////////////
// $Id: ctrl_xfer_pro.cc,v 1.75 2008-05-21 21:38:58 sshwarts Exp $
// $Id: ctrl_xfer_pro.cc,v 1.76 2008-08-03 19:53:08 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -110,9 +110,7 @@ BX_CPU_C::load_cs(bx_selector_t *selector, bx_descriptor_t *descriptor, Bit8u cp
}
#endif
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
updateFetchModeMask();
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
handleAlignmentCheck(); // CPL was modified

4
bochs/cpu/init.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: init.cc,v 1.174 2008-06-14 16:55:45 sshwarts Exp $
// $Id: init.cc,v 1.175 2008-08-03 19:53:08 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -751,8 +751,8 @@ void BX_CPU_C::reset(unsigned source)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0;
#endif
updateFetchModeMask();
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
flushICaches();
#endif

6
bochs/cpu/io.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: io.cc,v 1.64 2008-07-13 13:32:15 sshwarts Exp $
// $Id: io.cc,v 1.65 2008-08-03 19:53:08 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -62,7 +62,7 @@ Bit32u BX_CPU_C::FastRepINSW(bxInstruction_c *i, bx_address dstOff, Bit16u port,
if (laddrDst & 1) return 0;
#if BX_SupportGuest2HostTLB
hostAddrDst = v2h_write_byte(laddrDst, CPL);
hostAddrDst = v2h_write_byte(laddrDst, BX_CPU_THIS_PTR user_pl);
#else
bx_phy_address paddrDst;
@ -146,7 +146,7 @@ Bit32u BX_CPU_C::FastRepOUTSW(bxInstruction_c *i, unsigned srcSeg, bx_address sr
if (laddrSrc & 1) return 0;
#if BX_SupportGuest2HostTLB
hostAddrSrc = v2h_read_byte(laddrSrc, CPL);
hostAddrSrc = v2h_read_byte(laddrSrc, BX_CPU_THIS_PTR user_pl);
#else
bx_phy_address paddrSrc;

61
bochs/cpu/paging.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: paging.cc,v 1.144 2008-08-01 13:28:44 sshwarts Exp $
// $Id: paging.cc,v 1.145 2008-08-03 19:53:08 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -331,49 +331,39 @@ static unsigned priv_check[BX_PRIV_CHECK_SIZE];
// value, necessitating a TLB flush when CR0.WP changes.
//
// The test is:
// OK = 0x01 << ( (W<<2) | CPL ) [W:1=write, 0=read]
// OK = 0x01 << ( (W<<2) | PL ) [W:1=write, 0=read; PL:1=user, 0=sys]
//
// Thus for reads, it is:
// OK = 0x01 << ( CPL )
// OK = 0x01 << ( PL )
// And for writes:
// OK = 0x10 << ( CPL )
// OK = 0x04 << ( PL )
//
// bit 15: a Write from CPL=3 is OK
// bit 14: a Write from CPL=2 is OK
// bit 13: a Write from CPL=1 is OK
// bit 12: a Write from CPL=0 is OK
//
// bit 11: a Read from CPL=3 is OK
// bit 10: a Read from CPL=2 is OK
// bit 9: a Read from CPL=1 is OK
// bit 8: a Read from CPL=0 is OK
// bit 7: a Write from user (CPL=3) is OK
// bit 6: a Write from system is OK
// bit 5: a Read from user (CPL=3) is OK
// bit 4: a Read from system is OK
//
// And the lowest bits are as above, except that they also indicate
// that hostPageAddr is valid, so we do not separately need to test
// that pointer against NULL. These have smaller constants for us
// to be able to use smaller encodings in the trace generators. Note
// that whenever bit n (n=0..7) is set, then also n+8 is set.
// that whenever bit n (n=0..4) is set, then also n+4 is set.
// (The opposite is of course not true)
//
// bit 7: a Write from CPL=3 is OK, hostPageAddr is valid
// bit 6: a Write from CPL=2 is OK, hostPageAddr is valid
// bit 5: a Write from CPL=1 is OK, hostPageAddr is valid
// bit 4: a Write from CPL=0 is OK, hostPageAddr is valid
//
// bit 3: a Read from CPL=3 is OK, hostPageAddr is valid
// bit 2: a Read from CPL=2 is OK, hostPageAddr is valid
// bit 1: a Read from CPL=1 is OK, hostPageAddr is valid
// bit 0: a Read from CPL=0 is OK, hostPageAddr is valid
// bit 3: a Write from user (CPL=3) is OK, hostPageAddr is valid
// bit 2: a Write from system is OK, hostPageAddr is valid
// bit 1: a Read from user (CPL=3) is OK, hostPageAddr is valid
// bit 0: a Read from system is OK, hostPageAddr is valid
//
#define TLB_WriteUserOK 0x8000
#define TLB_WriteSysOK 0x7000
#define TLB_ReadUserOK 0x0800
#define TLB_ReadSysOK 0x0700
#define TLB_WriteUserPtrOK 0x0080
#define TLB_WriteSysPtrOK 0x0070
#define TLB_ReadUserPtrOK 0x0008
#define TLB_ReadSysPtrOK 0x0007
#define TLB_WriteUserOK 0x80
#define TLB_WriteSysOK 0x40
#define TLB_ReadUserOK 0x20
#define TLB_ReadSysOK 0x10
#define TLB_WriteUserPtrOK 0x08
#define TLB_WriteSysPtrOK 0x04
#define TLB_ReadUserPtrOK 0x02
#define TLB_ReadSysPtrOK 0x01
#define TLB_GlobalPage 0x80000000
@ -947,12 +937,11 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
// already looked up TLB for code access
if (access_type != CODE_ACCESS && tlbEntry->lpf == lpf)
if (tlbEntry->lpf == lpf)
{
paddress = tlbEntry->ppf | poffset;
accessBits = tlbEntry->accessBits;
paddress = tlbEntry->ppf | poffset;
if (accessBits & (0x0100 << ((isWrite<<2) | curr_pl)))
if (tlbEntry->accessBits & (0x10 << ((isWrite<<2) | pl)))
return paddress;
// The current access does not have permission according to the info
@ -1135,7 +1124,7 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
#if BX_X86_DEBUGGER
if (! hwbreakpoint_check(laddr))
#endif
accessBits |= (accessBits & 0xff00) >> 8;
accessBits |= (accessBits & 0xF0) >> 4;
}
#endif
tlbEntry->accessBits = accessBits;

33
bochs/cpu/proc_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: proc_ctrl.cc,v 1.249 2008-07-13 15:36:57 sshwarts Exp $
// $Id: proc_ctrl.cc,v 1.250 2008-08-03 19:53:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1050,10 +1050,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOADALL(bxInstruction_c *i)
BX_PANIC(("loadall: CS invalid"));
}
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
updateFetchModeMask();
handleCpuModeChange();
/* ES */
@ -2047,9 +2044,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSENTER(bxInstruction_c *i)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = long_mode();
#endif
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
updateFetchModeMask();
#if BX_SUPPORT_X86_64
handleCpuModeChange(); // mode change could happen only when in long_mode()
@ -2170,9 +2165,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSEXIT(bxInstruction_c *i)
EIP = EDX;
}
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
updateFetchModeMask();
#if BX_SUPPORT_X86_64
handleCpuModeChange(); // mode change could happen only when in long_mode()
@ -2250,10 +2243,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSCALL(bxInstruction_c *i)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 1; /* 64-bit code */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; /* available for use by system */
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
updateFetchModeMask();
handleCpuModeChange(); // mode change could only happen when in long_mode()
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
@ -2304,9 +2294,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSCALL(bxInstruction_c *i)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 32-bit code */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; /* available for use by system */
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
updateFetchModeMask();
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
BX_CPU_THIS_PTR alignment_check_mask = LPF_MASK; // CPL=0
@ -2406,10 +2394,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSRET(bxInstruction_c *i)
temp_RIP = ECX;
}
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
updateFetchModeMask();
handleCpuModeChange(); // mode change could only happen when in long64 mode
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
@ -2446,9 +2431,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSRET(bxInstruction_c *i)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 32-bit code */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; /* available for use by system */
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
updateFetchModeMask();
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
handleAlignmentCheck(); // CPL was modified

6
bochs/cpu/segment_ctrl_pro.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: segment_ctrl_pro.cc,v 1.95 2008-05-26 21:46:38 sshwarts Exp $
// $Id: segment_ctrl_pro.cc,v 1.96 2008-08-03 19:53:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -211,9 +211,7 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS]) {
invalidate_prefetch_q();
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
updateFetchModeMask();
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
handleAlignmentCheck(); // CPL was modified
#endif

7
bochs/cpu/smm.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: smm.cc,v 1.41 2008-07-13 15:35:09 sshwarts Exp $
// $Id: smm.cc,v 1.42 2008-08-03 19:53:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006 Stanislav Shwartsman
@ -164,10 +164,7 @@ void BX_CPU_C::enter_system_management_mode(void)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 16bit default size */
#endif
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
updateFetchModeMask();
handleCpuModeChange();
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK

20
bochs/cpu/string.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: string.cc,v 1.62 2008-06-25 10:34:21 sshwarts Exp $
// $Id: string.cc,v 1.63 2008-08-03 19:53:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -60,7 +60,7 @@ Bit32u BX_CPU_C::FastRepMOVSB(bxInstruction_c *i, unsigned srcSeg, bx_address sr
laddrSrc = BX_CPU_THIS_PTR get_laddr(srcSeg, srcOff);
#if BX_SupportGuest2HostTLB
hostAddrSrc = v2h_read_byte(laddrSrc, CPL);
hostAddrSrc = v2h_read_byte(laddrSrc, BX_CPU_THIS_PTR user_pl);
#else
bx_phy_address paddrSrc;
@ -81,7 +81,7 @@ Bit32u BX_CPU_C::FastRepMOVSB(bxInstruction_c *i, unsigned srcSeg, bx_address sr
laddrDst = BX_CPU_THIS_PTR get_laddr(dstSeg, dstOff);
#if BX_SupportGuest2HostTLB
hostAddrDst = v2h_write_byte(laddrDst, CPL);
hostAddrDst = v2h_write_byte(laddrDst, BX_CPU_THIS_PTR user_pl);
#else
bx_phy_address paddrDst;
@ -155,7 +155,7 @@ Bit32u BX_CPU_C::FastRepMOVSW(bxInstruction_c *i, unsigned srcSeg, bx_address sr
laddrSrc = BX_CPU_THIS_PTR get_laddr(srcSeg, srcOff);
#if BX_SupportGuest2HostTLB
hostAddrSrc = v2h_read_byte(laddrSrc, CPL);
hostAddrSrc = v2h_read_byte(laddrSrc, BX_CPU_THIS_PTR user_pl);
#else
bx_phy_address paddrSrc;
@ -176,7 +176,7 @@ Bit32u BX_CPU_C::FastRepMOVSW(bxInstruction_c *i, unsigned srcSeg, bx_address sr
laddrDst = BX_CPU_THIS_PTR get_laddr(dstSeg, dstOff);
#if BX_SupportGuest2HostTLB
hostAddrDst = v2h_write_byte(laddrDst, CPL);
hostAddrDst = v2h_write_byte(laddrDst, BX_CPU_THIS_PTR user_pl);
#else
bx_phy_address paddrDst;
@ -253,7 +253,7 @@ Bit32u BX_CPU_C::FastRepMOVSD(bxInstruction_c *i, unsigned srcSeg, bx_address sr
laddrSrc = BX_CPU_THIS_PTR get_laddr(srcSeg, srcOff);
#if BX_SupportGuest2HostTLB
hostAddrSrc = v2h_read_byte(laddrSrc, CPL);
hostAddrSrc = v2h_read_byte(laddrSrc, BX_CPU_THIS_PTR user_pl);
#else
bx_phy_address paddrSrc;
@ -274,7 +274,7 @@ Bit32u BX_CPU_C::FastRepMOVSD(bxInstruction_c *i, unsigned srcSeg, bx_address sr
laddrDst = BX_CPU_THIS_PTR get_laddr(dstSeg, dstOff);
#if BX_SupportGuest2HostTLB
hostAddrDst = v2h_write_byte(laddrDst, CPL);
hostAddrDst = v2h_write_byte(laddrDst, BX_CPU_THIS_PTR user_pl);
#else
bx_phy_address paddrDst;
@ -347,7 +347,7 @@ Bit32u BX_CPU_C::FastRepSTOSB(bxInstruction_c *i, unsigned dstSeg, bx_address ds
laddrDst = BX_CPU_THIS_PTR get_laddr(dstSeg, dstOff);
#if BX_SupportGuest2HostTLB
hostAddrDst = v2h_write_byte(laddrDst, CPL);
hostAddrDst = v2h_write_byte(laddrDst, BX_CPU_THIS_PTR user_pl);
#else
bx_phy_address paddrDst;
@ -412,7 +412,7 @@ Bit32u BX_CPU_C::FastRepSTOSW(bxInstruction_c *i, unsigned dstSeg, bx_address ds
laddrDst = BX_CPU_THIS_PTR get_laddr(dstSeg, dstOff);
#if BX_SupportGuest2HostTLB
hostAddrDst = v2h_write_byte(laddrDst, CPL);
hostAddrDst = v2h_write_byte(laddrDst, BX_CPU_THIS_PTR user_pl);
#else
bx_phy_address paddrDst;
@ -479,7 +479,7 @@ Bit32u BX_CPU_C::FastRepSTOSD(bxInstruction_c *i, unsigned dstSeg, bx_address ds
laddrDst = BX_CPU_THIS_PTR get_laddr(dstSeg, dstOff);
#if BX_SupportGuest2HostTLB
hostAddrDst = v2h_write_byte(laddrDst, CPL);
hostAddrDst = v2h_write_byte(laddrDst, BX_CPU_THIS_PTR user_pl);
#else
bx_phy_address paddrDst;

6
bochs/cpu/tasking.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: tasking.cc,v 1.60 2008-07-13 14:01:09 sshwarts Exp $
// $Id: tasking.cc,v 1.61 2008-08-03 19:53:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -624,9 +624,7 @@ void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
exception(BX_TS_EXCEPTION, raw_cs_selector & 0xfffc, 0);
}
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
updateFetchModeMask();
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
handleAlignmentCheck(); // task switch, CPL was modified

6
bochs/cpu/vm8086.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: vm8086.cc,v 1.46 2008-06-12 19:14:40 sshwarts Exp $
// $Id: vm8086.cc,v 1.47 2008-08-03 19:53:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -222,9 +222,7 @@ void BX_CPU_C::init_v8086_mode(void)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl = 3;
#if BX_SUPPORT_ICACHE // update instruction cache
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
updateFetchModeMask();
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
handleAlignmentCheck(); // CPL was modified