*** Current duplicate SSE/SSE2 instructions list ***
MOVUPS_VpsWps (0f 10) = MOVUPD_VpdWpd (66 0f 10) = MOVDQU_VdqWdq (f3 0f 6f) MOVUPS_WpsVps (0f 11) = MOVUPD_WpdVpd (66 0f 11) = MOVDQU_WdqVdq (f3 0f 7f) MOVAPS_VpsWps (0f 28) = MOVAPD_VpdWpd (66 0f 28) = MOVDQA_VdqWdq (66 0f 6f) MOVAPS_WpsVps (0f 29) = MOVAPD_WpdVpd (66 0f 29) = MOVDQA_WdqVdq (66 0f 7f) MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b) MOVLPS_VpsMq (0f 12) = MOVLPD_VsdMq (66 0f 12) MOVLPS_MqVps (0f 13) = MOVLPD_MqVsd (66 0f 13) MOVHPS_VpsMq (0f 16) = MOVHPD_VpdMq (66 0f 16) MOVHPS_MqVps (0f 17) = MOVHPD_MqVpd (66 0f 17) ANDPS_VpsWps (0f 54) = ANDPD_VpdWpd (66 0f 54) = PAND_VpdWpd (66 0f db) ANDNPS_VpsWps (0f 55) = ANDNPD_VpdWpd (66 0f 55) = PANDN_VpdWpd (66 0f df) ORPS_VpsWps (0f 56) = ORPD_VpdWpd (66 0f 56) = POR_VpdWpd (66 0f eb) XORPS_VpsWps (0f 57) = XORPD_VpdWpd (66 0f 57) = PXOR_VpdWpd (66 0f ef) Removed dupes
This commit is contained in:
Stanislav Shwartsman
parent
e03430ec8d
commit
bcd57bdcaf
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.118 2002-11-21 18:22:03 bdenney Exp $
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// $Id: cpu.h,v 1.119 2002-11-25 21:58:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -2067,8 +2067,6 @@ union {
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BX_SMF void MOVHPS_MqVps(bxInstruction_c *i);
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BX_SMF void MOVAPS_VpsWps(bxInstruction_c *i);
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BX_SMF void MOVAPS_WpsVps(bxInstruction_c *i);
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BX_SMF void MOVAPD_VpdWpd(bxInstruction_c *i);
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BX_SMF void MOVAPD_WpdVpd(bxInstruction_c *i);
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BX_SMF void CVTPI2PS_VpsQq(bxInstruction_c *i);
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BX_SMF void CVTSI2SS_VssEd(bxInstruction_c *i);
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BX_SMF void MOVNTPS_MdqVps(bxInstruction_c *i);
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@ -2085,10 +2083,6 @@ union {
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BX_SMF void RSQRTSS_VssWss(bxInstruction_c *i);
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BX_SMF void RCPPS_VpsWps(bxInstruction_c *i);
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BX_SMF void RCPSS_VssWss(bxInstruction_c *i);
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BX_SMF void ANDPS_VpsWps(bxInstruction_c *i);
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BX_SMF void ANDNPS_VpsWps(bxInstruction_c *i);
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BX_SMF void ORPS_VpsWps(bxInstruction_c *i);
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BX_SMF void XORPS_VpsWps(bxInstruction_c *i);
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BX_SMF void ADDPS_VpsWps(bxInstruction_c *i);
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BX_SMF void ADDSS_VssWss(bxInstruction_c *i);
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BX_SMF void MULPS_VpsWps(bxInstruction_c *i);
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@ -2122,9 +2116,7 @@ union {
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/* SSE */
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/* SSE2 */
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BX_SMF void MOVUPD_VpdWpd(bxInstruction_c *i);
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BX_SMF void MOVSD_VsdWsd(bxInstruction_c *i);
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BX_SMF void MOVUPD_WpdVpd(bxInstruction_c *i);
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BX_SMF void MOVSD_WsdVsd(bxInstruction_c *i);
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BX_SMF void UNPCKLPD_VpdWq(bxInstruction_c *i);
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BX_SMF void UNPCKHPD_VpdWq(bxInstruction_c *i);
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@ -2139,10 +2131,6 @@ union {
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BX_SMF void MOVMSKPD_EdVRpd(bxInstruction_c *i);
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BX_SMF void SQRTPD_VpdWpd(bxInstruction_c *i);
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BX_SMF void SQRTSD_VsdWsd(bxInstruction_c *i);
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BX_SMF void ANDPD_VpdWpd(bxInstruction_c *i);
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BX_SMF void ANDNPD_VpdWpd(bxInstruction_c *i);
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BX_SMF void ORPD_VpdWpd(bxInstruction_c *i);
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BX_SMF void XORPD_VpdWpd(bxInstruction_c *i);
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BX_SMF void ADDPD_VpdWpd(bxInstruction_c *i);
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BX_SMF void ADDSD_VsdWsd(bxInstruction_c *i);
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BX_SMF void MULPD_VpdWpd(bxInstruction_c *i);
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@ -2177,8 +2165,6 @@ union {
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BX_SMF void PUNPCKLQDQ_VdqWq(bxInstruction_c *i);
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BX_SMF void PUNPCKHQDQ_VdqWq(bxInstruction_c *i);
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BX_SMF void MOVD_VdqEd(bxInstruction_c *i);
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BX_SMF void MOVDQA_VdqWdq(bxInstruction_c *i);
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BX_SMF void MOVDQU_VdqWdq(bxInstruction_c *i);
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BX_SMF void PSHUFD_VdqWdqIb(bxInstruction_c *i);
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BX_SMF void PSHUFHW_VqWqIb(bxInstruction_c *i);
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BX_SMF void PCMPEQB_VdqWdq(bxInstruction_c *i);
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@ -2186,8 +2172,6 @@ union {
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BX_SMF void PCMPEQD_VdqWdq(bxInstruction_c *i);
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BX_SMF void MOVD_EdVd(bxInstruction_c *i);
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BX_SMF void MOVQ_VqWq(bxInstruction_c *i);
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BX_SMF void MOVDQA_WdqVdq(bxInstruction_c *i);
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BX_SMF void MOVDQU_WdqVdq(bxInstruction_c *i);
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BX_SMF void CMPPD_VpdWpdIb(bxInstruction_c *i);
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BX_SMF void CMPSD_VsdWsdIb(bxInstruction_c *i);
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BX_SMF void MOVNTI_MdGd(bxInstruction_c *i);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.35 2002-11-15 13:05:19 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.36 2002-11-25 21:58:28 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -213,26 +213,38 @@ static BxOpcodeInfo_t opcodesMOV_EdGd[2] = {
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/* SSE Groups */
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/* ********** */
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/* ***********************************
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According to the Intel/AMD Manuals:
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/*
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*** Duplicate SSE/SSE2 instructions ***
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MOVUPS_VpsWps (0f 10) = MOVUPD_VpdWpd (66 0f 10) = MOVDQU_VdqWdq (f3 0f 6f)
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MOVUPS_WpsVps (0f 11) = MOVUPD_WpdVpd (66 0f 11) = MOVDQU_WdqVdq (f3 0f 7f)
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MOVAPS_VpsWps (0f 28) = MOVAPD_VpdWpd (66 0f 28) = MOVDQA_VdqWdq (66 0f 6f)
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MOVAPS_WpsVps (0f 29) = MOVAPD_WpdVpd (66 0f 29) = MOVDQA_WdqVdq (66 0f 7f)
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MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)
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MOVLPS_VpsMq (0f 12) = MOVLPD_VsdMq (66 0f 12)
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MOVLPS_MqVps (0f 13) = MOVLPD_MqVsd (66 0f 13)
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MOVHPS_VpsMq (0f 16) = MOVHPD_VpdMq (66 0f 16)
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MOVHPS_MqVps (0f 17) = MOVHPD_MqVpd (66 0f 17)
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ANDPS_VpsWps (0f 54) = ANDPD_VpdWpd (66 0f 54) = PAND_VpdWpd (66 0f db)
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ANDNPS_VpsWps (0f 55) = ANDNPD_VpdWpd (66 0f 55) = PANDN_VpdWpd (66 0f df)
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ORPS_VpsWps (0f 56) = ORPD_VpdWpd (66 0f 56) = POR_VpdWpd (66 0f eb)
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XORPS_VpsWps (0f 57) = XORPD_VpdWpd (66 0f 57) = PXOR_VpdWpd (66 0f ef)
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MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)
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MOVLPS_VpsMq (0f 12) = MOVLPD_VsdMq (66 0f 12)
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MOVLPS_MqVps (0f 13) = MOVLPD_MqVsd (66 0f 13)
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MOVHPS_VpsMq (0f 16) = MOVHPD_VpdMq (66 0f 16)
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MOVHPS_MqVps (0f 17) = MOVHPD_MqVpd (66 0f 17)
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*/
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f10[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVUPS_VpsWps },
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/* 66 */ { 0, &BX_CPU_C::MOVUPD_VpdWpd },
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/* 66 */ { 0, &BX_CPU_C::MOVUPS_VpsWps },
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/* F2 */ { 0, &BX_CPU_C::MOVSD_VsdWsd },
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/* F3 */ { 0, &BX_CPU_C::MOVSS_VssWss }
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f11[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVUPS_WpsVps },
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/* 66 */ { 0, &BX_CPU_C::MOVUPD_WpdVpd },
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/* 66 */ { 0, &BX_CPU_C::MOVUPS_WpsVps },
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/* F2 */ { 0, &BX_CPU_C::MOVSD_WsdVsd },
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/* F3 */ { 0, &BX_CPU_C::MOVSS_WssVss }
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};
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@ -281,14 +293,14 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f17[4] = {
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f28[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVAPS_VpsWps },
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/* 66 */ { 0, &BX_CPU_C::MOVAPD_VpdWpd },
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/* 66 */ { 0, &BX_CPU_C::MOVAPS_VpsWps },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f29[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVAPS_WpsVps },
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/* 66 */ { 0, &BX_CPU_C::MOVAPD_WpdVpd },
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/* 66 */ { 0, &BX_CPU_C::MOVAPS_WpsVps },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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@ -364,29 +376,29 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f53[4] = {
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f54[4] = {
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/* -- */ { 0, &BX_CPU_C::ANDPS_VpsWps },
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/* 66 */ { 0, &BX_CPU_C::ANDPD_VpdWpd },
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/* -- */ { 0, &BX_CPU_C::PAND_VdqWdq },
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/* 66 */ { 0, &BX_CPU_C::PAND_VdqWdq },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f55[4] = {
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/* -- */ { 0, &BX_CPU_C::ANDNPS_VpsWps },
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/* 66 */ { 0, &BX_CPU_C::ANDNPD_VpdWpd },
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/* -- */ { 0, &BX_CPU_C::PANDN_VdqWdq },
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/* 66 */ { 0, &BX_CPU_C::PANDN_VdqWdq },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f56[4] = {
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/* -- */ { 0, &BX_CPU_C::ORPS_VpsWps },
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/* 66 */ { 0, &BX_CPU_C::ORPD_VpdWpd },
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/* -- */ { 0, &BX_CPU_C::POR_VdqWdq },
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/* 66 */ { 0, &BX_CPU_C::POR_VdqWdq },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f57[4] = {
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/* -- */ { 0, &BX_CPU_C::XORPS_VpsWps },
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/* 66 */ { 0, &BX_CPU_C::XORPD_VpdWpd },
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/* -- */ { 0, &BX_CPU_C::PXOR_VdqWdq },
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/* 66 */ { 0, &BX_CPU_C::PXOR_VdqWdq },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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@ -554,9 +566,9 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f6e[4] = {
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f6f[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVQ_PqQq },
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/* 66 */ { 0, &BX_CPU_C::MOVDQA_VdqWdq },
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/* 66 */ { 0, &BX_CPU_C::MOVAPS_VpsWps },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::MOVDQU_VdqWdq },
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/* F3 */ { 0, &BX_CPU_C::MOVUPS_VpsWps },
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f70[4] = {
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@ -596,9 +608,9 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f7e[4] = {
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f7f[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVQ_QqPq },
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/* 66 */ { 0, &BX_CPU_C::MOVDQA_WdqVdq },
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/* 66 */ { 0, &BX_CPU_C::MOVAPS_WpsVps },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::MOVDQU_WdqVdq },
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/* F3 */ { 0, &BX_CPU_C::MOVUPS_WpsVps },
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0fc2[4] = {
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode64.cc,v 1.31 2002-11-19 05:47:43 bdenney Exp $
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// $Id: fetchdecode64.cc,v 1.32 2002-11-25 21:58:35 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -281,26 +281,38 @@ static BxOpcodeInfo_t opcodesMOV_EdGd[2] = {
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/* SSE Groups */
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/* ********** */
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/* ***********************************
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According to the Intel/AMD Manuals:
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/*
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*** Duplicate SSE/SSE2 instructions ***
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MOVUPS_VpsWps (0f 10) = MOVUPD_VpdWpd (66 0f 10) = MOVDQU_VdqWdq (f3 0f 6f)
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MOVUPS_WpsVps (0f 11) = MOVUPD_WpdVpd (66 0f 11) = MOVDQU_WdqVdq (f3 0f 7f)
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MOVAPS_VpsWps (0f 28) = MOVAPD_VpdWpd (66 0f 28) = MOVDQA_VdqWdq (66 0f 6f)
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MOVAPS_WpsVps (0f 29) = MOVAPD_WpdVpd (66 0f 29) = MOVDQA_WdqVdq (66 0f 7f)
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MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)
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MOVLPS_VpsMq (0f 12) = MOVLPD_VsdMq (66 0f 12)
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MOVLPS_MqVps (0f 13) = MOVLPD_MqVsd (66 0f 13)
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MOVHPS_VpsMq (0f 16) = MOVHPD_VpdMq (66 0f 16)
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MOVHPS_MqVps (0f 17) = MOVHPD_MqVpd (66 0f 17)
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ANDPS_VpsWps (0f 54) = ANDPD_VpdWpd (66 0f 54) = PAND_VpdWpd (66 0f db)
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ANDNPS_VpsWps (0f 55) = ANDNPD_VpdWpd (66 0f 55) = PANDN_VpdWpd (66 0f df)
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ORPS_VpsWps (0f 56) = ORPD_VpdWpd (66 0f 56) = POR_VpdWpd (66 0f eb)
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XORPS_VpsWps (0f 57) = XORPD_VpdWpd (66 0f 57) = PXOR_VpdWpd (66 0f ef)
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MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)
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MOVLPS_VpsMq (0f 12) = MOVLPD_VsdMq (66 0f 12)
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MOVLPS_MqVps (0f 13) = MOVLPD_MqVsd (66 0f 13)
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MOVHPS_VpsMq (0f 16) = MOVHPD_VpdMq (66 0f 16)
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MOVHPS_MqVps (0f 17) = MOVHPD_MqVpd (66 0f 17)
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*/
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f10[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVUPS_VpsWps },
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/* 66 */ { 0, &BX_CPU_C::MOVUPD_VpdWpd },
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/* 66 */ { 0, &BX_CPU_C::MOVUPS_VpsWps },
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/* F2 */ { 0, &BX_CPU_C::MOVSD_VsdWsd },
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/* F3 */ { 0, &BX_CPU_C::MOVSS_VssWss }
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f11[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVUPS_WpsVps },
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/* 66 */ { 0, &BX_CPU_C::MOVUPD_WpdVpd },
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/* 66 */ { 0, &BX_CPU_C::MOVUPS_WpsVps },
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/* F2 */ { 0, &BX_CPU_C::MOVSD_WsdVsd },
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/* F3 */ { 0, &BX_CPU_C::MOVSS_WssVss }
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};
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@ -349,14 +361,14 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f17[4] = {
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f28[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVAPS_VpsWps },
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/* 66 */ { 0, &BX_CPU_C::MOVAPD_VpdWpd },
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/* 66 */ { 0, &BX_CPU_C::MOVAPS_VpsWps },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f29[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVAPS_WpsVps },
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/* 66 */ { 0, &BX_CPU_C::MOVAPD_WpdVpd },
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/* 66 */ { 0, &BX_CPU_C::MOVAPS_WpsVps },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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||||
@ -432,29 +444,29 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f53[4] = {
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t BxOpcodeGroupSSE_0f54[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::ANDPS_VpsWps },
|
||||
/* 66 */ { 0, &BX_CPU_C::ANDPD_VpdWpd },
|
||||
/* -- */ { 0, &BX_CPU_C::PAND_VdqWdq },
|
||||
/* 66 */ { 0, &BX_CPU_C::PAND_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t BxOpcodeGroupSSE_0f55[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::ANDNPS_VpsWps },
|
||||
/* 66 */ { 0, &BX_CPU_C::ANDNPD_VpdWpd },
|
||||
/* -- */ { 0, &BX_CPU_C::PANDN_VdqWdq },
|
||||
/* 66 */ { 0, &BX_CPU_C::PANDN_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t BxOpcodeGroupSSE_0f56[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::ORPS_VpsWps },
|
||||
/* 66 */ { 0, &BX_CPU_C::ORPD_VpdWpd },
|
||||
/* -- */ { 0, &BX_CPU_C::POR_VdqWdq },
|
||||
/* 66 */ { 0, &BX_CPU_C::POR_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t BxOpcodeGroupSSE_0f57[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::XORPS_VpsWps },
|
||||
/* 66 */ { 0, &BX_CPU_C::XORPD_VpdWpd },
|
||||
/* -- */ { 0, &BX_CPU_C::PXOR_VdqWdq },
|
||||
/* 66 */ { 0, &BX_CPU_C::PXOR_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
@ -622,9 +634,9 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f6e[4] = {
|
||||
|
||||
static BxOpcodeInfo_t BxOpcodeGroupSSE_0f6f[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::MOVQ_PqQq },
|
||||
/* 66 */ { 0, &BX_CPU_C::MOVDQA_VdqWdq },
|
||||
/* 66 */ { 0, &BX_CPU_C::MOVAPS_VpsWps },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::MOVDQU_VdqWdq },
|
||||
/* F3 */ { 0, &BX_CPU_C::MOVUPS_VpsWps },
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t BxOpcodeGroupSSE_0f70[4] = {
|
||||
@ -664,9 +676,9 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f7e[4] = {
|
||||
|
||||
static BxOpcodeInfo_t BxOpcodeGroupSSE_0f7f[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::MOVQ_QqPq },
|
||||
/* 66 */ { 0, &BX_CPU_C::MOVDQA_WdqVdq },
|
||||
/* 66 */ { 0, &BX_CPU_C::MOVAPS_WpsVps },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::MOVDQU_WdqVdq },
|
||||
/* F3 */ { 0, &BX_CPU_C::MOVAPS_WpsVps },
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t BxOpcodeGroupSSE_0fc2[4] = {
|
||||
|
||||
239
bochs/cpu/sse.cc
239
bochs/cpu/sse.cc
@ -251,14 +251,29 @@ void BX_CPU_C::FXRSTOR(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
/* MOVUPS: 0F 10 */
|
||||
/* MOVUPD: 66 0F 10 */
|
||||
/* MOVDQU: F3 0F 6F */
|
||||
void BX_CPU_C::MOVUPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVUPS_VpsWps: SSE instruction still not implemented"));
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("MOVUPS_VpsWps: SSE not supported in current configuration"));
|
||||
BX_INFO(("MOVUPS/MOVUPD/MOVDQU_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -275,14 +290,25 @@ void BX_CPU_C::MOVSS_VssWss(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
/* MOVUPS: 0F 11 */
|
||||
/* MOVUPD: 66 0F 11 */
|
||||
/* MOVDQU: F3 0F 7F */
|
||||
void BX_CPU_C::MOVUPS_WpsVps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVUPS_WpsVps: SSE instruction still not implemented"));
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_XMM_REG(i->rm(), op);
|
||||
}
|
||||
else {
|
||||
writeVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
#else
|
||||
BX_INFO(("MOVUPS_WpsVps: SSE not supported in current configuration"));
|
||||
BX_INFO(("MOVUPS/MOVUPD/MOVDQU_WpsVps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -371,26 +397,52 @@ void BX_CPU_C::MOVHPS_MqVps(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
/* MOVAPS: 0F 28 */
|
||||
/* MOVAPD: 66 0F 28 */
|
||||
/* MOVDQA: F3 0F 6F */
|
||||
void BX_CPU_C::MOVAPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVAPS_VpsWps: SSE instruction still not implemented"));
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("MOVAPS_VpsWps: SSE not supported in current configuration"));
|
||||
BX_INFO(("MOVAPS/MOVAPD/MOVDQA_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* MOVAPS: 0F 29 */
|
||||
/* MOVAPD: 66 0F 29 */
|
||||
/* MOVDQA: F3 0F 7F */
|
||||
void BX_CPU_C::MOVAPS_WpsVps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVAPS_WpsVps: SSE instruction still not implemented"));
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_XMM_REG(i->rm(), op);
|
||||
}
|
||||
else {
|
||||
writeVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
#else
|
||||
BX_INFO(("MOVAPS_WpsVps: SSE not supported in current configuration"));
|
||||
BX_INFO(("MOVAPS/MOVAPD/MOVDQA_WpsVps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -419,6 +471,7 @@ void BX_CPU_C::CVTSI2SS_VssEd(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 0F 2B */
|
||||
void BX_CPU_C::MOVNTPS_MdqVps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
@ -433,7 +486,7 @@ void BX_CPU_C::MOVNTPS_MdqVps(bxInstruction_c *i)
|
||||
writeVirtualDQword(i->seg(), RMAddr(i), (Bit8u *)(&val128));
|
||||
|
||||
#else
|
||||
BX_INFO(("MOVNTPS_MdqVps: SSE not supported in current configuration"));
|
||||
BX_INFO(("MOVNTPS/MOVNTPD_MdqVps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -594,54 +647,6 @@ void BX_CPU_C::RCPSS_VssWss(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::ANDPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ANDPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("ANDPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::ANDNPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ANDNPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("ANDNPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::ORPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ORPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("ORPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::XORPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("XORPS_VpsWps: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("XORPS_VpsWps: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::ADDPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
@ -855,3 +860,123 @@ void BX_CPU_C::MASKMOVQ_PqPRq(bxInstruction_c *i)
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ANDPS: 0F 54 */
|
||||
/* ANDPD: 66 0F 54 */
|
||||
/* PAND: F3 0F DB */
|
||||
void BX_CPU_C::PAND_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
op1.xmm64u(0) &= op2.xmm64u(0);
|
||||
op1.xmm64u(1) &= op2.xmm64u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("ANDPS/ANDPD/PAND_VdqWdq: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ANDNPS: 0F 55 */
|
||||
/* ANDNPD: 66 0F 55 */
|
||||
/* PANDN: F3 0F DF */
|
||||
void BX_CPU_C::PANDN_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = ~(op1.xmm64u(0)) & op2.xmm64u(0);
|
||||
result.xmm64u(1) = ~(op1.xmm64u(1)) & op2.xmm64u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("ANDNPS/ANDNPD/PANDN_VdqWdq: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ORPS: 0F 56 */
|
||||
/* ORPD: 66 0F 56 */
|
||||
/* POR: F3 0F EB */
|
||||
void BX_CPU_C::POR_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
op1.xmm64u(0) |= op2.xmm64u(0);
|
||||
op1.xmm64u(1) |= op2.xmm64u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("ORPS/ORPD/POR_VdqWdq: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* XORPS: 0F 57 */
|
||||
/* XORPD: 66 0F 57 */
|
||||
/* PXOR: F3 0F EF */
|
||||
void BX_CPU_C::PXOR_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
op1.xmm64u(0) ^= op2.xmm64u(0);
|
||||
op1.xmm64u(1) ^= op2.xmm64u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("XORPS/XORPD/PXOR_VdqWdq: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -24,42 +24,6 @@
|
||||
#include "bochs.h"
|
||||
#define LOG_THIS BX_CPU_THIS_PTR
|
||||
|
||||
void BX_CPU_C::MOVAPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVAPD_VpdWpd: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MOVAPD_VpdWpd: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MOVAPD_WpdVpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVAPD_WpdVpd: SSE instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MOVAPD_WpdVpd: SSE not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MOVUPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVUPD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MOVUPD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MOVSD_VsdWsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
@ -72,18 +36,6 @@ void BX_CPU_C::MOVSD_VsdWsd(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MOVUPD_WpdVpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVUPD_WpdVpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("MOVUPD_WpdVpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::MOVSD_WsdVsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
@ -252,54 +204,6 @@ void BX_CPU_C::SQRTSD_VsdWsd(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::ANDPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ANDPD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("ANDPD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::ANDNPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ANDNPD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("ANDNPD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::ORPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ORPD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("ORPD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::XORPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("XORPD_VpdWpd: SSE2 instruction still not implemented"));
|
||||
#else
|
||||
BX_INFO(("XORPD_VpdWpd: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::ADDPD_VpdWpd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
@ -1040,56 +944,6 @@ void BX_CPU_C::MOVD_VdqEd(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 6F */
|
||||
void BX_CPU_C::MOVDQA_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("MOVDQA_VdqWdq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* F3 0F 6F */
|
||||
void BX_CPU_C::MOVDQU_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("MOVDQU_VdqWdq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 70 */
|
||||
void BX_CPU_C::PSHUFD_VdqWdqIb(bxInstruction_c *i)
|
||||
{
|
||||
@ -1312,48 +1166,6 @@ void BX_CPU_C::MOVQ_VqWq(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 7F */
|
||||
void BX_CPU_C::MOVDQA_WdqVdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_XMM_REG(i->rm(), op);
|
||||
}
|
||||
else {
|
||||
writeVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
#else
|
||||
BX_INFO(("MOVDQA_WdqVdq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* F3 0F 7F */
|
||||
void BX_CPU_C::MOVDQU_WdqVdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_XMM_REG(i->rm(), op);
|
||||
}
|
||||
else {
|
||||
writeVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
#else
|
||||
BX_INFO(("MOVDQU_WdqVdq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPU_C::CMPPD_VpdWpdIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
@ -1797,34 +1609,6 @@ void BX_CPU_C::PMINUB_VdqWdq(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F DB */
|
||||
void BX_CPU_C::PAND_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
op1.xmm64u(0) &= op2.xmm64u(0);
|
||||
op1.xmm64u(1) &= op2.xmm64u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("PAND_VdqWdq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F DC */
|
||||
void BX_CPU_C::PADDUSB_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
@ -1919,34 +1703,6 @@ void BX_CPU_C::PMAXUB_VdqWdq(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F DF */
|
||||
void BX_CPU_C::PANDN_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = ~(op1.xmm64u(0)) & op2.xmm64u(0);
|
||||
result.xmm64u(1) = ~(op1.xmm64u(1)) & op2.xmm64u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PANDN_VdqWdq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F E0 */
|
||||
void BX_CPU_C::PAVGB_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
@ -2350,34 +2106,6 @@ void BX_CPU_C::PMINSW_VdqWdq(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F EB */
|
||||
void BX_CPU_C::POR_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
op1.xmm64u(0) |= op2.xmm64u(0);
|
||||
op1.xmm64u(1) |= op2.xmm64u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("POR_VdqWdq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F EC */
|
||||
void BX_CPU_C::PADDSB_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
@ -2475,34 +2203,6 @@ void BX_CPU_C::PMAXSW_VdqWdq(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F EF */
|
||||
void BX_CPU_C::PXOR_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
op1.xmm64u(0) ^= op2.xmm64u(0);
|
||||
op1.xmm64u(1) ^= op2.xmm64u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("PXOR_VdqWdq: SSE2 not supported in current configuration"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F F1 */
|
||||
void BX_CPU_C::PSLLW_VdqWdq(bxInstruction_c *i)
|
||||
{
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user