Updated instrumentation
Simplified exception code
This commit is contained in:
Stanislav Shwartsman
parent
c93d13d37b
commit
74b885d74b
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.557 2009-01-20 18:15:25 sshwarts Exp $
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// $Id: cpu.h,v 1.558 2009-01-20 19:34:16 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -279,7 +279,7 @@
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#define BX_MC_EXCEPTION 18
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#define BX_XM_EXCEPTION 19
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#define BX_MSR_MAX_INDEX 0x1000
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#define BX_CPU_HANDLED_EXCEPTIONS 20
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/* MSR registers */
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#define BX_MSR_TSC 0x010
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@ -329,6 +329,8 @@
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#define BX_MSR_MTRR_DEFTYPE 0x2ff
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#endif
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#define BX_MSR_MAX_INDEX 0x1000
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enum {
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BX_MEMTYPE_UC = 0,
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BX_MEMTYPE_WC,
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: exception.cc,v 1.128 2009-01-20 18:15:25 sshwarts Exp $
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// $Id: exception.cc,v 1.129 2009-01-20 19:34:16 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -817,10 +817,37 @@ void BX_CPU_C::interrupt(Bit8u vector, unsigned is_INT, bx_bool is_error_code, B
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// trap: override exception class to TRAP
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void BX_CPU_C::exception(unsigned vector, Bit16u error_code, unsigned unused)
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{
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unsigned exception_type = 0, exception_class = BX_EXCEPTION_CLASS_FAULT;
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bx_bool push_error = 0;
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struct ExceptionInfo {
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unsigned exception_type;
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unsigned exception_class;
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bx_bool push_error;
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};
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BX_INSTR_EXCEPTION(BX_CPU_ID, vector);
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static struct ExceptionInfo exceptions_info[BX_CPU_HANDLED_EXCEPTIONS] = {
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/* DE */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 0 },
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/* DB */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
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/* -- */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 }, // NMI
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/* BP */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_TRAP, 0 },
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/* OF */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_TRAP, 0 },
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/* BR */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
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/* UD */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
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/* NM */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
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/* DF */ { BX_ET_DOUBLE_FAULT, BX_EXCEPTION_CLASS_ABORT, 1 },
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// coprocessor segment overrun (286,386 only)
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/* -- */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_ABORT, 0 },
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/* TS */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
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/* NP */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
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/* SS */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
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/* GP */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
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/* PF */ { BX_ET_PAGE_FAULT, BX_EXCEPTION_CLASS_FAULT, 1 },
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/* -- */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 }, // reserved
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/* MF */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
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/* AC */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 1 },
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/* MC */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_ABORT, 0 },
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/* XM */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 }
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};
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BX_INSTR_EXCEPTION(BX_CPU_ID, vector, error_code);
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#if BX_DEBUGGER
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bx_dbg_exception(BX_CPU_ID, vector, error_code);
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@ -857,131 +884,21 @@ void BX_CPU_C::exception(unsigned vector, Bit16u error_code, unsigned unused)
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}
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}
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// note: fault-class exceptions _except_ #DB set RF in
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// eflags image.
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unsigned exception_type = 0;
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unsigned exception_class = BX_EXCEPTION_CLASS_FAULT;
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bx_bool push_error = 0;
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switch (vector) {
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case BX_DE_EXCEPTION: // DIV by 0
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push_error = 0;
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_CONTRIBUTORY;
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break;
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case BX_DB_EXCEPTION: // debug exceptions
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push_error = 0;
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// Instruction fetch breakpoint - FAULT
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// Data read or write breakpoint - TRAP
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// I/O read or write breakpoint - TRAP
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// General detect condition - FAULT
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// Single-step - TRAP
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// Task-switch - TRAP
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_BENIGN;
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break;
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case 2: // NMI
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push_error = 0;
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exception_type = BX_ET_BENIGN;
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break;
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case BX_BP_EXCEPTION: // breakpoint
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push_error = 0;
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exception_class = BX_EXCEPTION_CLASS_TRAP;
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exception_type = BX_ET_BENIGN;
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break;
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case BX_OF_EXCEPTION: // overflow
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push_error = 0;
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exception_class = BX_EXCEPTION_CLASS_TRAP;
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exception_type = BX_ET_BENIGN;
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break;
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case BX_BR_EXCEPTION: // bounds check
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push_error = 0;
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_BENIGN;
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break;
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case BX_UD_EXCEPTION: // invalid opcode
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push_error = 0;
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_BENIGN;
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break;
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case BX_NM_EXCEPTION: // device not available
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push_error = 0;
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_BENIGN;
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break;
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case BX_DF_EXCEPTION: // double fault
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push_error = 1;
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error_code = 0;
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exception_class = BX_EXCEPTION_CLASS_ABORT;
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exception_type = BX_ET_DOUBLE_FAULT;
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break;
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case 9: // coprocessor segment overrun (286,386 only)
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push_error = 0;
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exception_class = BX_EXCEPTION_CLASS_ABORT;
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exception_type = BX_ET_BENIGN;
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BX_PANIC(("exception(9): unfinished"));
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break;
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case BX_TS_EXCEPTION: // invalid TSS
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push_error = 1;
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_CONTRIBUTORY;
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break;
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case BX_NP_EXCEPTION: // segment not present
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push_error = 1;
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_CONTRIBUTORY;
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break;
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case BX_SS_EXCEPTION: // stack fault
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push_error = 1;
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_CONTRIBUTORY;
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break;
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case BX_GP_EXCEPTION: // general protection
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push_error = 1;
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_CONTRIBUTORY;
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break;
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case BX_PF_EXCEPTION: // page fault
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push_error = 1;
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_PAGE_FAULT;
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break;
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case 15: // reserved
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BX_PANIC(("exception(15): reserved"));
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push_error = 0;
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exception_type = 0;
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break;
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case BX_MF_EXCEPTION: // floating-point error
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push_error = 0;
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_BENIGN;
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break;
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#if BX_CPU_LEVEL >= 4
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case BX_AC_EXCEPTION: // alignment check
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push_error = 1;
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_BENIGN;
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break;
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#endif
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#if BX_CPU_LEVEL >= 5
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case BX_MC_EXCEPTION: // machine check
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BX_PANIC(("exception(): machine-check, vector 18 not implemented"));
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push_error = 0;
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exception_class = BX_EXCEPTION_CLASS_ABORT;
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exception_type = BX_ET_BENIGN;
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break;
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#if BX_SUPPORT_SSE
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case BX_XM_EXCEPTION: // SIMD Floating-Point exception
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push_error = 0;
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exception_class = BX_EXCEPTION_CLASS_FAULT;
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exception_type = BX_ET_BENIGN;
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break;
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#endif
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#endif
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default:
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BX_PANIC(("exception(%u): bad vector", (unsigned) vector));
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exception_type = BX_ET_BENIGN;
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push_error = 0; // keep compiler happy for now
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break;
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if (vector < BX_CPU_HANDLED_EXCEPTIONS) {
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push_error = exceptions_info[vector].push_error;
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exception_class = exceptions_info[vector].exception_class;
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exception_type = exceptions_info[vector].exception_type;
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}
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else {
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BX_PANIC(("exception(%u): bad vector", vector));
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}
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// note: fault-class exceptions _except_ #DB set RF in
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// eflags image.
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if (exception_class == BX_EXCEPTION_CLASS_FAULT)
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{
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// restore RIP/RSP to value before error occurred
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: instrument.cc,v 1.26 2008-11-18 20:55:59 sshwarts Exp $
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// $Id: instrument.cc,v 1.27 2009-01-20 19:34:16 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -187,11 +187,11 @@ void bx_instr_interrupt(unsigned cpu, unsigned vector)
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}
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}
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void bx_instr_exception(unsigned cpu, unsigned vector)
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void bx_instr_exception(unsigned cpu, unsigned vector, unsigned error_code)
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{
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if(active)
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{
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fprintf(stderr, "CPU %u: exception %02xh\n", cpu, vector);
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fprintf(stderr, "CPU %u: exception %02xh, error_code = %x\n", cpu, vector, error_code);
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}
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: instrument.h,v 1.32 2008-12-29 18:02:01 sshwarts Exp $
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// $Id: instrument.h,v 1.33 2009-01-20 19:34:16 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -73,135 +73,137 @@ void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address
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void bx_instr_opcode(unsigned cpu, const Bit8u *opcode, unsigned len, bx_bool is32, bx_bool is64);
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void bx_instr_interrupt(unsigned cpu, unsigned vector);
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void bx_instr_exception(unsigned cpu, unsigned vector);
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void bx_instr_exception(unsigned cpu, unsigned vector, unsigned error_code);
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void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address eip);
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void bx_instr_mem_data_access(unsigned cpu, unsigned seg, bx_address offset, unsigned len, unsigned rw);
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/* initialization/deinitialization of instrumentalization*/
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# define BX_INSTR_INIT_ENV() bx_instr_init_env()
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# define BX_INSTR_EXIT_ENV() bx_instr_exit_env()
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#define BX_INSTR_INIT_ENV() bx_instr_init_env()
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#define BX_INSTR_EXIT_ENV() bx_instr_exit_env()
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/* simulation init, shutdown, reset */
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# define BX_INSTR_INITIALIZE(cpu_id) bx_instr_initialize(cpu_id)
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# define BX_INSTR_EXIT(cpu_id)
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# define BX_INSTR_RESET(cpu_id, type) bx_instr_reset(cpu_id, type)
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# define BX_INSTR_HLT(cpu_id)
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# define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
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# define BX_INSTR_NEW_INSTRUCTION(cpu_id) bx_instr_new_instruction(cpu_id)
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#define BX_INSTR_INITIALIZE(cpu_id) bx_instr_initialize(cpu_id)
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#define BX_INSTR_EXIT(cpu_id)
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#define BX_INSTR_RESET(cpu_id, type) bx_instr_reset(cpu_id, type)
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#define BX_INSTR_HLT(cpu_id)
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#define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
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#define BX_INSTR_NEW_INSTRUCTION(cpu_id) bx_instr_new_instruction(cpu_id)
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/* called from command line debugger */
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# define BX_INSTR_DEBUG_PROMPT()
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# define BX_INSTR_START()
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# define BX_INSTR_STOP()
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# define BX_INSTR_PRINT()
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#define BX_INSTR_DEBUG_PROMPT()
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#define BX_INSTR_START()
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#define BX_INSTR_STOP()
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#define BX_INSTR_PRINT()
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/* branch resoultion */
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# define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip) bx_instr_cnear_branch_taken(cpu_id, new_eip)
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# define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id) bx_instr_cnear_branch_not_taken(cpu_id)
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# define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip) bx_instr_ucnear_branch(cpu_id, what, new_eip)
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# define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip) bx_instr_far_branch(cpu_id, what, new_cs, new_eip)
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#define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip) bx_instr_cnear_branch_taken(cpu_id, new_eip)
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#define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id) bx_instr_cnear_branch_not_taken(cpu_id)
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#define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip) bx_instr_ucnear_branch(cpu_id, what, new_eip)
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#define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip) bx_instr_far_branch(cpu_id, what, new_cs, new_eip)
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/* decoding completed */
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# define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64) \
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#define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64) \
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bx_instr_opcode(cpu_id, opcode, len, is32, is64)
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/* exceptional case and interrupt */
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# define BX_INSTR_EXCEPTION(cpu_id, vector) bx_instr_exception(cpu_id, vector)
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# define BX_INSTR_INTERRUPT(cpu_id, vector) bx_instr_interrupt(cpu_id, vector)
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# define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip) bx_instr_hwinterrupt(cpu_id, vector, cs, eip)
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#define BX_INSTR_EXCEPTION(cpu_id, vector, error_code) \
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bx_instr_exception(cpu_id, vector, error_code)
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#define BX_INSTR_INTERRUPT(cpu_id, vector) bx_instr_interrupt(cpu_id, vector)
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#define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip) bx_instr_hwinterrupt(cpu_id, vector, cs, eip)
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/* TLB/CACHE control instruction executed */
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# define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
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# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
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# define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
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# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
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#define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
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#define BX_INSTR_CACHE_CNTRL(cpu_id, what)
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#define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
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#define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
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/* execution */
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# define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
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# define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
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# define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
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#define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
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#define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
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#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
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/* memory access */
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# define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
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#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
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/* memory access */
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# define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw) \
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#define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw) \
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bx_instr_mem_data_access(cpu_id, seg, offset, len, rw)
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/* called from memory object */
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# define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
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# define BX_INSTR_PHY_READ(cpu_id, addr, len)
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#define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
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#define BX_INSTR_PHY_READ(cpu_id, addr, len)
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/* feedback from device units */
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# define BX_INSTR_INP(addr, len)
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# define BX_INSTR_INP2(addr, len, val)
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# define BX_INSTR_OUTP(addr, len, val)
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#define BX_INSTR_INP(addr, len)
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#define BX_INSTR_INP2(addr, len, val)
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#define BX_INSTR_OUTP(addr, len, val)
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/* wrmsr callback */
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# define BX_INSTR_WRMSR(cpu_id, addr, value)
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#define BX_INSTR_WRMSR(cpu_id, addr, value)
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#else
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#else // BX_INSTRUMENTATION
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/* initialization/deinitialization of instrumentalization*/
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# define BX_INSTR_INIT_ENV()
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# define BX_INSTR_EXIT_ENV()
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/* initialization/deinitialization of instrumentalization */
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#define BX_INSTR_INIT_ENV()
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#define BX_INSTR_EXIT_ENV()
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/* simulation init, shutdown, reset */
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# define BX_INSTR_INITIALIZE(cpu_id)
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# define BX_INSTR_EXIT(cpu_id)
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# define BX_INSTR_RESET(cpu_id, type)
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# define BX_INSTR_HLT(cpu_id)
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# define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
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# define BX_INSTR_NEW_INSTRUCTION(cpu_id)
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#define BX_INSTR_INITIALIZE(cpu_id)
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#define BX_INSTR_EXIT(cpu_id)
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#define BX_INSTR_RESET(cpu_id, type)
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#define BX_INSTR_HLT(cpu_id)
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#define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
|
||||
#define BX_INSTR_NEW_INSTRUCTION(cpu_id)
|
||||
|
||||
/* called from command line debugger */
|
||||
# define BX_INSTR_DEBUG_PROMPT()
|
||||
# define BX_INSTR_START()
|
||||
# define BX_INSTR_STOP()
|
||||
# define BX_INSTR_PRINT()
|
||||
#define BX_INSTR_DEBUG_PROMPT()
|
||||
#define BX_INSTR_START()
|
||||
#define BX_INSTR_STOP()
|
||||
#define BX_INSTR_PRINT()
|
||||
|
||||
/* branch resoultion */
|
||||
# define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip)
|
||||
# define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id)
|
||||
# define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip)
|
||||
# define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip)
|
||||
#define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip)
|
||||
#define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id)
|
||||
#define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip)
|
||||
#define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip)
|
||||
|
||||
/* decoding completed */
|
||||
# define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64)
|
||||
#define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64)
|
||||
|
||||
/* exceptional case and interrupt */
|
||||
# define BX_INSTR_EXCEPTION(cpu_id, vector)
|
||||
# define BX_INSTR_INTERRUPT(cpu_id, vector)
|
||||
# define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip)
|
||||
#define BX_INSTR_EXCEPTION(cpu_id, vector, error_code)
|
||||
#define BX_INSTR_INTERRUPT(cpu_id, vector)
|
||||
#define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip)
|
||||
|
||||
/* TLB/CACHE control instruction executed */
|
||||
# define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
|
||||
# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
|
||||
# define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
|
||||
# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
|
||||
#define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
|
||||
#define BX_INSTR_CACHE_CNTRL(cpu_id, what)
|
||||
#define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
|
||||
#define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
|
||||
|
||||
/* execution */
|
||||
# define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
|
||||
# define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
|
||||
# define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
|
||||
#define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
|
||||
#define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
|
||||
#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
|
||||
|
||||
/* memory access */
|
||||
# define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
|
||||
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
|
||||
|
||||
/* memory access */
|
||||
# define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw)
|
||||
#define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw)
|
||||
|
||||
/* called from memory object */
|
||||
# define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
|
||||
# define BX_INSTR_PHY_READ(cpu_id, addr, len)
|
||||
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
|
||||
#define BX_INSTR_PHY_READ(cpu_id, addr, len)
|
||||
|
||||
/* feedback from device units */
|
||||
# define BX_INSTR_INP(addr, len)
|
||||
# define BX_INSTR_INP2(addr, len, val)
|
||||
# define BX_INSTR_OUTP(addr, len, val)
|
||||
#define BX_INSTR_INP(addr, len)
|
||||
#define BX_INSTR_INP2(addr, len, val)
|
||||
#define BX_INSTR_OUTP(addr, len, val)
|
||||
|
||||
/* wrmsr callback */
|
||||
# define BX_INSTR_WRMSR(cpu_id, addr, value)
|
||||
#define BX_INSTR_WRMSR(cpu_id, addr, value)
|
||||
|
||||
#endif
|
||||
#endif // BX_INSTRUMENTATION
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: instrument.cc,v 1.21 2008-11-18 20:55:59 sshwarts Exp $
|
||||
// $Id: instrument.cc,v 1.22 2009-01-20 19:34:16 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -155,11 +155,11 @@ void bxInstrumentation::bx_instr_interrupt(unsigned vector)
|
||||
}
|
||||
}
|
||||
|
||||
void bxInstrumentation::bx_instr_exception(unsigned vector)
|
||||
void bxInstrumentation::bx_instr_exception(unsigned vector, unsigned error_code)
|
||||
{
|
||||
if(active)
|
||||
{
|
||||
fprintf(stderr, "CPU %u: exception %02xh\n", cpu_id, vector);
|
||||
fprintf(stderr, "CPU %u: exception %02xh error_code=%x\n", cpu_id, vector, error_code);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: instrument.h,v 1.30 2008-12-29 18:02:01 sshwarts Exp $
|
||||
// $Id: instrument.h,v 1.31 2009-01-20 19:34:16 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -110,7 +110,7 @@ public:
|
||||
void bx_instr_opcode(const Bit8u *opcode, unsigned len, bx_bool is32, bx_bool is64);
|
||||
|
||||
void bx_instr_interrupt(unsigned vector);
|
||||
void bx_instr_exception(unsigned vector);
|
||||
void bx_instr_exception(unsigned vector, unsigned error_code);
|
||||
void bx_instr_hwinterrupt(unsigned vector, Bit16u cs, bx_address eip);
|
||||
|
||||
void bx_instr_mem_data_access(unsigned seg, bx_address offset, unsigned len, unsigned rw);
|
||||
@ -124,129 +124,131 @@ void bx_instr_init(unsigned cpu);
|
||||
extern bxInstrumentation *icpu;
|
||||
|
||||
/* initialization/deinitialization of instrumentalization*/
|
||||
# define BX_INSTR_INIT_ENV() bx_instr_init_env()
|
||||
# define BX_INSTR_EXIT_ENV() bx_instr_exit_env()
|
||||
#define BX_INSTR_INIT_ENV() bx_instr_init_env()
|
||||
#define BX_INSTR_EXIT_ENV() bx_instr_exit_env()
|
||||
|
||||
/* simulation init, shutdown, reset */
|
||||
# define BX_INSTR_INITIALIZE(cpu_id) bx_instr_initialize(cpu_id);
|
||||
# define BX_INSTR_EXIT(cpu_id)
|
||||
# define BX_INSTR_RESET(cpu_id, type) icpu[cpu_id].bx_instr_reset(type)
|
||||
# define BX_INSTR_HLT(cpu_id)
|
||||
# define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
|
||||
#define BX_INSTR_INITIALIZE(cpu_id) bx_instr_initialize(cpu_id);
|
||||
#define BX_INSTR_EXIT(cpu_id)
|
||||
#define BX_INSTR_RESET(cpu_id, type) icpu[cpu_id].bx_instr_reset(type)
|
||||
#define BX_INSTR_HLT(cpu_id)
|
||||
#define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
|
||||
|
||||
# define BX_INSTR_NEW_INSTRUCTION(cpu_id) icpu[cpu_id].bx_instr_new_instruction()
|
||||
#define BX_INSTR_NEW_INSTRUCTION(cpu_id) icpu[cpu_id].bx_instr_new_instruction()
|
||||
|
||||
/* called from command line debugger */
|
||||
# define BX_INSTR_DEBUG_PROMPT()
|
||||
# define BX_INSTR_START()
|
||||
# define BX_INSTR_STOP()
|
||||
# define BX_INSTR_PRINT()
|
||||
#define BX_INSTR_DEBUG_PROMPT()
|
||||
#define BX_INSTR_START()
|
||||
#define BX_INSTR_STOP()
|
||||
#define BX_INSTR_PRINT()
|
||||
|
||||
/* branch resoultion */
|
||||
# define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip) icpu[cpu_id].bx_instr_cnear_branch_taken(new_eip)
|
||||
# define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id) icpu[cpu_id].bx_instr_cnear_branch_not_taken()
|
||||
# define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip) icpu[cpu_id].bx_instr_ucnear_branch(what, new_eip)
|
||||
# define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip) icpu[cpu_id].bx_instr_far_branch(what, new_cs, new_eip)
|
||||
#define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip) icpu[cpu_id].bx_instr_cnear_branch_taken(new_eip)
|
||||
#define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id) icpu[cpu_id].bx_instr_cnear_branch_not_taken()
|
||||
#define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip) icpu[cpu_id].bx_instr_ucnear_branch(what, new_eip)
|
||||
#define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip) icpu[cpu_id].bx_instr_far_branch(what, new_cs, new_eip)
|
||||
|
||||
/* decoding completed */
|
||||
# define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64) \
|
||||
#define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64) \
|
||||
icpu[cpu_id].bx_instr_opcode(opcode, len, is32, is64)
|
||||
|
||||
/* exceptional case and interrupt */
|
||||
# define BX_INSTR_EXCEPTION(cpu_id, vector) icpu[cpu_id].bx_instr_exception(vector)
|
||||
# define BX_INSTR_INTERRUPT(cpu_id, vector) icpu[cpu_id].bx_instr_interrupt(vector)
|
||||
# define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip) icpu[cpu_id].bx_instr_hwinterrupt(vector, cs, eip)
|
||||
#define BX_INSTR_EXCEPTION(cpu_id, vector, error_code) \
|
||||
icpu[cpu_id].bx_instr_exception(vector, error_code)
|
||||
|
||||
#define BX_INSTR_INTERRUPT(cpu_id, vector) icpu[cpu_id].bx_instr_interrupt(vector)
|
||||
#define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip) icpu[cpu_id].bx_instr_hwinterrupt(vector, cs, eip)
|
||||
|
||||
/* TLB/CACHE control instruction executed */
|
||||
# define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
|
||||
# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
|
||||
# define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
|
||||
# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
|
||||
#define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
|
||||
#define BX_INSTR_CACHE_CNTRL(cpu_id, what)
|
||||
#define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
|
||||
#define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
|
||||
|
||||
/* execution */
|
||||
# define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
|
||||
# define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
|
||||
# define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
|
||||
#define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
|
||||
#define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
|
||||
#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
|
||||
|
||||
/* memory access */
|
||||
# define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
|
||||
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
|
||||
|
||||
# define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw) \
|
||||
#define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw) \
|
||||
icpu[cpu_id].bx_instr_mem_data_access(seg, offset, len, rw)
|
||||
|
||||
/* called from memory object */
|
||||
# define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
|
||||
# define BX_INSTR_PHY_READ(cpu_id, addr, len)
|
||||
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
|
||||
#define BX_INSTR_PHY_READ(cpu_id, addr, len)
|
||||
|
||||
/* feedback from device units */
|
||||
# define BX_INSTR_INP(addr, len)
|
||||
# define BX_INSTR_INP2(addr, len, val)
|
||||
# define BX_INSTR_OUTP(addr, len, val)
|
||||
#define BX_INSTR_INP(addr, len)
|
||||
#define BX_INSTR_INP2(addr, len, val)
|
||||
#define BX_INSTR_OUTP(addr, len, val)
|
||||
|
||||
/* wrmsr callback */
|
||||
# define BX_INSTR_WRMSR(cpu_id, addr, value)
|
||||
#define BX_INSTR_WRMSR(cpu_id, addr, value)
|
||||
|
||||
#else
|
||||
#else // BX_INSTRUMENTATION
|
||||
|
||||
/* initialization/deinitialization of instrumentalization*/
|
||||
# define BX_INSTR_INIT_ENV()
|
||||
# define BX_INSTR_EXIT_ENV()
|
||||
/* initialization/deinitialization of instrumentalization */
|
||||
#define BX_INSTR_INIT_ENV()
|
||||
#define BX_INSTR_EXIT_ENV()
|
||||
|
||||
/* simulation init, shutdown, reset */
|
||||
# define BX_INSTR_INITIALIZE(cpu_id)
|
||||
# define BX_INSTR_EXIT(cpu_id)
|
||||
# define BX_INSTR_RESET(cpu_id, type)
|
||||
# define BX_INSTR_HLT(cpu_id)
|
||||
# define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
|
||||
# define BX_INSTR_NEW_INSTRUCTION(cpu_id)
|
||||
#define BX_INSTR_INITIALIZE(cpu_id)
|
||||
#define BX_INSTR_EXIT(cpu_id)
|
||||
#define BX_INSTR_RESET(cpu_id, type)
|
||||
#define BX_INSTR_HLT(cpu_id)
|
||||
#define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
|
||||
#define BX_INSTR_NEW_INSTRUCTION(cpu_id)
|
||||
|
||||
/* called from command line debugger */
|
||||
# define BX_INSTR_DEBUG_PROMPT()
|
||||
# define BX_INSTR_START()
|
||||
# define BX_INSTR_STOP()
|
||||
# define BX_INSTR_PRINT()
|
||||
#define BX_INSTR_DEBUG_PROMPT()
|
||||
#define BX_INSTR_START()
|
||||
#define BX_INSTR_STOP()
|
||||
#define BX_INSTR_PRINT()
|
||||
|
||||
/* branch resoultion */
|
||||
# define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip)
|
||||
# define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id)
|
||||
# define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip)
|
||||
# define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip)
|
||||
#define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip)
|
||||
#define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id)
|
||||
#define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip)
|
||||
#define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip)
|
||||
|
||||
/* decoding completed */
|
||||
# define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64)
|
||||
#define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64)
|
||||
|
||||
/* exceptional case and interrupt */
|
||||
# define BX_INSTR_EXCEPTION(cpu_id, vector)
|
||||
# define BX_INSTR_INTERRUPT(cpu_id, vector)
|
||||
# define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip)
|
||||
#define BX_INSTR_EXCEPTION(cpu_id, vector, error_code)
|
||||
#define BX_INSTR_INTERRUPT(cpu_id, vector)
|
||||
#define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip)
|
||||
|
||||
/* TLB/CACHE control instruction executed */
|
||||
# define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
|
||||
# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
|
||||
# define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
|
||||
# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
|
||||
#define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
|
||||
#define BX_INSTR_CACHE_CNTRL(cpu_id, what)
|
||||
#define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
|
||||
#define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
|
||||
|
||||
/* execution */
|
||||
# define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
|
||||
# define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
|
||||
# define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
|
||||
#define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
|
||||
#define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
|
||||
#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
|
||||
|
||||
/* memory access */
|
||||
# define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
|
||||
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
|
||||
|
||||
/* memory access */
|
||||
# define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw)
|
||||
#define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw)
|
||||
|
||||
/* called from memory object */
|
||||
# define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
|
||||
# define BX_INSTR_PHY_READ(cpu_id, addr, len)
|
||||
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
|
||||
#define BX_INSTR_PHY_READ(cpu_id, addr, len)
|
||||
|
||||
/* feedback from device units */
|
||||
# define BX_INSTR_INP(addr, len)
|
||||
# define BX_INSTR_INP2(addr, len, val)
|
||||
# define BX_INSTR_OUTP(addr, len, val)
|
||||
#define BX_INSTR_INP(addr, len)
|
||||
#define BX_INSTR_INP2(addr, len, val)
|
||||
#define BX_INSTR_OUTP(addr, len, val)
|
||||
|
||||
/* wrmsr callback */
|
||||
# define BX_INSTR_WRMSR(cpu_id, addr, value)
|
||||
#define BX_INSTR_WRMSR(cpu_id, addr, value)
|
||||
|
||||
#endif
|
||||
#endif // BX_INSTRUMENTATION
|
||||
|
||||
@ -113,7 +113,7 @@ The callback is called each time, when Bochs simulator executes an interrupt
|
||||
(software interrupt, hardware interrupt or an exception).
|
||||
|
||||
|
||||
void bx_instr_exception(unsigned cpu, unsigned vector);
|
||||
void bx_instr_exception(unsigned cpu, unsigned vector, unsigned error_code);
|
||||
|
||||
The callback is called each time, when Bochs simulator executes an exception.
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: instrument.cc,v 1.30 2008-12-29 18:02:01 sshwarts Exp $
|
||||
// $Id: instrument.cc,v 1.31 2009-01-20 19:34:16 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -52,7 +52,7 @@ void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address
|
||||
void bx_instr_opcode(unsigned cpu, const Bit8u *opcode, unsigned len, bx_bool is32, bx_bool is64) {}
|
||||
|
||||
void bx_instr_interrupt(unsigned cpu, unsigned vector) {}
|
||||
void bx_instr_exception(unsigned cpu, unsigned vector) {}
|
||||
void bx_instr_exception(unsigned cpu, unsigned vector, unsigned error_code) {}
|
||||
void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address eip) {}
|
||||
|
||||
void bx_instr_tlb_cntrl(unsigned cpu, unsigned what, bx_phy_address new_cr3) {}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: instrument.h,v 1.38 2008-12-29 18:02:01 sshwarts Exp $
|
||||
// $Id: instrument.h,v 1.39 2009-01-20 19:34:16 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -81,7 +81,7 @@ void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address
|
||||
void bx_instr_opcode(unsigned cpu, const Bit8u *opcode, unsigned len, bx_bool is32, bx_bool is64);
|
||||
|
||||
void bx_instr_interrupt(unsigned cpu, unsigned vector);
|
||||
void bx_instr_exception(unsigned cpu, unsigned vector);
|
||||
void bx_instr_exception(unsigned cpu, unsigned vector, unsigned error_code);
|
||||
void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address eip);
|
||||
|
||||
void bx_instr_tlb_cntrl(unsigned cpu, unsigned what, bx_phy_address new_cr3);
|
||||
@ -105,132 +105,134 @@ void bx_instr_phy_read(unsigned cpu, bx_address addr, unsigned len);
|
||||
void bx_instr_wrmsr(unsigned cpu, unsigned addr, Bit64u value);
|
||||
|
||||
/* initialization/deinitialization of instrumentalization*/
|
||||
# define BX_INSTR_INIT_ENV() bx_instr_init_env()
|
||||
# define BX_INSTR_EXIT_ENV() bx_instr_exit_env()
|
||||
#define BX_INSTR_INIT_ENV() bx_instr_init_env()
|
||||
#define BX_INSTR_EXIT_ENV() bx_instr_exit_env()
|
||||
|
||||
/* simulation init, shutdown, reset */
|
||||
# define BX_INSTR_INITIALIZE(cpu_id) bx_instr_initialize(cpu_id)
|
||||
# define BX_INSTR_EXIT(cpu_id) bx_instr_exit(cpu_id)
|
||||
# define BX_INSTR_RESET(cpu_id, type) bx_instr_reset(cpu_id, type)
|
||||
# define BX_INSTR_HLT(cpu_id) bx_instr_hlt(cpu_id)
|
||||
#define BX_INSTR_INITIALIZE(cpu_id) bx_instr_initialize(cpu_id)
|
||||
#define BX_INSTR_EXIT(cpu_id) bx_instr_exit(cpu_id)
|
||||
#define BX_INSTR_RESET(cpu_id, type) bx_instr_reset(cpu_id, type)
|
||||
#define BX_INSTR_HLT(cpu_id) bx_instr_hlt(cpu_id)
|
||||
|
||||
# define BX_INSTR_MWAIT(cpu_id, addr, len, flags) \
|
||||
#define BX_INSTR_MWAIT(cpu_id, addr, len, flags) \
|
||||
bx_instr_mwait(cpu_id, addr, len, flags)
|
||||
|
||||
# define BX_INSTR_NEW_INSTRUCTION(cpu_id) bx_instr_new_instruction(cpu_id)
|
||||
#define BX_INSTR_NEW_INSTRUCTION(cpu_id) bx_instr_new_instruction(cpu_id)
|
||||
|
||||
/* called from command line debugger */
|
||||
# define BX_INSTR_DEBUG_PROMPT() bx_instr_debug_promt()
|
||||
# define BX_INSTR_START() bx_instr_start()
|
||||
# define BX_INSTR_STOP() bx_instr_stop()
|
||||
# define BX_INSTR_PRINT() bx_instr_print()
|
||||
#define BX_INSTR_DEBUG_PROMPT() bx_instr_debug_promt()
|
||||
#define BX_INSTR_START() bx_instr_start()
|
||||
#define BX_INSTR_STOP() bx_instr_stop()
|
||||
#define BX_INSTR_PRINT() bx_instr_print()
|
||||
|
||||
/* branch resoultion */
|
||||
# define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip) bx_instr_cnear_branch_taken(cpu_id, new_eip)
|
||||
# define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id) bx_instr_cnear_branch_not_taken(cpu_id)
|
||||
# define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip) bx_instr_ucnear_branch(cpu_id, what, new_eip)
|
||||
# define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip) bx_instr_far_branch(cpu_id, what, new_cs, new_eip)
|
||||
#define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip) bx_instr_cnear_branch_taken(cpu_id, new_eip)
|
||||
#define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id) bx_instr_cnear_branch_not_taken(cpu_id)
|
||||
#define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip) bx_instr_ucnear_branch(cpu_id, what, new_eip)
|
||||
#define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip) bx_instr_far_branch(cpu_id, what, new_cs, new_eip)
|
||||
|
||||
/* decoding completed */
|
||||
# define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64) \
|
||||
#define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64) \
|
||||
bx_instr_opcode(cpu_id, opcode, len, is32, is64)
|
||||
|
||||
/* exceptional case and interrupt */
|
||||
# define BX_INSTR_EXCEPTION(cpu_id, vector) bx_instr_exception(cpu_id, vector)
|
||||
# define BX_INSTR_INTERRUPT(cpu_id, vector) bx_instr_interrupt(cpu_id, vector)
|
||||
# define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip) bx_instr_hwinterrupt(cpu_id, vector, cs, eip)
|
||||
#define BX_INSTR_EXCEPTION(cpu_id, vector, error_code) \
|
||||
bx_instr_exception(cpu_id, vector, error_code)
|
||||
|
||||
#define BX_INSTR_INTERRUPT(cpu_id, vector) bx_instr_interrupt(cpu_id, vector)
|
||||
#define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip) bx_instr_hwinterrupt(cpu_id, vector, cs, eip)
|
||||
|
||||
/* TLB/CACHE control instruction executed */
|
||||
# define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr) bx_instr_clflush(cpu_id, laddr, paddr)
|
||||
# define BX_INSTR_CACHE_CNTRL(cpu_id, what) bx_instr_cache_cntrl(cpu_id, what)
|
||||
# define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3) bx_instr_tlb_cntrl(cpu_id, what, new_cr3)
|
||||
# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset) \
|
||||
#define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr) bx_instr_clflush(cpu_id, laddr, paddr)
|
||||
#define BX_INSTR_CACHE_CNTRL(cpu_id, what) bx_instr_cache_cntrl(cpu_id, what)
|
||||
#define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3) bx_instr_tlb_cntrl(cpu_id, what, new_cr3)
|
||||
#define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset) \
|
||||
bx_instr_prefetch_hint(cpu_id, what, seg, offset)
|
||||
|
||||
/* execution */
|
||||
# define BX_INSTR_BEFORE_EXECUTION(cpu_id, i) bx_instr_before_execution(cpu_id, i)
|
||||
# define BX_INSTR_AFTER_EXECUTION(cpu_id, i) bx_instr_after_execution(cpu_id, i)
|
||||
# define BX_INSTR_REPEAT_ITERATION(cpu_id, i) bx_instr_repeat_iteration(cpu_id, i)
|
||||
#define BX_INSTR_BEFORE_EXECUTION(cpu_id, i) bx_instr_before_execution(cpu_id, i)
|
||||
#define BX_INSTR_AFTER_EXECUTION(cpu_id, i) bx_instr_after_execution(cpu_id, i)
|
||||
#define BX_INSTR_REPEAT_ITERATION(cpu_id, i) bx_instr_repeat_iteration(cpu_id, i)
|
||||
|
||||
/* memory access */
|
||||
# define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw) bx_instr_lin_access(cpu_id, lin, phy, len, rw)
|
||||
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw) bx_instr_lin_access(cpu_id, lin, phy, len, rw)
|
||||
|
||||
/* memory access */
|
||||
# define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw) bx_instr_mem_data_access(cpu_id, seg, offset, len, rw)
|
||||
#define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw) bx_instr_mem_data_access(cpu_id, seg, offset, len, rw)
|
||||
|
||||
/* called from memory object */
|
||||
# define BX_INSTR_PHY_WRITE(cpu_id, addr, len) bx_instr_phy_write(cpu_id, addr, len)
|
||||
# define BX_INSTR_PHY_READ(cpu_id, addr, len) bx_instr_phy_read(cpu_id, addr, len)
|
||||
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len) bx_instr_phy_write(cpu_id, addr, len)
|
||||
#define BX_INSTR_PHY_READ(cpu_id, addr, len) bx_instr_phy_read(cpu_id, addr, len)
|
||||
|
||||
/* feedback from device units */
|
||||
# define BX_INSTR_INP(addr, len) bx_instr_inp(addr, len)
|
||||
# define BX_INSTR_INP2(addr, len, val) bx_instr_inp2(addr, len, val)
|
||||
# define BX_INSTR_OUTP(addr, len, val) bx_instr_outp(addr, len, val)
|
||||
#define BX_INSTR_INP(addr, len) bx_instr_inp(addr, len)
|
||||
#define BX_INSTR_INP2(addr, len, val) bx_instr_inp2(addr, len, val)
|
||||
#define BX_INSTR_OUTP(addr, len, val) bx_instr_outp(addr, len, val)
|
||||
|
||||
/* wrmsr callback */
|
||||
# define BX_INSTR_WRMSR(cpu_id, addr, value) bx_instr_wrmsr(cpu_id, addr, value)
|
||||
#define BX_INSTR_WRMSR(cpu_id, addr, value) bx_instr_wrmsr(cpu_id, addr, value)
|
||||
|
||||
#else
|
||||
|
||||
/* initialization/deinitialization of instrumentalization*/
|
||||
# define BX_INSTR_INIT_ENV()
|
||||
# define BX_INSTR_EXIT_ENV()
|
||||
/* initialization/deinitialization of instrumentalization */
|
||||
#define BX_INSTR_INIT_ENV()
|
||||
#define BX_INSTR_EXIT_ENV()
|
||||
|
||||
/* simulation init, shutdown, reset */
|
||||
# define BX_INSTR_INITIALIZE(cpu_id)
|
||||
# define BX_INSTR_EXIT(cpu_id)
|
||||
# define BX_INSTR_RESET(cpu_id, type)
|
||||
# define BX_INSTR_HLT(cpu_id)
|
||||
# define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
|
||||
# define BX_INSTR_NEW_INSTRUCTION(cpu_id)
|
||||
#define BX_INSTR_INITIALIZE(cpu_id)
|
||||
#define BX_INSTR_EXIT(cpu_id)
|
||||
#define BX_INSTR_RESET(cpu_id, type)
|
||||
#define BX_INSTR_HLT(cpu_id)
|
||||
#define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
|
||||
#define BX_INSTR_NEW_INSTRUCTION(cpu_id)
|
||||
|
||||
/* called from command line debugger */
|
||||
# define BX_INSTR_DEBUG_PROMPT()
|
||||
# define BX_INSTR_START()
|
||||
# define BX_INSTR_STOP()
|
||||
# define BX_INSTR_PRINT()
|
||||
#define BX_INSTR_DEBUG_PROMPT()
|
||||
#define BX_INSTR_START()
|
||||
#define BX_INSTR_STOP()
|
||||
#define BX_INSTR_PRINT()
|
||||
|
||||
/* branch resoultion */
|
||||
# define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip)
|
||||
# define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id)
|
||||
# define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip)
|
||||
# define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip)
|
||||
#define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip)
|
||||
#define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id)
|
||||
#define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip)
|
||||
#define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip)
|
||||
|
||||
/* decoding completed */
|
||||
# define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64)
|
||||
#define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64)
|
||||
|
||||
/* exceptional case and interrupt */
|
||||
# define BX_INSTR_EXCEPTION(cpu_id, vector)
|
||||
# define BX_INSTR_INTERRUPT(cpu_id, vector)
|
||||
# define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip)
|
||||
#define BX_INSTR_EXCEPTION(cpu_id, vector, error_code)
|
||||
#define BX_INSTR_INTERRUPT(cpu_id, vector)
|
||||
#define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip)
|
||||
|
||||
/* TLB/CACHE control instruction executed */
|
||||
# define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
|
||||
# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
|
||||
# define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
|
||||
# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
|
||||
#define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
|
||||
#define BX_INSTR_CACHE_CNTRL(cpu_id, what)
|
||||
#define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
|
||||
#define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
|
||||
|
||||
/* execution */
|
||||
# define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
|
||||
# define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
|
||||
# define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
|
||||
#define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
|
||||
#define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
|
||||
#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
|
||||
|
||||
/* memory access */
|
||||
# define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
|
||||
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
|
||||
|
||||
/* memory access */
|
||||
# define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw)
|
||||
#define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw)
|
||||
|
||||
/* called from memory object */
|
||||
# define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
|
||||
# define BX_INSTR_PHY_READ(cpu_id, addr, len)
|
||||
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
|
||||
#define BX_INSTR_PHY_READ(cpu_id, addr, len)
|
||||
|
||||
/* feedback from device units */
|
||||
# define BX_INSTR_INP(addr, len)
|
||||
# define BX_INSTR_INP2(addr, len, val)
|
||||
# define BX_INSTR_OUTP(addr, len, val)
|
||||
#define BX_INSTR_INP(addr, len)
|
||||
#define BX_INSTR_INP2(addr, len, val)
|
||||
#define BX_INSTR_OUTP(addr, len, val)
|
||||
|
||||
/* wrmsr callback */
|
||||
# define BX_INSTR_WRMSR(cpu_id, addr, value)
|
||||
#define BX_INSTR_WRMSR(cpu_id, addr, value)
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user