More use of LOAD_Ex method
This commit is contained in:
Stanislav Shwartsman
parent
79cabe4bec
commit
1da5943f1a
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: bit16.cc,v 1.12 2008-08-08 09:22:46 sshwarts Exp $
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// $Id: bit16.cc,v 1.13 2008-08-10 19:34:28 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -32,26 +32,15 @@
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#if BX_CPU_LEVEL >= 3
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GwEw(bxInstruction_c *i)
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GwEwR(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16;
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/* op2_16 is a register or memory reference */
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op2_16 = read_virtual_word(i->seg(), eaddr);
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}
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Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
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if (op2_16 == 0) {
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assert_ZF(); /* op1_16 undefined */
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}
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else {
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op1_16 = 0;
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Bit16u op1_16 = 0;
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while ((op2_16 & 0x01) == 0) {
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op1_16++;
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op2_16 >>= 1;
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@ -65,26 +54,15 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GwEw(bxInstruction_c *i)
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}
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GwEw(bxInstruction_c *i)
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GwEwR(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16;
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/* op2_16 is a register or memory reference */
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op2_16 = read_virtual_word(i->seg(), eaddr);
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}
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Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
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if (op2_16 == 0) {
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assert_ZF(); /* op1_16 undefined */
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}
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else {
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op1_16 = 15;
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Bit16u op1_16 = 15;
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while ((op2_16 & 0x8000) == 0) {
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op1_16--;
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op2_16 <<= 1;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: bit32.cc,v 1.11 2008-08-08 09:22:46 sshwarts Exp $
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// $Id: bit32.cc,v 1.12 2008-08-10 19:34:28 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -32,26 +32,15 @@
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#if BX_CPU_LEVEL >= 3
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GdEd(bxInstruction_c *i)
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GdEdR(bxInstruction_c *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32;
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/* op2_32 is a register or memory reference */
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if (i->modC0()) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op2_32 = read_virtual_dword(i->seg(), eaddr);
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}
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Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
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if (op2_32 == 0) {
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assert_ZF(); /* op1_32 undefined */
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}
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else {
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op1_32 = 0;
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Bit32u op1_32 = 0;
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while ((op2_32 & 0x01) == 0) {
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op1_32++;
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op2_32 >>= 1;
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@ -65,26 +54,15 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GdEd(bxInstruction_c *i)
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}
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GdEd(bxInstruction_c *i)
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GdEdR(bxInstruction_c *i)
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{
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/* for 32 bit operand size mode */
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Bit32u op1_32, op2_32;
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/* op2_32 is a register or memory reference */
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if (i->modC0()) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op2_32 = read_virtual_dword(i->seg(), eaddr);
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}
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Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
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if (op2_32 == 0) {
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assert_ZF(); /* op1_32 undefined */
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}
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else {
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op1_32 = 31;
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Bit32u op1_32 = 31;
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while ((op2_32 & 0x80000000) == 0) {
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op1_32--;
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op2_32 <<= 1;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: bit64.cc,v 1.16 2008-08-08 09:22:46 sshwarts Exp $
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// $Id: bit64.cc,v 1.17 2008-08-10 19:34:28 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -32,25 +32,15 @@
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#if BX_SUPPORT_X86_64
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GqEq(bxInstruction_c *i)
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GqEqR(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64;
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/* op2_64 is a register or memory reference */
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op2_64 = read_virtual_qword_64(i->seg(), eaddr);
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}
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Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
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if (op2_64 == 0) {
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assert_ZF(); /* op1_64 undefined */
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}
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else {
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op1_64 = 0;
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Bit64u op1_64 = 0;
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while ((op2_64 & 0x01) == 0) {
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op1_64++;
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op2_64 >>= 1;
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@ -64,25 +54,15 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GqEq(bxInstruction_c *i)
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}
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GqEq(bxInstruction_c *i)
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GqEqR(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64;
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/* op2_64 is a register or memory reference */
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if (i->modC0()) {
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op2_64 = BX_READ_64BIT_REG(i->rm());
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}
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else {
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op2_64 = read_virtual_qword_64(i->seg(), eaddr);
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}
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Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
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if (op2_64 == 0) {
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assert_ZF(); /* op1_64 undefined */
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}
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else {
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op1_64 = 63;
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Bit64u op1_64 = 63;
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while ((op2_64 & BX_CONST64(0x8000000000000000)) == 0) {
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op1_64--;
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op2_64 <<= 1;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.502 2008-08-09 21:05:05 sshwarts Exp $
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// $Id: cpu.h,v 1.503 2008-08-10 19:34:28 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1375,10 +1375,10 @@ public: // for now...
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BX_SMF void SHLD_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHLD_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSF_GwEw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSF_GdEd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSR_GwEw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSR_GdEd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSF_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSF_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSR_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSR_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BT_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BT_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1640,8 +1640,6 @@ public: // for now...
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BX_SMF void CALL_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CALL_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CALL_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CALL_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CALL32_Ep(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CALL16_Ep(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1650,8 +1648,6 @@ public: // for now...
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BX_SMF void JMP_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void JMP_EwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void JMP_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void JMP_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SLDT_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void STR_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1674,6 +1670,8 @@ public: // for now...
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#if BX_SUPPORT_X86_64
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BX_SMF void LOAD_Eq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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#endif
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BX_SMF void LOAD_Wss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_Wsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_Wdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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#if BX_SUPPORT_FPU == 0 // if FPU is disabled
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@ -2532,8 +2530,8 @@ public: // for now...
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BX_SMF void MOVSX_GqEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVSX_GqEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSF_GqEq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSR_GqEq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSF_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSR_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BT_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BTS_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -2590,10 +2588,8 @@ public: // for now...
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BX_SMF void DEC_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void INC_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void DEC_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CALL_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CALL_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CALL64_Ep(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void JMP_EqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void JMP_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void JMP64_Ep(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PUSHF_Fq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: ctrl_xfer16.cc,v 1.59 2008-08-08 09:22:46 sshwarts Exp $
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// $Id: ctrl_xfer16.cc,v 1.60 2008-08-10 19:34:28 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -251,28 +251,6 @@ done:
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_EwM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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Bit16u op1_16 = read_virtual_word(i->seg(), eaddr);
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if (op1_16 > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
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{
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BX_ERROR(("CALL_Ew: IP out of CS limits!"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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push_16(IP);
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RIP = op1_16;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, EIP);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_EwR(bxInstruction_c *i)
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{
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Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
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@ -568,16 +546,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::JNLE_Jw(bxInstruction_c *i)
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#endif
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_EwM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit16u new_IP = read_virtual_word(i->seg(), eaddr);
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branch_near16(new_IP);
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP, new_IP);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_EwR(bxInstruction_c *i)
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{
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Bit16u new_IP = BX_READ_16BIT_REG(i->rm());
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: ctrl_xfer32.cc,v 1.76 2008-08-08 09:22:46 sshwarts Exp $
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// $Id: ctrl_xfer32.cc,v 1.77 2008-08-10 19:34:28 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -249,28 +249,6 @@ done:
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_EdM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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Bit32u op1_32 = read_virtual_dword(i->seg(), eaddr);
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if (op1_32 > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
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{
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BX_ERROR(("CALL_Ed: EIP out of CS limits!"));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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push_32(EIP);
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RIP = op1_32;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, EIP);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_EdR(bxInstruction_c *i)
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{
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#if BX_DEBUGGER
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@ -601,16 +579,6 @@ done:
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_EdM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
|
||||
Bit32u new_EIP = read_virtual_dword(i->seg(), eaddr);
|
||||
branch_near32(new_EIP);
|
||||
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP, new_EIP);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_EdR(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u new_EIP = BX_READ_32BIT_REG(i->rm());
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
////////c/////////////////////////////////////////////////////////////////
|
||||
// $Id: ctrl_xfer64.cc,v 1.71 2008-08-08 09:22:47 sshwarts Exp $
|
||||
// $Id: ctrl_xfer64.cc,v 1.72 2008-08-10 19:34:28 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -151,28 +151,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_Jq(bxInstruction_c *i)
|
||||
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, RIP);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_EqM(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
#if BX_DEBUGGER
|
||||
BX_CPU_THIS_PTR show_flag |= Flag_call;
|
||||
#endif
|
||||
|
||||
Bit64u op1_64 = read_virtual_qword_64(i->seg(), eaddr);
|
||||
|
||||
if (! IsCanonical(op1_64))
|
||||
{
|
||||
BX_ERROR(("CALL_Eq: canonical RIP violation"));
|
||||
exception(BX_GP_EXCEPTION, 0, 0);
|
||||
}
|
||||
|
||||
push_64(RIP);
|
||||
RIP = op1_64;
|
||||
|
||||
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, RIP);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_EqR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_DEBUGGER
|
||||
@ -443,22 +421,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::JNLE_Jq(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_EqM(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
Bit64u op1_64 = read_virtual_qword_64(i->seg(), eaddr);
|
||||
|
||||
if (! IsCanonical(op1_64)) {
|
||||
BX_ERROR(("JMP_Eq: canonical RIP violation"));
|
||||
exception(BX_GP_EXCEPTION, 0, 0);
|
||||
}
|
||||
|
||||
RIP = op1_64;
|
||||
|
||||
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP, RIP);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_EqR(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: data_xfer.cc,v 1.2 2008-08-09 21:07:48 sshwarts Exp $
|
||||
// $Id: data_xfer.cc,v 1.3 2008-08-10 19:34:28 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2008 Stanislav Shwartsman
|
||||
@ -55,3 +55,19 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wdq(bxInstruction_c *i)
|
||||
readVirtualDQwordAligned(i->seg(), eaddr, (Bit8u *)(&BX_READ_XMM_REG(BX_TMP_REGISTER)));
|
||||
BX_CPU_CALL_METHOD(i->execute2, (i));
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wss(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
Bit32u val_32 = read_virtual_dword(i->seg(), eaddr);
|
||||
BX_WRITE_XMM_REG_LO_DWORD(BX_TMP_REGISTER, val_32);
|
||||
BX_CPU_CALL_METHOD(i->execute2, (i));
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wsd(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
Bit64u val_64 = read_virtual_qword(i->seg(), eaddr);
|
||||
BX_WRITE_XMM_REG_LO_QWORD(BX_TMP_REGISTER, val_64);
|
||||
BX_CPU_CALL_METHOD(i->execute2, (i));
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: fetchdecode.cc,v 1.198 2008-08-09 21:05:05 sshwarts Exp $
|
||||
// $Id: fetchdecode.cc,v 1.199 2008-08-10 19:34:28 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -690,8 +690,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
|
||||
/* 0F B9 /wr */ { 0, BX_IA_UD2B },
|
||||
/* 0F BA /wr */ { BxGroup8, BX_IA_ERROR, BxOpcodeInfoG8EwIbR },
|
||||
/* 0F BB /wr */ { 0, BX_IA_BTC_EwGwR },
|
||||
/* 0F BC /wr */ { 0, BX_IA_BSF_GwEw },
|
||||
/* 0F BD /wr */ { 0, BX_IA_BSR_GwEw },
|
||||
/* 0F BC /wr */ { 0, BX_IA_BSF_GwEwR },
|
||||
/* 0F BD /wr */ { 0, BX_IA_BSR_GwEwR },
|
||||
/* 0F BE /wr */ { 0, BX_IA_MOVSX_GwEbR },
|
||||
/* 0F BF /wr */ { 0, BX_IA_MOV_GwEwR }, // MOVSX_GwEw
|
||||
/* 0F C0 /wr */ { 0, BX_IA_XADD_EbGbR },
|
||||
@ -1253,8 +1253,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
|
||||
/* 0F B9 /dr */ { BxTraceEnd, BX_IA_UD2B },
|
||||
/* 0F BA /dr */ { BxGroup8, BX_IA_ERROR, BxOpcodeInfoG8EdIbR },
|
||||
/* 0F BB /dr */ { 0, BX_IA_BTC_EdGdR },
|
||||
/* 0F BC /dr */ { 0, BX_IA_BSF_GdEd },
|
||||
/* 0F BD /dr */ { 0, BX_IA_BSR_GdEd },
|
||||
/* 0F BC /dr */ { 0, BX_IA_BSF_GdEdR },
|
||||
/* 0F BD /dr */ { 0, BX_IA_BSR_GdEdR },
|
||||
/* 0F BE /dr */ { 0, BX_IA_MOVSX_GdEbR },
|
||||
/* 0F BF /dr */ { 0, BX_IA_MOVSX_GdEwR },
|
||||
/* 0F C0 /dr */ { 0, BX_IA_XADD_EbGbR },
|
||||
@ -1823,8 +1823,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
|
||||
/* 0F B9 /wm */ { BxTraceEnd, BX_IA_UD2B },
|
||||
/* 0F BA /wm */ { BxGroup8, BX_IA_ERROR, BxOpcodeInfoG8EwIbM },
|
||||
/* 0F BB /wm */ { BxLockable, BX_IA_BTC_EwGwM },
|
||||
/* 0F BC /wm */ { 0, BX_IA_BSF_GwEw },
|
||||
/* 0F BD /wm */ { 0, BX_IA_BSR_GwEw },
|
||||
/* 0F BC /wm */ { 0, BX_IA_BSF_GwEwM },
|
||||
/* 0F BD /wm */ { 0, BX_IA_BSR_GwEwM },
|
||||
/* 0F BE /wm */ { 0, BX_IA_MOVSX_GwEbM },
|
||||
/* 0F BF /wm */ { 0, BX_IA_MOV_GwEwM }, // MOVSX_GwEw
|
||||
/* 0F C0 /wm */ { BxLockable, BX_IA_XADD_EbGbM },
|
||||
@ -2386,8 +2386,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
|
||||
/* 0F B9 /dm */ { BxTraceEnd, BX_IA_UD2B },
|
||||
/* 0F BA /dm */ { BxGroup8, BX_IA_ERROR, BxOpcodeInfoG8EdIbM },
|
||||
/* 0F BB /dm */ { BxLockable, BX_IA_BTC_EdGdM },
|
||||
/* 0F BC /dm */ { 0, BX_IA_BSF_GdEd },
|
||||
/* 0F BD /dm */ { 0, BX_IA_BSR_GdEd },
|
||||
/* 0F BC /dm */ { 0, BX_IA_BSF_GdEdM },
|
||||
/* 0F BD /dm */ { 0, BX_IA_BSR_GdEdM },
|
||||
/* 0F BE /dm */ { 0, BX_IA_MOVSX_GdEbM },
|
||||
/* 0F BF /dm */ { 0, BX_IA_MOVSX_GdEwM },
|
||||
/* 0F C0 /dm */ { BxLockable, BX_IA_XADD_EbGbM },
|
||||
@ -2456,6 +2456,14 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
|
||||
/* 0F FF /dm */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
enum {
|
||||
BX_RESOLVE16_DISPLACEMENT,
|
||||
BX_RESOLVE16_BASE_INDEX,
|
||||
BX_RESOLVE32_BASE,
|
||||
BX_RESOLVE32_BASE_INDEX,
|
||||
BX_RESOLVE_NONE
|
||||
};
|
||||
|
||||
unsigned BX_CPP_AttrRegparmN(3)
|
||||
BX_CPU_C::fetchDecode32(const Bit8u *iptr, bxInstruction_c *i, unsigned remainingInPage)
|
||||
{
|
||||
@ -2464,7 +2472,7 @@ BX_CPU_C::fetchDecode32(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
|
||||
|
||||
bx_bool is_32, lock=0;
|
||||
unsigned b1, b2, ilen=0, attr, os_32, ia_opcode = 0;
|
||||
unsigned imm_mode, offset;
|
||||
unsigned imm_mode, offset, resolve = BX_RESOLVE_NONE;
|
||||
unsigned rm = 0, mod=0, nnn=0;
|
||||
|
||||
#define SSE_PREFIX_NONE 0
|
||||
@ -2594,6 +2602,7 @@ fetch_b1:
|
||||
|
||||
if (i->as32L()) {
|
||||
// 32-bit addressing modes; note that mod==11b handled above
|
||||
resolve = BX_RESOLVE32_BASE;
|
||||
i->ResolveModrm = &BX_CPU_C::BxResolve32Base;
|
||||
if (rm != 4) { // no s-i-b byte
|
||||
if (mod == 0x00) { // mod == 00b
|
||||
@ -2642,6 +2651,7 @@ get_8bit_displ:
|
||||
i->setSibScale(scale);
|
||||
i->setSibBase(base);
|
||||
if (index != 4) {
|
||||
resolve = BX_RESOLVE32_BASE_INDEX;
|
||||
i->ResolveModrm = &BX_CPU_C::BxResolve32BaseIndex;
|
||||
i->setSibIndex(index);
|
||||
}
|
||||
@ -2665,6 +2675,7 @@ get_8bit_displ:
|
||||
}
|
||||
else {
|
||||
// 16-bit addressing modes, mod==11b handled above
|
||||
resolve = BX_RESOLVE16_BASE_INDEX;
|
||||
i->ResolveModrm = &BX_CPU_C::BxResolve16BaseIndex;
|
||||
i->setSibBase(Resolve16BaseReg[rm]);
|
||||
i->setSibIndex(Resolve16IndexReg[rm]);
|
||||
@ -2672,6 +2683,7 @@ get_8bit_displ:
|
||||
if (BX_NULL_SEG_REG(i->seg()))
|
||||
i->setSeg(sreg_mod00_rm16[rm]);
|
||||
if (rm == 0x06) {
|
||||
resolve = BX_RESOLVE16_DISPLACEMENT;
|
||||
i->ResolveModrm = &BX_CPU_C::BxResolve16Disp;
|
||||
get_16bit_displ:
|
||||
if ((ilen+1) < remain) {
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: fetchdecode64.cc,v 1.206 2008-08-09 21:05:05 sshwarts Exp $
|
||||
// $Id: fetchdecode64.cc,v 1.207 2008-08-10 19:34:28 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -638,8 +638,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F B9 /wr */ { BxTraceEnd, BX_IA_UD2B },
|
||||
/* 0F BA /wr */ { BxGroup8, BX_IA_ERROR, BxOpcodeInfoG8EwIbR },
|
||||
/* 0F BB /wr */ { 0, BX_IA_BTC_EwGwR },
|
||||
/* 0F BC /wr */ { 0, BX_IA_BSF_GwEw },
|
||||
/* 0F BD /wr */ { 0, BX_IA_BSR_GwEw },
|
||||
/* 0F BC /wr */ { 0, BX_IA_BSF_GwEwR },
|
||||
/* 0F BD /wr */ { 0, BX_IA_BSR_GwEwR },
|
||||
/* 0F BE /wr */ { 0, BX_IA_MOVSX_GwEbR },
|
||||
/* 0F BF /wr */ { 0, BX_IA_MOV_GwEwR }, // MOVSX_GwEw
|
||||
/* 0F C0 /wr */ { 0, BX_IA_XADD_EbGbR },
|
||||
@ -1165,8 +1165,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F B9 /dr */ { BxTraceEnd, BX_IA_UD2B },
|
||||
/* 0F BA /dr */ { BxGroup8, BX_IA_ERROR, BxOpcodeInfoG8EdIbR },
|
||||
/* 0F BB /dr */ { 0, BX_IA_BTC_EdGdR },
|
||||
/* 0F BC /dr */ { 0, BX_IA_BSF_GdEd },
|
||||
/* 0F BD /dr */ { 0, BX_IA_BSR_GdEd },
|
||||
/* 0F BC /dr */ { 0, BX_IA_BSF_GdEdR },
|
||||
/* 0F BD /dr */ { 0, BX_IA_BSR_GdEdR },
|
||||
/* 0F BE /dr */ { 0, BX_IA_MOVSX_GdEbR },
|
||||
/* 0F BF /dr */ { 0, BX_IA_MOVSX_GdEwR },
|
||||
/* 0F C0 /dr */ { 0, BX_IA_XADD_EbGbR },
|
||||
@ -1692,8 +1692,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F B9 /qr */ { BxTraceEnd, BX_IA_UD2B },
|
||||
/* 0F BA /qr */ { BxGroup8, BX_IA_ERROR, BxOpcodeInfo64G8EqIbR },
|
||||
/* 0F BB /qr */ { 0, BX_IA_BTC_EqGqR },
|
||||
/* 0F BC /qr */ { 0, BX_IA_BSF_GqEq },
|
||||
/* 0F BD /qr */ { 0, BX_IA_BSR_GqEq },
|
||||
/* 0F BC /qr */ { 0, BX_IA_BSF_GqEqR },
|
||||
/* 0F BD /qr */ { 0, BX_IA_BSR_GqEqR },
|
||||
/* 0F BE /qr */ { 0, BX_IA_MOVSX_GqEbR },
|
||||
/* 0F BF /qr */ { 0, BX_IA_MOVSX_GqEwR },
|
||||
/* 0F C0 /qr */ { 0, BX_IA_XADD_EbGbR },
|
||||
@ -2225,8 +2225,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F B9 /wm */ { BxTraceEnd, BX_IA_UD2B },
|
||||
/* 0F BA /wm */ { BxGroup8, BX_IA_ERROR, BxOpcodeInfoG8EwIbM },
|
||||
/* 0F BB /wm */ { BxLockable, BX_IA_BTC_EwGwM },
|
||||
/* 0F BC /wm */ { 0, BX_IA_BSF_GwEw },
|
||||
/* 0F BD /wm */ { 0, BX_IA_BSR_GwEw },
|
||||
/* 0F BC /wm */ { 0, BX_IA_BSF_GwEwM },
|
||||
/* 0F BD /wm */ { 0, BX_IA_BSR_GwEwM },
|
||||
/* 0F BE /wm */ { 0, BX_IA_MOVSX_GwEbM },
|
||||
/* 0F BF /wm */ { 0, BX_IA_MOV_GwEwM }, // MOVSX_GwEw
|
||||
/* 0F C0 /wm */ { BxLockable, BX_IA_XADD_EbGbM },
|
||||
@ -2752,8 +2752,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F B9 /dm */ { BxTraceEnd, BX_IA_UD2B },
|
||||
/* 0F BA /dm */ { BxGroup8, BX_IA_ERROR, BxOpcodeInfoG8EdIbM },
|
||||
/* 0F BB /dm */ { BxLockable, BX_IA_BTC_EdGdM },
|
||||
/* 0F BC /dm */ { 0, BX_IA_BSF_GdEd },
|
||||
/* 0F BD /dm */ { 0, BX_IA_BSR_GdEd },
|
||||
/* 0F BC /dm */ { 0, BX_IA_BSF_GdEdM },
|
||||
/* 0F BD /dm */ { 0, BX_IA_BSR_GdEdM },
|
||||
/* 0F BE /dm */ { 0, BX_IA_MOVSX_GdEbM },
|
||||
/* 0F BF /dm */ { 0, BX_IA_MOVSX_GdEwM },
|
||||
/* 0F C0 /dm */ { BxLockable, BX_IA_XADD_EbGbM },
|
||||
@ -3279,8 +3279,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F B9 /qm */ { BxTraceEnd, BX_IA_UD2B },
|
||||
/* 0F BA /qm */ { BxGroup8, BX_IA_ERROR, BxOpcodeInfo64G8EqIbM },
|
||||
/* 0F BB /qm */ { BxLockable, BX_IA_BTC_EqGqM },
|
||||
/* 0F BC /qm */ { 0, BX_IA_BSF_GqEq },
|
||||
/* 0F BD /qm */ { 0, BX_IA_BSR_GqEq },
|
||||
/* 0F BC /qm */ { 0, BX_IA_BSF_GqEqM },
|
||||
/* 0F BD /qm */ { 0, BX_IA_BSR_GqEqM },
|
||||
/* 0F BE /qm */ { 0, BX_IA_MOVSX_GqEbM },
|
||||
/* 0F BF /qm */ { 0, BX_IA_MOVSX_GqEwM },
|
||||
/* 0F C0 /qm */ { BxLockable, BX_IA_XADD_EbGbM },
|
||||
@ -3349,6 +3349,14 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F FF /qm */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
enum {
|
||||
BX_RESOLVE32_BASE,
|
||||
BX_RESOLVE32_BASE_INDEX,
|
||||
BX_RESOLVE64_BASE,
|
||||
BX_RESOLVE64_BASE_INDEX,
|
||||
BX_RESOLVE_NONE
|
||||
};
|
||||
|
||||
unsigned BX_CPP_AttrRegparmN(3)
|
||||
BX_CPU_C::fetchDecode64(const Bit8u *iptr, bxInstruction_c *i, unsigned remainingInPage)
|
||||
{
|
||||
@ -3357,7 +3365,7 @@ BX_CPU_C::fetchDecode64(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
|
||||
|
||||
unsigned b1, b2, ilen=0, attr, lock=0, ia_opcode = 0;
|
||||
unsigned imm_mode, offset = 512, rex_r = 0, rex_x = 0, rex_b = 0;
|
||||
unsigned rm = 0, mod = 0, nnn = 0;
|
||||
unsigned rm = 0, mod = 0, nnn = 0, resolve = BX_RESOLVE_NONE;
|
||||
#define SSE_PREFIX_NONE 0
|
||||
#define SSE_PREFIX_66 1
|
||||
#define SSE_PREFIX_F2 2
|
||||
@ -3521,6 +3529,7 @@ fetch_b1:
|
||||
|
||||
if (i->as64L()) {
|
||||
// 64-bit addressing modes; note that mod==11b handled above
|
||||
resolve = BX_RESOLVE64_BASE;
|
||||
i->ResolveModrm = &BX_CPU_C::BxResolve64Base;
|
||||
if ((rm & 0x7) != 4) { // no s-i-b byte
|
||||
if (mod == 0x00) { // mod == 00b
|
||||
@ -3570,6 +3579,7 @@ get_8bit_displ:
|
||||
i->setSibScale(scale);
|
||||
i->setSibBase(base);
|
||||
if (index != 4) {
|
||||
resolve = BX_RESOLVE64_BASE_INDEX;
|
||||
i->ResolveModrm = &BX_CPU_C::BxResolve64BaseIndex;
|
||||
i->setSibIndex(index);
|
||||
}
|
||||
@ -3593,6 +3603,7 @@ get_8bit_displ:
|
||||
}
|
||||
else {
|
||||
// 32-bit addressing modes; note that mod==11b handled above
|
||||
resolve = BX_RESOLVE32_BASE;
|
||||
i->ResolveModrm = &BX_CPU_C::BxResolve32Base;
|
||||
if ((rm & 0x7) != 4) { // no s-i-b byte
|
||||
if (mod == 0x00) { // mod == 00b
|
||||
@ -3627,6 +3638,7 @@ get_8bit_displ:
|
||||
i->setSibBase(base);
|
||||
i->setSibScale(scale);
|
||||
if (index != 4) {
|
||||
resolve = BX_RESOLVE32_BASE_INDEX;
|
||||
i->ResolveModrm = &BX_CPU_C::BxResolve32BaseIndex;
|
||||
i->setSibIndex(index);
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: ia_opcodes.h,v 1.13 2008-08-09 21:05:06 sshwarts Exp $
|
||||
// $Id: ia_opcodes.h,v 1.14 2008-08-10 19:34:28 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2008 Stanislav Shwartsman
|
||||
@ -95,10 +95,14 @@ bx_define_opcode(BX_IA_AND_GwEwR, &BX_CPU_C::AND_GwEwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_ARPL_EwGw, &BX_CPU_C::ARPL_EwGw, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BOUND_GdMa, &BX_CPU_C::BOUND_GdMa, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BOUND_GwMa, &BX_CPU_C::BOUND_GwMa, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSF_GdEd, &BX_CPU_C::BSF_GdEd, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSF_GwEw, &BX_CPU_C::BSF_GwEw, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSR_GdEd, &BX_CPU_C::BSR_GdEd, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSR_GwEw, &BX_CPU_C::BSR_GwEw, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSF_GdEdR, &BX_CPU_C::BSF_GdEdR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSF_GdEdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::BSF_GdEdR, 0)
|
||||
bx_define_opcode(BX_IA_BSF_GwEwR, &BX_CPU_C::BSF_GwEwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSF_GwEwM, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::BSF_GwEwR, 0)
|
||||
bx_define_opcode(BX_IA_BSR_GdEdR, &BX_CPU_C::BSR_GdEdR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSR_GdEdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::BSR_GdEdR, 0)
|
||||
bx_define_opcode(BX_IA_BSR_GwEwR, &BX_CPU_C::BSR_GwEwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSR_GwEwM, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::BSR_GwEwR, 0)
|
||||
bx_define_opcode(BX_IA_BSWAP_ERX, &BX_CPU_C::BSWAP_ERX, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BT_EdGdM, &BX_CPU_C::BT_EdGdM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BT_EdGdR, &BX_CPU_C::BT_EdGdR, NULL, 0)
|
||||
@ -133,9 +137,9 @@ bx_define_opcode(BX_IA_BTS_EwGwR, &BX_CPU_C::BTS_EwGwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BTS_EwIbM, &BX_CPU_C::BTS_EwIbM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BTS_EwIbR, &BX_CPU_C::BTS_EwIbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_ERROR, &BX_CPU_C::BxError, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CALL_EdM, &BX_CPU_C::CALL_EdM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CALL_EdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::CALL_EdR, 0)
|
||||
bx_define_opcode(BX_IA_CALL_EdR, &BX_CPU_C::CALL_EdR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CALL_EwM, &BX_CPU_C::CALL_EwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CALL_EwM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::CALL_EwR, 0)
|
||||
bx_define_opcode(BX_IA_CALL_EwR, &BX_CPU_C::CALL_EwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CALL_Jd, &BX_CPU_C::CALL_Jd, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CALL_Jw, &BX_CPU_C::CALL_Jw, NULL, 0)
|
||||
@ -305,9 +309,9 @@ bx_define_opcode(BX_IA_JL_Jw, &BX_CPU_C::JL_Jw, NULL, 0)
|
||||
bx_define_opcode(BX_IA_JLE_Jd, &BX_CPU_C::JLE_Jd, NULL, 0)
|
||||
bx_define_opcode(BX_IA_JLE_Jw, &BX_CPU_C::JLE_Jw, NULL, 0)
|
||||
bx_define_opcode(BX_IA_JMP_Ap, &BX_CPU_C::JMP_Ap, NULL, 0)
|
||||
bx_define_opcode(BX_IA_JMP_EdM, &BX_CPU_C::JMP_EdM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_JMP_EdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::JMP_EdR, 0)
|
||||
bx_define_opcode(BX_IA_JMP_EdR, &BX_CPU_C::JMP_EdR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_JMP_EwM, &BX_CPU_C::JMP_EwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_JMP_EwM, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::JMP_EwR, 0)
|
||||
bx_define_opcode(BX_IA_JMP_EwR, &BX_CPU_C::JMP_EwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_JMP_Jd, &BX_CPU_C::JMP_Jd, NULL, 0)
|
||||
bx_define_opcode(BX_IA_JMP_Jw, &BX_CPU_C::JMP_Jw, NULL, 0)
|
||||
@ -1408,8 +1412,10 @@ bx_define_opcode(BX_IA_MOVZX_GqEwR, &BX_CPU_C::MOVZX_GqEwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_MOVSX_GqEbR, &BX_CPU_C::MOVSX_GqEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_MOVSX_GqEwR, &BX_CPU_C::MOVSX_GqEwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_MOVSX_GqEdR, &BX_CPU_C::MOVSX_GqEdR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSF_GqEq, &BX_CPU_C::BSF_GqEq, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSR_GqEq, &BX_CPU_C::BSR_GqEq, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSF_GqEqR, &BX_CPU_C::BSF_GqEqR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSF_GqEqM, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::BSF_GqEqR, 0)
|
||||
bx_define_opcode(BX_IA_BSR_GqEqR, &BX_CPU_C::BSR_GqEqR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BSR_GqEqM, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::BSR_GqEqR, 0)
|
||||
bx_define_opcode(BX_IA_BT_EqGqM, &BX_CPU_C::BT_EqGqM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BTS_EqGqM, &BX_CPU_C::BTS_EqGqM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_BTR_EqGqM, &BX_CPU_C::BTR_EqGqM, NULL, 0)
|
||||
@ -1455,10 +1461,10 @@ bx_define_opcode(BX_IA_INC_EqM, &BX_CPU_C::INC_EqM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_DEC_EqM, &BX_CPU_C::DEC_EqM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_INC_EqR, &BX_CPU_C::INC_EqR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_DEC_EqR, &BX_CPU_C::DEC_EqR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CALL_EqM, &BX_CPU_C::CALL_EqM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CALL_EqM, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::CALL_EqR, 0)
|
||||
bx_define_opcode(BX_IA_CALL_EqR, &BX_CPU_C::CALL_EqR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CALL64_Ep, &BX_CPU_C::CALL64_Ep, NULL, 0)
|
||||
bx_define_opcode(BX_IA_JMP_EqM, &BX_CPU_C::JMP_EqM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_JMP_EqM, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::JMP_EqR, 0)
|
||||
bx_define_opcode(BX_IA_JMP_EqR, &BX_CPU_C::JMP_EqR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_JMP64_Ep, &BX_CPU_C::JMP64_Ep, NULL, 0)
|
||||
bx_define_opcode(BX_IA_PUSHF_Fq, &BX_CPU_C::PUSHF_Fq, NULL, 0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user