Support for Intel LSS/LFS/LGS in 64-bit mode
TODO: have both AMD and Intelk versions
This commit is contained in:
Stanislav Shwartsman
parent
bb27085003
commit
e26609fa97
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.315 2007-03-22 22:51:41 sshwarts Exp $
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// $Id: cpu.h,v 1.316 2007-04-09 20:28:14 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1614,11 +1614,16 @@ public: // for now...
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BX_SMF void BTC_EwIb(bxInstruction_c *);
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BX_SMF void BTC_EdIb(bxInstruction_c *);
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BX_SMF void LES_GvMp(bxInstruction_c *);
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BX_SMF void LDS_GvMp(bxInstruction_c *);
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BX_SMF void LSS_GvMp(bxInstruction_c *);
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BX_SMF void LFS_GvMp(bxInstruction_c *);
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BX_SMF void LGS_GvMp(bxInstruction_c *);
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BX_SMF void LES_GwMp(bxInstruction_c *);
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BX_SMF void LDS_GwMp(bxInstruction_c *);
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BX_SMF void LSS_GwMp(bxInstruction_c *);
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BX_SMF void LFS_GwMp(bxInstruction_c *);
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BX_SMF void LGS_GwMp(bxInstruction_c *);
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BX_SMF void LES_GdMp(bxInstruction_c *);
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BX_SMF void LDS_GdMp(bxInstruction_c *);
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BX_SMF void LSS_GdMp(bxInstruction_c *);
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BX_SMF void LFS_GdMp(bxInstruction_c *);
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BX_SMF void LGS_GdMp(bxInstruction_c *);
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BX_SMF void MOVZX_GdEb(bxInstruction_c *);
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BX_SMF void MOVZX_GwEb(bxInstruction_c *);
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@ -2414,14 +2419,13 @@ public: // for now...
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BX_SMF void CALL_Aq(bxInstruction_c *);
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BX_SMF void JMP_Jq(bxInstruction_c *);
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BX_SMF void JCC_Jq(bxInstruction_c *);
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BX_SMF void MOV_CqRq(bxInstruction_c *);
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BX_SMF void MOV_DqRq(bxInstruction_c *);
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BX_SMF void MOV_RqCq(bxInstruction_c *);
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BX_SMF void MOV_RqDq(bxInstruction_c *);
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BX_SMF void JCC_Jq(bxInstruction_c *);
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BX_SMF void SHLD_EqGq(bxInstruction_c *);
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BX_SMF void SHRD_EqGq(bxInstruction_c *);
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BX_SMF void IMUL_GqEq(bxInstruction_c *);
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@ -2503,6 +2507,10 @@ public: // for now...
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BX_SMF void PUSH64_GS(bxInstruction_c *);
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BX_SMF void POP64_GS(bxInstruction_c *);
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BX_SMF void LSS_GqMp(bxInstruction_c *);
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BX_SMF void LFS_GqMp(bxInstruction_c *);
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BX_SMF void LGS_GqMp(bxInstruction_c *);
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BX_SMF void SGDT64_Ms(bxInstruction_c *);
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BX_SMF void SIDT64_Ms(bxInstruction_c *);
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BX_SMF void LGDT64_Ms(bxInstruction_c *);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.104 2007-03-23 14:35:50 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.105 2007-04-09 20:28:14 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -615,8 +615,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* C1 */ { BxAnother | BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfoG2Ew },
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/* C2 */ { BxImmediate_Iw, &BX_CPU_C::RETnear16_Iw },
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/* C3 */ { 0, &BX_CPU_C::RETnear16 },
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/* C4 */ { BxAnother, &BX_CPU_C::LES_GvMp },
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/* C5 */ { BxAnother, &BX_CPU_C::LDS_GvMp },
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/* C4 */ { BxAnother, &BX_CPU_C::LES_GwMp },
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/* C5 */ { BxAnother, &BX_CPU_C::LDS_GwMp },
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/* C6 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::MOV_EbIb },
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/* C7 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::MOV_EwIw },
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/* C8 */ { BxImmediate_IwIb, &BX_CPU_C::ENTER_IwIb },
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@ -897,10 +897,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GwEw },
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/* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
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/* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EwGw },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GwMp },
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/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EwGw },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GwMp },
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GwMp },
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/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GwEb },
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/* 0F B7 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GwEw }, // MOVZX_GwEw
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/* 0F B8 */ { 0, &BX_CPU_C::BxError },
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@ -1173,8 +1173,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* C1 */ { BxAnother | BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfoG2Ed },
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/* C2 */ { BxImmediate_Iw, &BX_CPU_C::RETnear32_Iw },
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/* C3 */ { 0, &BX_CPU_C::RETnear32 },
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/* C4 */ { BxAnother, &BX_CPU_C::LES_GvMp },
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/* C5 */ { BxAnother, &BX_CPU_C::LDS_GvMp },
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/* C4 */ { BxAnother, &BX_CPU_C::LES_GdMp },
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/* C5 */ { BxAnother, &BX_CPU_C::LDS_GdMp },
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/* C6 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::MOV_EbIb },
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/* C7 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::MOV_EdId },
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/* C8 */ { BxImmediate_IwIb, &BX_CPU_C::ENTER_IwIb },
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@ -1455,10 +1455,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GdEd },
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/* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
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/* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EdGd },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GdMp },
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/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EdGd },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GdMp },
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GdMp },
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/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GdEb },
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/* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GdEw },
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/* 0F B8 */ { 0, &BX_CPU_C::BxError },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode64.cc,v 1.108 2007-04-02 10:46:32 sshwarts Exp $
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// $Id: fetchdecode64.cc,v 1.109 2007-04-09 20:28:15 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1016,10 +1016,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
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/* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GwEw },
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/* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
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/* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EwGw },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GwMp },
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/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EwGw },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GwMp },
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GwMp },
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/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GwEb },
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/* 0F B7 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GwEw }, // MOVZX_GwEw
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/* 0F B8 */ { 0, &BX_CPU_C::BxError },
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@ -1545,10 +1545,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
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/* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GdEd },
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/* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
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/* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EdGd },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GdMp },
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/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EdGd },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GdMp },
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GdMp },
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/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GdEb },
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/* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GdEw },
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/* 0F B8 */ { 0, &BX_CPU_C::BxError },
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@ -2074,10 +2074,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
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/* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GqEq },
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/* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
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/* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EqGq },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
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/* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GqMp }, // TODO: LSS_GdMp for AMD CPU
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/* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EqGq },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
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/* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GqMp }, // TODO: LFS_GdMp for AMD CPU
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/* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GqMp }, // TODO: LGS_GdMp for AMD CPU
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/* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GqEb },
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/* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GqEw },
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/* 0F B8 */ { 0, &BX_CPU_C::BxError },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: segment_ctrl.cc,v 1.14 2006-03-06 22:03:02 sshwarts Exp $
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// $Id: segment_ctrl.cc,v 1.15 2007-04-09 20:28:15 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -33,165 +33,237 @@
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#define LOG_THIS BX_CPU_THIS_PTR
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void BX_CPU_C::LES_GvMp(bxInstruction_c *i)
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void BX_CPU_C::LES_GwMp(bxInstruction_c *i)
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{
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if (i->modC0()) {
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BX_DEBUG(("invalid use of LES, must use memory reference!"));
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BX_DEBUG(("LES_GwMp: invalid use of LES, must be memory reference!"));
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UndefinedOpcode(i);
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}
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#if BX_CPU_LEVEL > 2
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if (i->os32L()) {
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Bit16u es;
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Bit32u reg_32;
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Bit16u reg_16, es;
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read_virtual_dword(i->seg(), RMAddr(i), ®_32);
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read_virtual_word(i->seg(), RMAddr(i) + 4, &es);
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read_virtual_word(i->seg(), RMAddr(i), ®_16);
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read_virtual_word(i->seg(), RMAddr(i) + 2, &es);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
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BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
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}
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else
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#endif /* BX_CPU_LEVEL > 2 */
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{ /* 16 bit mode */
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Bit16u reg_16, es;
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read_virtual_word(i->seg(), RMAddr(i), ®_16);
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read_virtual_word(i->seg(), RMAddr(i) + 2, &es);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
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BX_WRITE_16BIT_REG(i->nnn(), reg_16);
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}
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BX_WRITE_16BIT_REG(i->nnn(), reg_16);
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}
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void BX_CPU_C::LDS_GvMp(bxInstruction_c *i)
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void BX_CPU_C::LES_GdMp(bxInstruction_c *i)
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{
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if (i->modC0()) {
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BX_DEBUG(("invalid use of LDS, must use memory reference!"));
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BX_DEBUG(("LES_GdMp: invalid use of LES, must be memory reference!"));
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UndefinedOpcode(i);
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}
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#if BX_CPU_LEVEL > 2
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if (i->os32L()) {
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Bit16u ds;
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Bit32u reg_32;
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Bit16u es;
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Bit32u reg_32;
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read_virtual_dword(i->seg(), RMAddr(i), ®_32);
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read_virtual_word(i->seg(), RMAddr(i) + 4, &ds);
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read_virtual_dword(i->seg(), RMAddr(i), ®_32);
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read_virtual_word(i->seg(), RMAddr(i) + 4, &es);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
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BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
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}
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else
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#endif /* BX_CPU_LEVEL > 2 */
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{ /* 16 bit mode */
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Bit16u reg_16, ds;
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read_virtual_word(i->seg(), RMAddr(i), ®_16);
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read_virtual_word(i->seg(), RMAddr(i) + 2, &ds);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
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BX_WRITE_16BIT_REG(i->nnn(), reg_16);
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}
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BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
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}
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#if BX_CPU_LEVEL >= 3
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void BX_CPU_C::LFS_GvMp(bxInstruction_c *i)
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void BX_CPU_C::LDS_GwMp(bxInstruction_c *i)
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{
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if (i->modC0()) {
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BX_DEBUG(("invalid use of LFS, must use memory reference!"));
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BX_DEBUG(("LDS_GwMp: invalid use of LDS, must be memory reference!"));
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UndefinedOpcode(i);
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}
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if (i->os32L()) {
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Bit32u reg_32;
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Bit16u fs;
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Bit16u reg_16, ds;
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read_virtual_dword(i->seg(), RMAddr(i), ®_32);
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read_virtual_word(i->seg(), RMAddr(i) + 4, &fs);
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read_virtual_word(i->seg(), RMAddr(i), ®_16);
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read_virtual_word(i->seg(), RMAddr(i) + 2, &ds);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
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BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
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}
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else { /* 16 bit operand size */
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Bit16u reg_16;
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Bit16u fs;
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read_virtual_word(i->seg(), RMAddr(i), ®_16);
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read_virtual_word(i->seg(), RMAddr(i) + 2, &fs);
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
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BX_WRITE_16BIT_REG(i->nnn(), reg_16);
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}
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BX_WRITE_16BIT_REG(i->nnn(), reg_16);
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}
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void BX_CPU_C::LGS_GvMp(bxInstruction_c *i)
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void BX_CPU_C::LDS_GdMp(bxInstruction_c *i)
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{
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if (i->modC0()) {
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BX_DEBUG(("invalid use of LGS, must use memory reference!"));
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BX_DEBUG(("LDS_GdMp: invalid use of LDS, must be memory reference!"));
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UndefinedOpcode(i);
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}
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if (i->os32L()) {
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Bit32u reg_32;
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Bit16u gs;
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Bit16u ds;
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Bit32u reg_32;
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read_virtual_dword(i->seg(), RMAddr(i), ®_32);
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read_virtual_word(i->seg(), RMAddr(i) + 4, &gs);
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read_virtual_dword(i->seg(), RMAddr(i), ®_32);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 4, &ds);
|
||||
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
|
||||
|
||||
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
|
||||
}
|
||||
else { /* 16 bit operand size */
|
||||
Bit16u reg_16;
|
||||
Bit16u gs;
|
||||
|
||||
read_virtual_word(i->seg(), RMAddr(i), ®_16);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 2, &gs);
|
||||
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
|
||||
|
||||
BX_WRITE_16BIT_REG(i->nnn(), reg_16);
|
||||
}
|
||||
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
|
||||
}
|
||||
|
||||
void BX_CPU_C::LSS_GvMp(bxInstruction_c *i)
|
||||
void BX_CPU_C::LFS_GwMp(bxInstruction_c *i)
|
||||
{
|
||||
if (i->modC0()) {
|
||||
BX_DEBUG(("invalid use of LSS, must use memory reference!"));
|
||||
BX_DEBUG(("LFS_GwMp: invalid use of LFS, must be memory reference!"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
if (i->os32L()) {
|
||||
Bit32u reg_32;
|
||||
Bit16u ss_raw;
|
||||
Bit16u reg_16, fs;
|
||||
|
||||
read_virtual_dword(i->seg(), RMAddr(i), ®_32);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 4, &ss_raw);
|
||||
read_virtual_word(i->seg(), RMAddr(i), ®_16);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 2, &fs);
|
||||
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss_raw);
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
|
||||
|
||||
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
|
||||
}
|
||||
else { /* 16 bit operand size */
|
||||
Bit16u reg_16;
|
||||
Bit16u ss_raw;
|
||||
|
||||
read_virtual_word(i->seg(), RMAddr(i), ®_16);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 2, &ss_raw);
|
||||
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss_raw);
|
||||
|
||||
BX_WRITE_16BIT_REG(i->nnn(), reg_16);
|
||||
}
|
||||
BX_WRITE_16BIT_REG(i->nnn(), reg_16);
|
||||
}
|
||||
|
||||
void BX_CPU_C::LFS_GdMp(bxInstruction_c *i)
|
||||
{
|
||||
if (i->modC0()) {
|
||||
BX_DEBUG(("LFS_GdMp: invalid use of LFS, must be memory reference!"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
Bit32u reg_32;
|
||||
Bit16u fs;
|
||||
|
||||
read_virtual_dword(i->seg(), RMAddr(i), ®_32);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 4, &fs);
|
||||
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
|
||||
|
||||
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
void BX_CPU_C::LFS_GqMp(bxInstruction_c *i)
|
||||
{
|
||||
if (i->modC0()) {
|
||||
BX_DEBUG(("LFS_GqMp: invalid use of LFS, must be memory reference!"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
Bit64u reg_64;
|
||||
Bit16u fs;
|
||||
|
||||
read_virtual_qword(i->seg(), RMAddr(i), ®_64);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 8, &fs);
|
||||
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
|
||||
|
||||
BX_WRITE_64BIT_REG(i->nnn(), reg_64);
|
||||
}
|
||||
#endif
|
||||
|
||||
void BX_CPU_C::LGS_GwMp(bxInstruction_c *i)
|
||||
{
|
||||
if (i->modC0()) {
|
||||
BX_DEBUG(("LGS_GwMp: invalid use of LGS, must be memory reference!"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
Bit16u reg_16, gs;
|
||||
|
||||
read_virtual_word(i->seg(), RMAddr(i), ®_16);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 2, &gs);
|
||||
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
|
||||
|
||||
BX_WRITE_16BIT_REG(i->nnn(), reg_16);
|
||||
}
|
||||
|
||||
void BX_CPU_C::LGS_GdMp(bxInstruction_c *i)
|
||||
{
|
||||
if (i->modC0()) {
|
||||
BX_DEBUG(("LGS_GdMp: invalid use of LGS, must be memory reference!"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
Bit32u reg_32;
|
||||
Bit16u gs;
|
||||
|
||||
read_virtual_dword(i->seg(), RMAddr(i), ®_32);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 4, &gs);
|
||||
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
|
||||
|
||||
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
void BX_CPU_C::LGS_GqMp(bxInstruction_c *i)
|
||||
{
|
||||
if (i->modC0()) {
|
||||
BX_DEBUG(("LGS_GqMp: invalid use of LGS, must be memory reference!"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
Bit64u reg_64;
|
||||
Bit16u gs;
|
||||
|
||||
read_virtual_qword(i->seg(), RMAddr(i), ®_64);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 8, &gs);
|
||||
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
|
||||
|
||||
BX_WRITE_64BIT_REG(i->nnn(), reg_64);
|
||||
}
|
||||
#endif
|
||||
|
||||
void BX_CPU_C::LSS_GwMp(bxInstruction_c *i)
|
||||
{
|
||||
if (i->modC0()) {
|
||||
BX_DEBUG(("LSS_GwMp: invalid use of LSS, must be memory reference!"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
Bit16u reg_16, ss;
|
||||
|
||||
read_virtual_word(i->seg(), RMAddr(i), ®_16);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 2, &ss);
|
||||
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
|
||||
|
||||
BX_WRITE_16BIT_REG(i->nnn(), reg_16);
|
||||
}
|
||||
|
||||
void BX_CPU_C::LSS_GdMp(bxInstruction_c *i)
|
||||
{
|
||||
if (i->modC0()) {
|
||||
BX_DEBUG(("LSS_GdMp: invalid use of LSS, must be memory reference!"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
Bit32u reg_32;
|
||||
Bit16u ss;
|
||||
|
||||
read_virtual_dword(i->seg(), RMAddr(i), ®_32);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 4, &ss);
|
||||
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
|
||||
|
||||
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
void BX_CPU_C::LSS_GqMp(bxInstruction_c *i)
|
||||
{
|
||||
if (i->modC0()) {
|
||||
BX_DEBUG(("LSS_GqMp: invalid use of LSS, must be memory reference!"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
Bit64u reg_64;
|
||||
Bit16u ss;
|
||||
|
||||
read_virtual_qword(i->seg(), RMAddr(i), ®_64);
|
||||
read_virtual_word(i->seg(), RMAddr(i) + 8, &ss);
|
||||
|
||||
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
|
||||
|
||||
BX_WRITE_64BIT_REG(i->nnn(), reg_64);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -43,3 +43,9 @@ TODO (know issues in CPU model):
|
||||
|
||||
[!] CLFLUSH instructin should not crash in case of EXECUTE-ONLY segment
|
||||
access (according to AMD manuals)
|
||||
|
||||
[!] AMD and Intel x86_64 implementations are different.
|
||||
Currently Bochs emulation is according to Intel version.
|
||||
Do we need to support both ?
|
||||
|
||||
[!] More flexible CPUID - vendor and etc
|
||||
|
||||
Loading…
Reference in New Issue
Block a user