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Split more opcodes

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This commit is contained in:
Stanislav Shwartsman 2007-11-18 18:24:46 +00:00
parent 570e87733c
commit cdc9a09090
15 changed files with 906 additions and 737 deletions
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98
bochs/cpu/arith16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith16.cc,v 1.54 2007-11-17 18:08:46 sshwarts Exp $
// $Id: arith16.cc,v 1.55 2007-11-18 18:24:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -373,7 +373,7 @@ void BX_CPU_C::CWD(bxInstruction_c *i)
}
}
void BX_CPU_C::XADD_EwGw(bxInstruction_c *i)
void BX_CPU_C::XADD_EwGwM(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit16u op1_16, op2_16, sum_16;
@ -384,25 +384,42 @@ void BX_CPU_C::XADD_EwGw(bxInstruction_c *i)
* dst <-- tmp | op1 = sum
*/
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op2_16 = BX_READ_16BIT_REG(i->nnn());
sum_16 = op1_16 + op2_16;
write_RMW_virtual_word(sum_16);
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
sum_16 = op1_16 + op2_16;
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->rm(), sum_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
sum_16 = op1_16 + op2_16;
write_RMW_virtual_word(sum_16);
/* and write destination into source */
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
}
/* and write destination into source */
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
SET_FLAGS_OSZAPC_S1_16(op1_16, sum_16, BX_INSTR_ADD16);
#else
BX_INFO(("XADD_EwGw: not supported on < 80486"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::XADD_EwGwR(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit16u op1_16, op2_16, sum_16;
/* XADD dst(r/m), src(r)
* temp <-- src + dst | sum = op2 + op1
* src <-- dst | op2 = op1
* dst <-- tmp | op1 = sum
*/
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
sum_16 = op1_16 + op2_16;
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->rm(), sum_16);
SET_FLAGS_OSZAPC_S1_16(op1_16, sum_16, BX_INSTR_ADD16);
#else
@ -558,32 +575,43 @@ void BX_CPU_C::DEC_EwR(bxInstruction_c *i)
SET_FLAGS_OSZAP_RESULT_16(op1_16, BX_INSTR_DEC16);
}
void BX_CPU_C::CMPXCHG_EwGw(bxInstruction_c *i)
void BX_CPU_C::CMPXCHG_EwGwM(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit16u op1_16, op2_16, diff_16;
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
diff_16 = AX - op1_16;
SET_FLAGS_OSZAPC_16(AX, op1_16, diff_16, BX_INSTR_COMPARE16);
if (diff_16 == 0) { // if accumulator == dest
// dest <-- src
op2_16 = BX_READ_16BIT_REG(i->nnn());
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), op2_16);
}
else {
write_RMW_virtual_word(op2_16);
}
write_RMW_virtual_word(op2_16);
}
else {
// accumulator <-- dest
AX = op1_16;
}
#else
BX_INFO(("CMPXCHG_EwGw: not supported for cpu-level <= 3"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::CMPXCHG_EwGwR(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit16u op1_16, op2_16, diff_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
diff_16 = AX - op1_16;
SET_FLAGS_OSZAPC_16(AX, op1_16, diff_16, BX_INSTR_COMPARE16);
if (diff_16 == 0) { // if accumulator == dest
// dest <-- src
op2_16 = BX_READ_16BIT_REG(i->nnn());
BX_WRITE_16BIT_REG(i->rm(), op2_16);
}
else {
// accumulator <-- dest

97
bochs/cpu/arith32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith32.cc,v 1.60 2007-11-17 18:08:46 sshwarts Exp $
// $Id: arith32.cc,v 1.61 2007-11-18 18:24:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -417,10 +417,9 @@ void BX_CPU_C::CMPXCHG_IBTS(bxInstruction_c *i)
UndefinedOpcode(i);
}
void BX_CPU_C::XADD_EdGd(bxInstruction_c *i)
void BX_CPU_C::XADD_EdGdM(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit32u op1_32, op2_32, sum_32;
/* XADD dst(r/m), src(r)
@ -429,25 +428,42 @@ void BX_CPU_C::XADD_EdGd(bxInstruction_c *i)
* dst <-- tmp | op1 = sum
*/
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op2_32 = BX_READ_32BIT_REG(i->nnn());
sum_32 = op1_32 + op2_32;
write_RMW_virtual_dword(sum_32);
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
sum_32 = op1_32 + op2_32;
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
sum_32 = op1_32 + op2_32;
write_RMW_virtual_dword(sum_32);
/* and write destination into source */
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
}
/* and write destination into source */
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
SET_FLAGS_OSZAPC_S1_32(op1_32, sum_32, BX_INSTR_ADD32);
#else
BX_INFO (("XADD_EdGd not supported for cpulevel <= 3"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::XADD_EdGdR(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit32u op1_32, op2_32, sum_32;
/* XADD dst(r/m), src(r)
* temp <-- src + dst | sum = op2 + op1
* src <-- dst | op2 = op1
* dst <-- tmp | op1 = sum
*/
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
sum_32 = op1_32 + op2_32;
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
SET_FLAGS_OSZAPC_S1_32(op1_32, sum_32, BX_INSTR_ADD32);
#else
@ -612,32 +628,43 @@ void BX_CPU_C::DEC_EdR(bxInstruction_c *i)
SET_FLAGS_OSZAP_RESULT_32(op1_32, BX_INSTR_DEC32);
}
void BX_CPU_C::CMPXCHG_EdGd(bxInstruction_c *i)
void BX_CPU_C::CMPXCHG_EdGdM(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit32u op1_32, op2_32, diff_32;
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
diff_32 = EAX - op1_32;
SET_FLAGS_OSZAPC_32(EAX, op1_32, diff_32, BX_INSTR_COMPARE32);
if (diff_32 == 0) { // if accumulator == dest
// dest <-- src
op2_32 = BX_READ_32BIT_REG(i->nnn());
write_RMW_virtual_dword(op2_32);
}
else {
// accumulator <-- dest
RAX = op1_32;
}
#else
BX_INFO(("CMPXCHG_EdGd: not supported for cpulevel <= 3"));
UndefinedOpcode(i);
#endif
}
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
}
else {
write_RMW_virtual_dword(op2_32);
}
void BX_CPU_C::CMPXCHG_EdGdR(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit32u op1_32, op2_32, diff_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
diff_32 = EAX - op1_32;
SET_FLAGS_OSZAPC_32(EAX, op1_32, diff_32, BX_INSTR_COMPARE32);
if (diff_32 == 0) { // if accumulator == dest
// dest <-- src
op2_32 = BX_READ_32BIT_REG(i->nnn());
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
}
else {
// accumulator <-- dest

233
bochs/cpu/arith64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith64.cc,v 1.37 2007-11-17 23:28:30 sshwarts Exp $
// $Id: arith64.cc,v 1.38 2007-11-18 18:24:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -34,24 +34,27 @@
#if BX_SUPPORT_X86_64
void BX_CPU_C::ADD_EqGq(bxInstruction_c *i)
void BX_CPU_C::ADD_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, sum_64;
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op2_64 = BX_READ_64BIT_REG(i->nnn());
sum_64 = op1_64 + op2_64;
write_RMW_virtual_qword(sum_64);
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
sum_64 = op1_64 + op2_64;
BX_WRITE_64BIT_REG(i->rm(), sum_64);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
sum_64 = op1_64 + op2_64;
write_RMW_virtual_qword(sum_64);
}
SET_FLAGS_OSZAPC_S1_64(op1_64, sum_64, BX_INSTR_ADD64);
}
void BX_CPU_C::ADD_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, sum_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
sum_64 = op1_64 + op2_64;
BX_WRITE_64BIT_REG(i->rm(), sum_64);
SET_FLAGS_OSZAPC_S1_64(op1_64, sum_64, BX_INSTR_ADD64);
}
@ -93,26 +96,31 @@ void BX_CPU_C::ADD_RAXId(bxInstruction_c *i)
SET_FLAGS_OSZAPC_S1_64(op1_64, sum_64, BX_INSTR_ADD64);
}
void BX_CPU_C::ADC_EqGq(bxInstruction_c *i)
void BX_CPU_C::ADC_EqGqM(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
Bit64u op1_64, op2_64, sum_64;
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op2_64 = BX_READ_64BIT_REG(i->nnn());
sum_64 = op1_64 + op2_64 + temp_CF;
write_RMW_virtual_qword(sum_64);
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
sum_64 = op1_64 + op2_64 + temp_CF;
BX_WRITE_64BIT_REG(i->rm(), sum_64);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
sum_64 = op1_64 + op2_64 + temp_CF;
write_RMW_virtual_qword(sum_64);
}
SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD_ADC64(temp_CF));
}
void BX_CPU_C::ADC_EqGqR(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
Bit64u op1_64, op2_64, sum_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
sum_64 = op1_64 + op2_64 + temp_CF;
BX_WRITE_64BIT_REG(i->rm(), sum_64);
SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD_ADC64(temp_CF));
}
@ -158,26 +166,31 @@ void BX_CPU_C::ADC_RAXId(bxInstruction_c *i)
SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD_ADC64(temp_CF));
}
void BX_CPU_C::SBB_EqGq(bxInstruction_c *i)
void BX_CPU_C::SBB_EqGqM(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
Bit64u op1_64, op2_64, diff_64;
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op2_64 = BX_READ_64BIT_REG(i->nnn());
diff_64 = op1_64 - (op2_64 + temp_CF);
write_RMW_virtual_qword(diff_64);
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
diff_64 = op1_64 - (op2_64 + temp_CF);
BX_WRITE_64BIT_REG(i->rm(), diff_64);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
diff_64 = op1_64 - (op2_64 + temp_CF);
write_RMW_virtual_qword(diff_64);
}
SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB_SBB64(temp_CF));
}
void BX_CPU_C::SBB_EqGqR(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
Bit64u op1_64, op2_64, diff_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
diff_64 = op1_64 - (op2_64 + temp_CF);
BX_WRITE_64BIT_REG(i->rm(), diff_64);
SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB_SBB64(temp_CF));
}
@ -252,24 +265,27 @@ void BX_CPU_C::SBB_EqIdR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB_SBB64(temp_CF));
}
void BX_CPU_C::SUB_EqGq(bxInstruction_c *i)
void BX_CPU_C::SUB_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op2_64 = BX_READ_64BIT_REG(i->nnn());
diff_64 = op1_64 - op2_64;
write_RMW_virtual_qword(diff_64);
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
diff_64 = op1_64 - op2_64;
BX_WRITE_64BIT_REG(i->rm(), diff_64);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
diff_64 = op1_64 - op2_64;
write_RMW_virtual_qword(diff_64);
}
SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB64);
}
void BX_CPU_C::SUB_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
diff_64 = op1_64 - op2_64;
BX_WRITE_64BIT_REG(i->rm(), diff_64);
SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB64);
}
@ -311,21 +327,24 @@ void BX_CPU_C::SUB_RAXId(bxInstruction_c *i)
SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB64);
}
void BX_CPU_C::CMP_EqGq(bxInstruction_c *i)
void BX_CPU_C::CMP_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
/* pointer, segment address pair */
read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op2_64 = BX_READ_64BIT_REG(i->nnn());
diff_64 = op1_64 - op2_64;
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_COMPARE64);
}
void BX_CPU_C::CMP_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_COMPARE64);
@ -378,7 +397,7 @@ void BX_CPU_C::CQO(bxInstruction_c *i)
RDX = 0;
}
void BX_CPU_C::XADD_EqGq(bxInstruction_c *i)
void BX_CPU_C::XADD_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, sum_64;
@ -388,33 +407,38 @@ void BX_CPU_C::XADD_EqGq(bxInstruction_c *i)
* dst <-- tmp | op1 = sum
*/
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op2_64 = BX_READ_64BIT_REG(i->nnn());
sum_64 = op1_64 + op2_64;
write_RMW_virtual_qword(sum_64);
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
/* and write destination into source */
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
SET_FLAGS_OSZAPC_S1_64(op1_64, sum_64, BX_INSTR_ADD64);
}
void BX_CPU_C::XADD_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, sum_64;
/* XADD dst(r/m), src(r)
* temp <-- src + dst | sum = op2 + op1
* src <-- dst | op2 = op1
* dst <-- tmp | op1 = sum
*/
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
sum_64 = op1_64 + op2_64;
/* now write sum back to destination */
if (i->modC0()) {
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->rm(), sum_64);
}
else {
write_RMW_virtual_qword(sum_64);
/* and write destination into source */
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
}
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->rm(), sum_64);
SET_FLAGS_OSZAPC_S1_64(op1_64, sum_64, BX_INSTR_ADD64);
}
@ -584,33 +608,38 @@ void BX_CPU_C::DEC_EqR(bxInstruction_c *i)
SET_FLAGS_OSZAP_RESULT_64(op1_64, BX_INSTR_DEC64);
}
void BX_CPU_C::CMPXCHG_EqGq(bxInstruction_c *i)
void BX_CPU_C::CMPXCHG_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
diff_64 = RAX - op1_64;
SET_FLAGS_OSZAPC_64(RAX, op1_64, diff_64, BX_INSTR_COMPARE64);
if (diff_64 == 0) { // if accumulator == dest
// dest <-- src
op2_64 = BX_READ_64BIT_REG(i->nnn());
write_RMW_virtual_qword(op2_64);
}
else {
// accumulator <-- dest
RAX = op1_64;
}
}
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), op2_64);
}
else {
write_RMW_virtual_qword(op2_64);
}
void BX_CPU_C::CMPXCHG_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
diff_64 = RAX - op1_64;
SET_FLAGS_OSZAPC_64(RAX, op1_64, diff_64, BX_INSTR_COMPARE64);
if (diff_64 == 0) { // if accumulator == dest
// dest <-- src
op2_64 = BX_READ_64BIT_REG(i->nnn());
BX_WRITE_64BIT_REG(i->rm(), op2_64);
}
else {
// accumulator <-- dest

98
bochs/cpu/arith8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith8.cc,v 1.45 2007-11-17 18:08:46 sshwarts Exp $
// $Id: arith8.cc,v 1.46 2007-11-18 18:24:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -335,7 +335,7 @@ void BX_CPU_C::CMP_ALIb(bxInstruction_c *i)
SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_COMPARE8);
}
void BX_CPU_C::XADD_EbGb(bxInstruction_c *i)
void BX_CPU_C::XADD_EbGbM(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit8u op1, op2, sum;
@ -346,25 +346,42 @@ void BX_CPU_C::XADD_EbGb(bxInstruction_c *i)
* dst <-- tmp | op1 = sum
*/
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
sum = op1 + op2;
write_RMW_virtual_byte(sum);
if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
sum = op1 + op2;
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), sum);
}
else {
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
sum = op1 + op2;
write_RMW_virtual_byte(sum);
/* and write destination into source */
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
}
/* and write destination into source */
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
SET_FLAGS_OSZAPC_S1_8(op1, sum, BX_INSTR_ADD8);
#else
BX_INFO(("XADD_EbGb: not supported on < 80486"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::XADD_EbGbR(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit8u op1, op2, sum;
/* XADD dst(r/m8), src(r8)
* temp <-- src + dst | sum = op2 + op1
* src <-- dst | op2 = op1
* dst <-- tmp | op1 = sum
*/
op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
sum = op1 + op2;
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), sum);
SET_FLAGS_OSZAPC_S1_8(op1, sum, BX_INSTR_ADD8);
#else
@ -520,18 +537,12 @@ void BX_CPU_C::DEC_EbR(bxInstruction_c *i)
SET_FLAGS_OSZAP_RESULT_8(op1_8, BX_INSTR_DEC8);
}
void BX_CPU_C::CMPXCHG_EbGb(bxInstruction_c *i)
void BX_CPU_C::CMPXCHG_EbGbM(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit8u op1_8, op2_8, diff_8;
if (i->modC0()) {
op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
}
else {
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
}
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
diff_8 = AL - op1_8;
SET_FLAGS_OSZAPC_8(AL, op1_8, diff_8, BX_INSTR_COMPARE8);
@ -539,13 +550,32 @@ void BX_CPU_C::CMPXCHG_EbGb(bxInstruction_c *i)
if (diff_8 == 0) { // if accumulator == dest
// dest <-- src
op2_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op2_8);
}
else {
write_RMW_virtual_byte(op2_8);
}
write_RMW_virtual_byte(op2_8);
}
else {
// accumulator <-- dest
AL = op1_8;
}
#else
BX_INFO(("CMPXCHG_EbGb: not supported for cpulevel <= 3"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::CMPXCHG_EbGbR(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit8u op1_8, op2_8, diff_8;
op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
diff_8 = AL - op1_8;
SET_FLAGS_OSZAPC_8(AL, op1_8, diff_8, BX_INSTR_COMPARE8);
if (diff_8 == 0) { // if accumulator == dest
// dest <-- src
op2_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op2_8);
}
else {
// accumulator <-- dest

239
bochs/cpu/bit.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bit.cc,v 1.36 2007-11-17 23:28:30 sshwarts Exp $
// $Id: bit.cc,v 1.37 2007-11-18 18:24:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -554,22 +554,13 @@ void BX_CPU_C::BSWAP_RRX(bxInstruction_c *i)
}
#endif // #if BX_SUPPORT_X86_64
void BX_CPU_C::BT_EwGw(bxInstruction_c *i)
void BX_CPU_C::BT_EwGwM(bxInstruction_c *i)
{
bx_address op1_addr;
Bit16u op1_16, op2_16, index;
Bit32s displacement32;
op2_16 = BX_READ_16BIT_REG(i->nnn());
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 &= 0x0f;
setB_CF((op1_16 >> op2_16) & 0x01);
return;
}
index = op2_16 & 0x0f;
displacement32 = ((Bit16s) (op2_16&0xfff0)) / 16;
op1_addr = RMAddr(i) + 2 * displacement32;
@ -580,6 +571,16 @@ void BX_CPU_C::BT_EwGw(bxInstruction_c *i)
setB_CF((op1_16 >> index) & 0x01);
}
void BX_CPU_C::BT_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 &= 0x0f;
setB_CF((op1_16 >> op2_16) & 0x01);
}
void BX_CPU_C::BT_EdGdM(bxInstruction_c *i)
{
bx_address op1_addr;
@ -610,7 +611,7 @@ void BX_CPU_C::BT_EdGdR(bxInstruction_c *i)
}
#if BX_SUPPORT_X86_64
void BX_CPU_C::BT_EqGq(bxInstruction_c *i)
void BX_CPU_C::BT_EqGqM(bxInstruction_c *i)
{
bx_address op1_addr;
Bit64u op1_64, op2_64;
@ -618,15 +619,6 @@ void BX_CPU_C::BT_EqGq(bxInstruction_c *i)
Bit64u index;
op2_64 = BX_READ_64BIT_REG(i->nnn());
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 &= 0x3f;
setB_CF((op1_64 >> op2_64) & 0x01);
return;
}
index = op2_64 & 0x3f;
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
op1_addr = RMAddr(i) + 8 * displacement64;
@ -636,28 +628,25 @@ void BX_CPU_C::BT_EqGq(bxInstruction_c *i)
setB_CF((op1_64 >> index) & 0x01);
}
void BX_CPU_C::BT_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 &= 0x3f;
setB_CF((op1_64 >> op2_64) & 0x01);
}
#endif
void BX_CPU_C::BTS_EwGw(bxInstruction_c *i)
void BX_CPU_C::BTS_EwGwM(bxInstruction_c *i)
{
bx_address op1_addr;
Bit16u op1_16, op2_16, bit_i, index;
Bit32s displacement32;
op2_16 = BX_READ_16BIT_REG(i->nnn());
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 &= 0x0f;
setB_CF((op1_16 >> op2_16) & 0x01);
op1_16 |= (((Bit16u) 1) << op2_16);
/* now write diff back to destination */
BX_WRITE_16BIT_REG(i->rm(), op1_16);
return;
}
index = op2_16 & 0x0f;
displacement32 = ((Bit16s) (op2_16 & 0xfff0)) / 16;
op1_addr = RMAddr(i) + 2 * displacement32;
@ -673,6 +662,20 @@ void BX_CPU_C::BTS_EwGw(bxInstruction_c *i)
setB_CF(bit_i);
}
void BX_CPU_C::BTS_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 &= 0x0f;
setB_CF((op1_16 >> op2_16) & 0x01);
op1_16 |= (((Bit16u) 1) << op2_16);
/* now write diff back to destination */
BX_WRITE_16BIT_REG(i->rm(), op1_16);
}
void BX_CPU_C::BTS_EdGdM(bxInstruction_c *i)
{
bx_address op1_addr;
@ -711,7 +714,7 @@ void BX_CPU_C::BTS_EdGdR(bxInstruction_c *i)
}
#if BX_SUPPORT_X86_64
void BX_CPU_C::BTS_EqGq(bxInstruction_c *i)
void BX_CPU_C::BTS_EqGqM(bxInstruction_c *i)
{
bx_address op1_addr;
Bit64u op1_64, op2_64, index;
@ -719,19 +722,6 @@ void BX_CPU_C::BTS_EqGq(bxInstruction_c *i)
Bit64u bit_i;
op2_64 = BX_READ_64BIT_REG(i->nnn());
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 &= 0x3f;
setB_CF((op1_64 >> op2_64) & 0x01);
op1_64 |= (((Bit64u) 1) << op2_64);
/* now write diff back to destination */
BX_WRITE_64BIT_REG(i->rm(), op1_64);
return;
}
index = op2_64 & 0x3f;
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
op1_addr = RMAddr(i) + 8 * displacement64;
@ -746,28 +736,29 @@ void BX_CPU_C::BTS_EqGq(bxInstruction_c *i)
setB_CF(bit_i);
}
void BX_CPU_C::BTS_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 &= 0x3f;
setB_CF((op1_64 >> op2_64) & 0x01);
op1_64 |= (((Bit64u) 1) << op2_64);
/* now write diff back to destination */
BX_WRITE_64BIT_REG(i->rm(), op1_64);
}
#endif
void BX_CPU_C::BTR_EwGw(bxInstruction_c *i)
void BX_CPU_C::BTR_EwGwM(bxInstruction_c *i)
{
bx_address op1_addr;
Bit16u op1_16, op2_16, index;
Bit32s displacement32;
op2_16 = BX_READ_16BIT_REG(i->nnn());
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 &= 0x0f;
setB_CF((op1_16 >> op2_16) & 0x01);
op1_16 &= ~(((Bit16u) 1) << op2_16);
/* now write diff back to destination */
BX_WRITE_16BIT_REG(i->rm(), op1_16);
return;
}
index = op2_16 & 0x0f;
displacement32 = ((Bit16s) (op2_16&0xfff0)) / 16;
op1_addr = RMAddr(i) + 2 * displacement32;
@ -784,6 +775,20 @@ void BX_CPU_C::BTR_EwGw(bxInstruction_c *i)
setB_CF(temp_cf);
}
void BX_CPU_C::BTR_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 &= 0x0f;
setB_CF((op1_16 >> op2_16) & 0x01);
op1_16 &= ~(((Bit16u) 1) << op2_16);
/* now write diff back to destination */
BX_WRITE_16BIT_REG(i->rm(), op1_16);
}
void BX_CPU_C::BTR_EdGdM(bxInstruction_c *i)
{
bx_address op1_addr;
@ -823,26 +828,13 @@ void BX_CPU_C::BTR_EdGdR(bxInstruction_c *i)
}
#if BX_SUPPORT_X86_64
void BX_CPU_C::BTR_EqGq(bxInstruction_c *i)
void BX_CPU_C::BTR_EqGqM(bxInstruction_c *i)
{
bx_address op1_addr;
Bit64u op1_64, op2_64, index;
Bit64s displacement64;
op2_64 = BX_READ_64BIT_REG(i->nnn());
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 &= 0x3f;
setB_CF((op1_64 >> op2_64) & 0x01);
op1_64 &= ~(((Bit64u) 1) << op2_64);
/* now write diff back to destination */
BX_WRITE_64BIT_REG(i->rm(), op1_64);
return;
}
index = op2_64 & 0x3f;
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
op1_addr = RMAddr(i) + 8 * displacement64;
@ -858,9 +850,23 @@ void BX_CPU_C::BTR_EqGq(bxInstruction_c *i)
setB_CF(temp_cf);
}
void BX_CPU_C::BTR_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 &= 0x3f;
setB_CF((op1_64 >> op2_64) & 0x01);
op1_64 &= ~(((Bit64u) 1) << op2_64);
/* now write diff back to destination */
BX_WRITE_64BIT_REG(i->rm(), op1_64);
}
#endif
void BX_CPU_C::BTC_EwGw(bxInstruction_c *i)
void BX_CPU_C::BTC_EwGwM(bxInstruction_c *i)
{
bx_address op1_addr;
Bit16u op1_16, op2_16, index_16;
@ -869,28 +875,32 @@ void BX_CPU_C::BTC_EwGw(bxInstruction_c *i)
op2_16 = BX_READ_16BIT_REG(i->nnn());
index_16 = op2_16 & 0x0f;
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
op1_addr = 0; // keep compiler happy
}
else {
displacement16 = ((Bit16s) (op2_16 & 0xfff0)) / 16;
op1_addr = RMAddr(i) + 2 * displacement16;
read_RMW_virtual_word(i->seg(), op1_addr, &op1_16);
}
displacement16 = ((Bit16s) (op2_16 & 0xfff0)) / 16;
op1_addr = RMAddr(i) + 2 * displacement16;
read_RMW_virtual_word(i->seg(), op1_addr, &op1_16);
bx_bool temp_CF = (op1_16 >> index_16) & 0x01;
op1_16 ^= (((Bit16u) 1) << index_16); /* toggle bit */
setB_CF(temp_CF);
/* now write diff back to destination */
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), op1_16);
}
else {
write_RMW_virtual_word(op1_16);
}
write_RMW_virtual_word(op1_16);
setB_CF(temp_CF);
}
void BX_CPU_C::BTC_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 &= 0x0f;
bx_bool temp_CF = (op1_16 >> op2_16) & 0x01;
op1_16 ^= (((Bit16u) 1) << op2_16); /* toggle bit */
setB_CF(temp_CF);
BX_WRITE_16BIT_REG(i->rm(), op1_16);
setB_CF(temp_CF);
}
@ -931,7 +941,7 @@ void BX_CPU_C::BTC_EdGdR(bxInstruction_c *i)
}
#if BX_SUPPORT_X86_64
void BX_CPU_C::BTC_EqGq(bxInstruction_c *i)
void BX_CPU_C::BTC_EqGqM(bxInstruction_c *i)
{
bx_address op1_addr;
Bit64u op1_64, op2_64;
@ -940,29 +950,30 @@ void BX_CPU_C::BTC_EqGq(bxInstruction_c *i)
op2_64 = BX_READ_64BIT_REG(i->nnn());
index = op2_64 & 0x3f;
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_addr = 0; // keep compiler happy
}
else {
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
op1_addr = RMAddr(i) + 8 * displacement64;
read_RMW_virtual_qword(i->seg(), op1_addr, &op1_64);
}
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
op1_addr = RMAddr(i) + 8 * displacement64;
read_RMW_virtual_qword(i->seg(), op1_addr, &op1_64);
bx_bool temp_CF = (op1_64 >> index) & 0x01;
op1_64 ^= (((Bit64u) 1) << index); /* toggle bit */
setB_CF(temp_CF);
/* now write diff back to destination */
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), op1_64);
}
else {
write_RMW_virtual_qword(op1_64);
}
write_RMW_virtual_qword(op1_64);
}
void BX_CPU_C::BTC_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 &= 0x3f;
bx_bool temp_CF = (op1_64 >> op2_64) & 0x01;
op1_64 ^= (((Bit64u) 1) << op2_64); /* toggle bit */
setB_CF(temp_CF);
BX_WRITE_64BIT_REG(i->rm(), op1_64);
}
#endif

162
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.364 2007-11-17 23:28:30 sshwarts Exp $
// $Id: cpu.h,v 1.365 2007-11-18 18:24:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1464,10 +1464,11 @@ public: // for now...
BX_SMF void TEST_EwGwM(bxInstruction_c *);
BX_SMF void TEST_EdGdM(bxInstruction_c *);
BX_SMF void XCHG_EbGbR(bxInstruction_c *);
BX_SMF void XCHG_EbGbM(bxInstruction_c *);
BX_SMF void XCHG_EwGw(bxInstruction_c *);
BX_SMF void XCHG_EdGdR(bxInstruction_c *);
BX_SMF void XCHG_EdGdM(bxInstruction_c *);
BX_SMF void XCHG_EbGb(bxInstruction_c *);
BX_SMF void XCHG_EwGw(bxInstruction_c *);
BX_SMF void MOV_EbGbM(bxInstruction_c *);
BX_SMF void MOV_EbGbR(bxInstruction_c *);
@ -1676,26 +1677,30 @@ public: // for now...
BX_SMF void BSR_GwEw(bxInstruction_c *);
BX_SMF void BSR_GdEd(bxInstruction_c *);
BX_SMF void BT_EdGdR(bxInstruction_c *);
BX_SMF void BT_EwGwM(bxInstruction_c *);
BX_SMF void BT_EdGdM(bxInstruction_c *);
BX_SMF void BTS_EdGdR(bxInstruction_c *);
BX_SMF void BTS_EwGwM(bxInstruction_c *);
BX_SMF void BTS_EdGdM(bxInstruction_c *);
BX_SMF void BTR_EdGdR(bxInstruction_c *);
BX_SMF void BTR_EwGwM(bxInstruction_c *);
BX_SMF void BTR_EdGdM(bxInstruction_c *);
BX_SMF void BTC_EdGdR(bxInstruction_c *);
BX_SMF void BTC_EwGwM(bxInstruction_c *);
BX_SMF void BTC_EdGdM(bxInstruction_c *);
BX_SMF void BT_EwGw(bxInstruction_c *);
BX_SMF void BT_EwGwR(bxInstruction_c *);
BX_SMF void BT_EdGdR(bxInstruction_c *);
BX_SMF void BTS_EwGwR(bxInstruction_c *);
BX_SMF void BTS_EdGdR(bxInstruction_c *);
BX_SMF void BTR_EwGwR(bxInstruction_c *);
BX_SMF void BTR_EdGdR(bxInstruction_c *);
BX_SMF void BTC_EwGwR(bxInstruction_c *);
BX_SMF void BTC_EdGdR(bxInstruction_c *);
BX_SMF void BT_EwIb(bxInstruction_c *);
BX_SMF void BT_EdIb(bxInstruction_c *);
BX_SMF void BTS_EwGw(bxInstruction_c *);
BX_SMF void BTS_EwIb(bxInstruction_c *);
BX_SMF void BTS_EdIb(bxInstruction_c *);
BX_SMF void BTR_EwGw(bxInstruction_c *);
BX_SMF void BTR_EwIb(bxInstruction_c *);
BX_SMF void BTR_EdIb(bxInstruction_c *);
BX_SMF void BTC_EwGw(bxInstruction_c *);
BX_SMF void BTC_EwIb(bxInstruction_c *);
BX_SMF void BTC_EdIb(bxInstruction_c *);
@ -2565,16 +2570,20 @@ public: // for now...
BX_SMF void CMPXCHG_XBTS(bxInstruction_c *);
BX_SMF void CMPXCHG_IBTS(bxInstruction_c *);
BX_SMF void CMPXCHG_EbGb(bxInstruction_c *);
BX_SMF void CMPXCHG_EdGd(bxInstruction_c *);
BX_SMF void CMPXCHG8B(bxInstruction_c *);
BX_SMF void XADD_EbGb(bxInstruction_c *);
BX_SMF void XADD_EdGd(bxInstruction_c *);
BX_SMF void RETnear32_Iw(bxInstruction_c *);
BX_SMF void RETnear16_Iw(bxInstruction_c *);
BX_SMF void RETfar32_Iw(bxInstruction_c *);
BX_SMF void RETfar16_Iw(bxInstruction_c *);
BX_SMF void XADD_EbGbM(bxInstruction_c *);
BX_SMF void XADD_EwGwM(bxInstruction_c *);
BX_SMF void XADD_EdGdM(bxInstruction_c *);
BX_SMF void XADD_EbGbR(bxInstruction_c *);
BX_SMF void XADD_EwGwR(bxInstruction_c *);
BX_SMF void XADD_EdGdR(bxInstruction_c *);
#if BX_CPU_LEVEL == 2
BX_SMF void LOADALL(bxInstruction_c *);
#endif
@ -2589,9 +2598,15 @@ public: // for now...
BX_SMF void CMP_AXIw(bxInstruction_c *);
BX_SMF void CWDE(bxInstruction_c *);
BX_SMF void CDQ(bxInstruction_c *);
BX_SMF void XADD_EwGw(bxInstruction_c *);
BX_SMF void CMPXCHG_EwGw(bxInstruction_c *);
BX_SMF void CMPXCHG_EbGbM(bxInstruction_c *);
BX_SMF void CMPXCHG_EwGwM(bxInstruction_c *);
BX_SMF void CMPXCHG_EdGdM(bxInstruction_c *);
BX_SMF void CMPXCHG_EbGbR(bxInstruction_c *);
BX_SMF void CMPXCHG_EwGwR(bxInstruction_c *);
BX_SMF void CMPXCHG_EdGdR(bxInstruction_c *);
BX_SMF void MUL_AXEw(bxInstruction_c *);
BX_SMF void IMUL_AXEw(bxInstruction_c *);
BX_SMF void DIV_AXEw(bxInstruction_c *);
@ -2621,40 +2636,31 @@ public: // for now...
#if BX_SUPPORT_X86_64
// 64 bit extensions
BX_SMF void ADD_EqGq(bxInstruction_c *);
BX_SMF void ADD_GqEq(bxInstruction_c *);
BX_SMF void ADD_RAXId(bxInstruction_c *);
BX_SMF void ADC_EqGq(bxInstruction_c *);
BX_SMF void ADC_GqEq(bxInstruction_c *);
BX_SMF void ADC_RAXId(bxInstruction_c *);
BX_SMF void SUB_EqGq(bxInstruction_c *);
BX_SMF void SUB_GqEq(bxInstruction_c *);
BX_SMF void SUB_RAXId(bxInstruction_c *);
BX_SMF void SBB_EqGq(bxInstruction_c *);
BX_SMF void SBB_GqEq(bxInstruction_c *);
BX_SMF void SBB_RAXId(bxInstruction_c *);
BX_SMF void OR_EqGq(bxInstruction_c *);
BX_SMF void OR_GqEq(bxInstruction_c *);
BX_SMF void OR_RAXId(bxInstruction_c *);
BX_SMF void AND_EqGq(bxInstruction_c *);
BX_SMF void ADC_GqEq(bxInstruction_c *);
BX_SMF void SBB_GqEq(bxInstruction_c *);
BX_SMF void AND_GqEq(bxInstruction_c *);
BX_SMF void AND_RAXId(bxInstruction_c *);
BX_SMF void XOR_EqGq(bxInstruction_c *);
BX_SMF void SUB_GqEq(bxInstruction_c *);
BX_SMF void XOR_GqEq(bxInstruction_c *);
BX_SMF void XOR_RAXId(bxInstruction_c *);
BX_SMF void CMP_EqGq(bxInstruction_c *);
BX_SMF void CMP_GqEq(bxInstruction_c *);
BX_SMF void ADD_RAXId(bxInstruction_c *);
BX_SMF void OR_RAXId(bxInstruction_c *);
BX_SMF void ADC_RAXId(bxInstruction_c *);
BX_SMF void SBB_RAXId(bxInstruction_c *);
BX_SMF void AND_RAXId(bxInstruction_c *);
BX_SMF void SUB_RAXId(bxInstruction_c *);
BX_SMF void XOR_RAXId(bxInstruction_c *);
BX_SMF void CMP_RAXId(bxInstruction_c *);
BX_SMF void PUSH64_Id(bxInstruction_c *);
BX_SMF void TEST_EqGqR(bxInstruction_c *);
BX_SMF void TEST_EqGqM(bxInstruction_c *);
BX_SMF void TEST_RAXId(bxInstruction_c *);
BX_SMF void TEST_EqGq(bxInstruction_c *);
BX_SMF void XCHG_EqGq(bxInstruction_c *);
BX_SMF void XCHG_EqGqR(bxInstruction_c *);
BX_SMF void XCHG_EqGqM(bxInstruction_c *);
BX_SMF void LEA_GqM(bxInstruction_c *);
BX_SMF void MOV_RAXOq(bxInstruction_c *);
@ -2665,9 +2671,11 @@ public: // for now...
BX_SMF void MOV_OqAX(bxInstruction_c *);
BX_SMF void MOV_ALOq(bxInstruction_c *);
BX_SMF void MOV_OqAL(bxInstruction_c *);
BX_SMF void MOV_EqGq(bxInstruction_c *);
BX_SMF void MOV_GqEq(bxInstruction_c *);
BX_SMF void MOV_EqGqR(bxInstruction_c *);
BX_SMF void MOV_EqGqM(bxInstruction_c *);
BX_SMF void MOV_GqEqR(bxInstruction_c *);
BX_SMF void MOV_GqEqM(bxInstruction_c *);
BX_SMF void MOV_EqIdR(bxInstruction_c *);
BX_SMF void MOV_EqIdM(bxInstruction_c *);
@ -2683,10 +2691,8 @@ public: // for now...
BX_SMF void REP_LODSQ_RAXXq(bxInstruction_c *);
BX_SMF void REP_SCASQ_RAXXq(bxInstruction_c *);
BX_SMF void RETnear64(bxInstruction_c *);
BX_SMF void ENTER64_IwIb(bxInstruction_c *);
BX_SMF void LEAVE64(bxInstruction_c *);
BX_SMF void RETfar64(bxInstruction_c *);
BX_SMF void IRET64(bxInstruction_c *);
@ -2720,27 +2726,56 @@ public: // for now...
BX_SMF void IMUL_GqEq(bxInstruction_c *);
BX_SMF void IMUL_GqEqId(bxInstruction_c *);
BX_SMF void MOVZX_GqEb(bxInstruction_c *);
BX_SMF void MOVZX_GqEw(bxInstruction_c *);
BX_SMF void MOVSX_GqEb(bxInstruction_c *);
BX_SMF void MOVSX_GqEw(bxInstruction_c *);
BX_SMF void MOVSX_GqEd(bxInstruction_c *);
BX_SMF void MOVZX_GqEbM(bxInstruction_c *);
BX_SMF void MOVZX_GqEwM(bxInstruction_c *);
BX_SMF void MOVSX_GqEbM(bxInstruction_c *);
BX_SMF void MOVSX_GqEwM(bxInstruction_c *);
BX_SMF void MOVSX_GqEdM(bxInstruction_c *);
BX_SMF void MOVZX_GqEbR(bxInstruction_c *);
BX_SMF void MOVZX_GqEwR(bxInstruction_c *);
BX_SMF void MOVSX_GqEbR(bxInstruction_c *);
BX_SMF void MOVSX_GqEwR(bxInstruction_c *);
BX_SMF void MOVSX_GqEdR(bxInstruction_c *);
BX_SMF void BSF_GqEq(bxInstruction_c *);
BX_SMF void BSR_GqEq(bxInstruction_c *);
BX_SMF void BT_EqGq(bxInstruction_c *);
BX_SMF void BT_EqIb(bxInstruction_c *);
BX_SMF void BT_EqGqM(bxInstruction_c *);
BX_SMF void BTS_EqGqM(bxInstruction_c *);
BX_SMF void BTR_EqGqM(bxInstruction_c *);
BX_SMF void BTC_EqGqM(bxInstruction_c *);
BX_SMF void BTS_EqGq(bxInstruction_c *);
BX_SMF void BT_EqGqR(bxInstruction_c *);
BX_SMF void BTS_EqGqR(bxInstruction_c *);
BX_SMF void BTR_EqGqR(bxInstruction_c *);
BX_SMF void BTC_EqGqR(bxInstruction_c *);
BX_SMF void BT_EqIb(bxInstruction_c *);
BX_SMF void BTS_EqIb(bxInstruction_c *);
BX_SMF void BTR_EqGq(bxInstruction_c *);
BX_SMF void BTR_EqIb(bxInstruction_c *);
BX_SMF void BTC_EqGq(bxInstruction_c *);
BX_SMF void BTC_EqIb(bxInstruction_c *);
BX_SMF void BSWAP_RRX(bxInstruction_c *);
BX_SMF void ADD_EqGqM(bxInstruction_c *);
BX_SMF void OR_EqGqM(bxInstruction_c *);
BX_SMF void ADC_EqGqM(bxInstruction_c *);
BX_SMF void SBB_EqGqM(bxInstruction_c *);
BX_SMF void AND_EqGqM(bxInstruction_c *);
BX_SMF void SUB_EqGqM(bxInstruction_c *);
BX_SMF void XOR_EqGqM(bxInstruction_c *);
BX_SMF void CMP_EqGqM(bxInstruction_c *);
BX_SMF void ADD_EqGqR(bxInstruction_c *);
BX_SMF void OR_EqGqR(bxInstruction_c *);
BX_SMF void ADC_EqGqR(bxInstruction_c *);
BX_SMF void SBB_EqGqR(bxInstruction_c *);
BX_SMF void AND_EqGqR(bxInstruction_c *);
BX_SMF void SUB_EqGqR(bxInstruction_c *);
BX_SMF void XOR_EqGqR(bxInstruction_c *);
BX_SMF void CMP_EqGqR(bxInstruction_c *);
BX_SMF void ADD_EqIdM(bxInstruction_c *);
BX_SMF void OR_EqIdM(bxInstruction_c *);
BX_SMF void ADC_EqIdM(bxInstruction_c *);
@ -2793,11 +2828,16 @@ public: // for now...
BX_SMF void PUSHF_Fq(bxInstruction_c *);
BX_SMF void POPF_Fq(bxInstruction_c *);
BX_SMF void CMPXCHG_EqGq(bxInstruction_c *);
BX_SMF void CMPXCHG_EqGqR(bxInstruction_c *);
BX_SMF void CMPXCHG_EqGqM(bxInstruction_c *);
BX_SMF void CDQE(bxInstruction_c *);
BX_SMF void CQO(bxInstruction_c *);
BX_SMF void XADD_EqGq(bxInstruction_c *);
BX_SMF void XADD_EqGqR(bxInstruction_c *);
BX_SMF void XADD_EqGqM(bxInstruction_c *);
BX_SMF void RETnear64(bxInstruction_c *);
BX_SMF void RETnear64_Iw(bxInstruction_c *);
BX_SMF void RETfar64(bxInstruction_c *);
BX_SMF void RETfar64_Iw(bxInstruction_c *);
BX_SMF void CMOV_GqEq(bxInstruction_c *);
@ -2808,6 +2848,7 @@ public: // for now...
BX_SMF void POP_Eq(bxInstruction_c *);
BX_SMF void XCHG_RRXRAX(bxInstruction_c *);
BX_SMF void PUSH64_Id(bxInstruction_c *);
BX_SMF void PUSH64_FS(bxInstruction_c *);
BX_SMF void POP64_FS(bxInstruction_c *);
BX_SMF void PUSH64_GS(bxInstruction_c *);
@ -2836,7 +2877,6 @@ public: // for now...
BX_SMF void CMPXCHG16B(bxInstruction_c *);
BX_SMF void POPCNT_GqEq(bxInstruction_c *);
BX_SMF void MOVNTI_MqGq(bxInstruction_c *i);
#endif // #if BX_SUPPORT_X86_64

13
bochs/cpu/ctrl_xfer16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ctrl_xfer16.cc,v 1.41 2007-11-17 18:08:46 sshwarts Exp $
// $Id: ctrl_xfer16.cc,v 1.42 2007-11-18 18:24:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -241,11 +241,6 @@ void BX_CPU_C::CALL16_Ep(bxInstruction_c *i)
BX_CPU_THIS_PTR show_flag |= Flag_call;
#endif
if (i->modC0()) {
BX_INFO(("CALL_Ep: op1 is a register"));
exception(BX_UD_EXCEPTION, 0, 0);
}
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
read_virtual_word(i->seg(), RMAddr(i)+2, &cs_raw);
@ -537,12 +532,6 @@ void BX_CPU_C::JMP16_Ep(bxInstruction_c *i)
invalidate_prefetch_q();
if (i->modC0()) {
/* far indirect must specify a memory address */
BX_INFO(("JMP_Ep(): op1 is a register"));
exception(BX_UD_EXCEPTION, 0, 0);
}
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
read_virtual_word(i->seg(), RMAddr(i)+2, &cs_raw);

16
bochs/cpu/data_xfer16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer16.cc,v 1.45 2007-11-17 18:28:58 sshwarts Exp $
// $Id: data_xfer16.cc,v 1.46 2007-11-18 18:24:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -95,14 +95,9 @@ void BX_CPU_C::MOV_SwEw(bxInstruction_c *i)
{
Bit16u op2_16;
/* If attempt is made to load the CS register ... */
if (i->nnn() == BX_SEG_REG_CS) {
UndefinedOpcode(i);
}
/* Illegal to use nonexisting segments */
if (i->nnn() >= 6) {
BX_INFO(("MOV_EwSw: using of nonexisting segment register %d", i->nnn()));
/* Attempt to load CS or nonexisting segment register */
if (i->nnn() >= 6 || i->nnn() == BX_SEG_REG_CS) {
BX_INFO(("MOV_EwSw: can't use this segment register %d", i->nnn()));
UndefinedOpcode(i);
}
@ -120,8 +115,7 @@ void BX_CPU_C::MOV_SwEw(bxInstruction_c *i)
// trap exceptions until the execution boundary following the
// next instruction is reached.
// Same code as POP_SS()
BX_CPU_THIS_PTR inhibit_mask |=
BX_INHIBIT_INTERRUPTS | BX_INHIBIT_DEBUG;
BX_CPU_THIS_PTR inhibit_mask |= BX_INHIBIT_INTERRUPTS | BX_INHIBIT_DEBUG;
BX_CPU_THIS_PTR async_event = 1;
}
}

152
bochs/cpu/data_xfer64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer64.cc,v 1.27 2007-11-17 18:08:46 sshwarts Exp $
// $Id: data_xfer64.cc,v 1.28 2007-11-18 18:24:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -46,30 +46,26 @@ void BX_CPU_C::MOV_RRXIq(bxInstruction_c *i)
BX_WRITE_64BIT_REG(i->opcodeReg(), i->Iq());
}
void BX_CPU_C::MOV_EqGq(bxInstruction_c *i)
void BX_CPU_C::MOV_EqGqM(bxInstruction_c *i)
{
Bit64u op2_64 = BX_READ_64BIT_REG(i->nnn());
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), op2_64);
}
else {
write_virtual_qword(i->seg(), RMAddr(i), &op2_64);
}
write_virtual_qword(i->seg(), RMAddr(i), &BX_READ_64BIT_REG(i->nnn()));
}
void BX_CPU_C::MOV_GqEq(bxInstruction_c *i)
void BX_CPU_C::MOV_EqGqR(bxInstruction_c *i)
{
Bit64u op2_64;
Bit64u op2_64 = BX_READ_64BIT_REG(i->nnn());
BX_WRITE_64BIT_REG(i->rm(), op2_64);
}
if (i->modC0()) {
op2_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
}
void BX_CPU_C::MOV_GqEqM(bxInstruction_c *i)
{
/* pointer, segment address pair */
read_virtual_qword(i->seg(), RMAddr(i), &BX_READ_64BIT_REG(i->nnn()));
}
void BX_CPU_C::MOV_GqEqR(bxInstruction_c *i)
{
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
BX_WRITE_64BIT_REG(i->nnn(), op2_64);
}
@ -135,103 +131,119 @@ void BX_CPU_C::MOV_EqIdR(bxInstruction_c *i)
BX_WRITE_64BIT_REG(i->rm(), op_64);
}
void BX_CPU_C::MOVZX_GqEb(bxInstruction_c *i)
void BX_CPU_C::MOVZX_GqEbM(bxInstruction_c *i)
{
Bit8u op2_8;
if (i->modC0()) {
op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
else {
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op2_8);
}
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op2_8);
/* zero extend byte op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit64u) op2_8);
}
void BX_CPU_C::MOVZX_GqEw(bxInstruction_c *i)
void BX_CPU_C::MOVZX_GqEbR(bxInstruction_c *i)
{
Bit8u op2_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
/* zero extend byte op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit64u) op2_8);
}
void BX_CPU_C::MOVZX_GqEwM(bxInstruction_c *i)
{
Bit16u op2_16;
if (i->modC0()) {
op2_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
/* zero extend word op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit64u) op2_16);
}
void BX_CPU_C::MOVSX_GqEb(bxInstruction_c *i)
void BX_CPU_C::MOVZX_GqEwR(bxInstruction_c *i)
{
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
/* zero extend word op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit64u) op2_16);
}
void BX_CPU_C::MOVSX_GqEbM(bxInstruction_c *i)
{
Bit8u op2_8;
if (i->modC0()) {
op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
else {
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op2_8);
}
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op2_8);
/* sign extend byte op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit8s) op2_8);
}
void BX_CPU_C::MOVSX_GqEw(bxInstruction_c *i)
void BX_CPU_C::MOVSX_GqEbR(bxInstruction_c *i)
{
Bit8u op2_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
/* sign extend byte op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit8s) op2_8);
}
void BX_CPU_C::MOVSX_GqEwM(bxInstruction_c *i)
{
Bit16u op2_16;
if (i->modC0()) {
op2_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
/* sign extend word op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit16s) op2_16);
}
void BX_CPU_C::MOVSX_GqEd(bxInstruction_c *i)
void BX_CPU_C::MOVSX_GqEwR(bxInstruction_c *i)
{
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
/* sign extend word op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit16s) op2_16);
}
void BX_CPU_C::MOVSX_GqEdM(bxInstruction_c *i)
{
Bit32u op2_32;
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
/* sign extend word op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit32s) op2_32);
}
void BX_CPU_C::XCHG_EqGq(bxInstruction_c *i)
void BX_CPU_C::MOVSX_GqEdR(bxInstruction_c *i)
{
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
/* sign extend word op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit32s) op2_32);
}
void BX_CPU_C::XCHG_EqGqM(bxInstruction_c *i)
{
Bit64u op2_64, op1_64;
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op2_64 = BX_READ_64BIT_REG(i->nnn());
write_RMW_virtual_qword(op2_64);
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
BX_WRITE_64BIT_REG(i->rm(), op2_64);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
write_RMW_virtual_qword(op2_64);
}
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
}
void BX_CPU_C::XCHG_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op2_64 = BX_READ_64BIT_REG(i->nnn());
BX_WRITE_64BIT_REG(i->rm(), op2_64);
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
}

29
bochs/cpu/data_xfer8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer8.cc,v 1.29 2007-11-17 18:08:46 sshwarts Exp $
// $Id: data_xfer8.cc,v 1.30 2007-11-18 18:24:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -105,22 +105,23 @@ void BX_CPU_C::XLAT(bxInstruction_c *i)
read_virtual_byte(i->seg(), offset, &AL);
}
void BX_CPU_C::XCHG_EbGb(bxInstruction_c *i)
void BX_CPU_C::XCHG_EbGbM(bxInstruction_c *i)
{
Bit8u op2, op1;
Bit8u op1, op2;
/* pointer, segment address pair */
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
/* op1 is a register or memory reference */
if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op2);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
write_RMW_virtual_byte(op2);
}
write_RMW_virtual_byte(op2);
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
}
void BX_CPU_C::XCHG_EbGbR(bxInstruction_c *i)
{
Bit8u op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op2);
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
}

133
bochs/cpu/fetchdecode.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.cc,v 1.129 2007-11-17 18:29:00 sshwarts Exp $
// $Id: fetchdecode.cc,v 1.130 2007-11-18 18:24:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -164,56 +164,56 @@ static BxExecutePtr_tR Resolve32Mod0BaseIndex[8] = {
static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
// 512 entries for 16bit mode
/* 00 /wr */ { BxLockable, &BX_CPU_C::ADD_EbGbR },
/* 01 /wr */ { BxLockable, &BX_CPU_C::ADD_EwGwR },
/* 00 /wr */ { 0, &BX_CPU_C::ADD_EbGbR },
/* 01 /wr */ { 0, &BX_CPU_C::ADD_EwGwR },
/* 02 /wr */ { 0, &BX_CPU_C::ADD_GbEb },
/* 03 /wr */ { 0, &BX_CPU_C::ADD_GwEwR },
/* 04 /wr */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
/* 05 /wr */ { BxImmediate_Iv, &BX_CPU_C::ADD_AXIw },
/* 06 /wr */ { 0, &BX_CPU_C::PUSH16_ES },
/* 07 /wr */ { 0, &BX_CPU_C::POP16_ES },
/* 08 /wr */ { BxLockable, &BX_CPU_C::OR_EbGbR },
/* 09 /wr */ { BxLockable, &BX_CPU_C::OR_EwGwR },
/* 08 /wr */ { 0, &BX_CPU_C::OR_EbGbR },
/* 09 /wr */ { 0, &BX_CPU_C::OR_EwGwR },
/* 0A /wr */ { 0, &BX_CPU_C::OR_GbEb },
/* 0B /wr */ { 0, &BX_CPU_C::OR_GwEw },
/* 0C /wr */ { BxImmediate_Ib, &BX_CPU_C::OR_ALIb },
/* 0D /wr */ { BxImmediate_Iv, &BX_CPU_C::OR_AXIw },
/* 0E /wr */ { 0, &BX_CPU_C::PUSH16_CS },
/* 0F /wr */ { 0, &BX_CPU_C::BxError }, // 2-byte escape
/* 10 /wr */ { BxLockable, &BX_CPU_C::ADC_EbGbR },
/* 11 /wr */ { BxLockable, &BX_CPU_C::ADC_EwGwR },
/* 10 /wr */ { 0, &BX_CPU_C::ADC_EbGbR },
/* 11 /wr */ { 0, &BX_CPU_C::ADC_EwGwR },
/* 12 /wr */ { 0, &BX_CPU_C::ADC_GbEb },
/* 13 /wr */ { 0, &BX_CPU_C::ADC_GwEw },
/* 14 /wr */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
/* 15 /wr */ { BxImmediate_Iv, &BX_CPU_C::ADC_AXIw },
/* 16 /wr */ { 0, &BX_CPU_C::PUSH16_SS },
/* 17 /wr */ { 0, &BX_CPU_C::POP16_SS },
/* 18 /wr */ { BxLockable, &BX_CPU_C::SBB_EbGbR },
/* 19 /wr */ { BxLockable, &BX_CPU_C::SBB_EwGwR },
/* 18 /wr */ { 0, &BX_CPU_C::SBB_EbGbR },
/* 19 /wr */ { 0, &BX_CPU_C::SBB_EwGwR },
/* 1A /wr */ { 0, &BX_CPU_C::SBB_GbEb },
/* 1B /wr */ { 0, &BX_CPU_C::SBB_GwEw },
/* 1C /wr */ { BxImmediate_Ib, &BX_CPU_C::SBB_ALIb },
/* 1D /wr */ { BxImmediate_Iv, &BX_CPU_C::SBB_AXIw },
/* 1E /wr */ { 0, &BX_CPU_C::PUSH16_DS },
/* 1F /wr */ { 0, &BX_CPU_C::POP16_DS },
/* 20 /wr */ { BxLockable, &BX_CPU_C::AND_EbGbR },
/* 21 /wr */ { BxLockable, &BX_CPU_C::AND_EwGwR },
/* 20 /wr */ { 0, &BX_CPU_C::AND_EbGbR },
/* 21 /wr */ { 0, &BX_CPU_C::AND_EwGwR },
/* 22 /wr */ { 0, &BX_CPU_C::AND_GbEb },
/* 23 /wr */ { 0, &BX_CPU_C::AND_GwEw },
/* 24 /wr */ { BxImmediate_Ib, &BX_CPU_C::AND_ALIb },
/* 25 /wr */ { BxImmediate_Iv, &BX_CPU_C::AND_AXIw },
/* 26 /wr */ { BxPrefix, &BX_CPU_C::BxError }, // ES:
/* 27 /wr */ { 0, &BX_CPU_C::DAA },
/* 28 /wr */ { BxLockable, &BX_CPU_C::SUB_EbGbR },
/* 29 /wr */ { BxLockable, &BX_CPU_C::SUB_EwGwR },
/* 28 /wr */ { 0, &BX_CPU_C::SUB_EbGbR },
/* 29 /wr */ { 0, &BX_CPU_C::SUB_EwGwR },
/* 2A /wr */ { 0, &BX_CPU_C::SUB_GbEb },
/* 2B /wr */ { 0, &BX_CPU_C::SUB_GwEw },
/* 2C /wr */ { BxImmediate_Ib, &BX_CPU_C::SUB_ALIb },
/* 2D /wr */ { BxImmediate_Iv, &BX_CPU_C::SUB_AXIw },
/* 2E /wr */ { BxPrefix, &BX_CPU_C::BxError }, // CS:
/* 2F /wr */ { 0, &BX_CPU_C::DAS },
/* 30 /wr */ { BxLockable, &BX_CPU_C::XOR_EbGbR },
/* 31 /wr */ { BxLockable, &BX_CPU_C::XOR_EwGwR },
/* 30 /wr */ { 0, &BX_CPU_C::XOR_EbGbR },
/* 31 /wr */ { 0, &BX_CPU_C::XOR_EwGwR },
/* 32 /wr */ { 0, &BX_CPU_C::XOR_GbEb },
/* 33 /wr */ { 0, &BX_CPU_C::XOR_GwEw },
/* 34 /wr */ { BxImmediate_Ib, &BX_CPU_C::XOR_ALIb },
@ -298,8 +298,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 83 /wr */ { BxGroup1 | BxImmediate_Ib_SE, NULL, BxOpcodeInfoG1EwR },
/* 84 /wr */ { 0, &BX_CPU_C::TEST_EbGbR },
/* 85 /wr */ { 0, &BX_CPU_C::TEST_EwGwR },
/* 86 /wr */ { BxLockable, &BX_CPU_C::XCHG_EbGb },
/* 87 /wr */ { BxLockable, &BX_CPU_C::XCHG_EwGw },
/* 86 /wr */ { 0, &BX_CPU_C::XCHG_EbGbR },
/* 87 /wr */ { 0, &BX_CPU_C::XCHG_EwGw },
/* 88 /wr */ { 0, &BX_CPU_C::MOV_EbGbR },
/* 89 /wr */ { 0, &BX_CPU_C::MOV_EwGwR },
/* 8A /wr */ { 0, &BX_CPU_C::MOV_GbEbR },
@ -633,7 +633,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F A0 /wr */ { 0, &BX_CPU_C::PUSH16_FS },
/* 0F A1 /wr */ { 0, &BX_CPU_C::POP16_FS },
/* 0F A2 /wr */ { 0, &BX_CPU_C::CPUID },
/* 0F A3 /wr */ { 0, &BX_CPU_C::BT_EwGw },
/* 0F A3 /wr */ { 0, &BX_CPU_C::BT_EwGwR },
/* 0F A4 /wr */ { BxImmediate_Ib, &BX_CPU_C::SHLD_EwGw },
/* 0F A5 /wr */ { 0, &BX_CPU_C::SHLD_EwGw },
/* 0F A6 /wr */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
@ -641,15 +641,15 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F A8 /wr */ { 0, &BX_CPU_C::PUSH16_GS },
/* 0F A9 /wr */ { 0, &BX_CPU_C::POP16_GS },
/* 0F AA /wr */ { 0, &BX_CPU_C::RSM },
/* 0F AB /wr */ { BxLockable, &BX_CPU_C::BTS_EwGw },
/* 0F AB /wr */ { 0, &BX_CPU_C::BTS_EwGwR },
/* 0F AC /wr */ { BxImmediate_Ib, &BX_CPU_C::SHRD_EwGw },
/* 0F AD /wr */ { 0, &BX_CPU_C::SHRD_EwGw },
/* 0F AE /wr */ { BxGroup15, NULL, BxOpcodeInfoG15R },
/* 0F AF /wr */ { 0, &BX_CPU_C::IMUL_GwEw },
/* 0F B0 /wr */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 /wr */ { BxLockable, &BX_CPU_C::CMPXCHG_EwGw },
/* 0F B0 /wr */ { 0, &BX_CPU_C::CMPXCHG_EbGbR },
/* 0F B1 /wr */ { 0, &BX_CPU_C::CMPXCHG_EwGwR },
/* 0F B2 /wr */ { 0, &BX_CPU_C::BxError }, // LSS
/* 0F B3 /wr */ { BxLockable, &BX_CPU_C::BTR_EwGw },
/* 0F B3 /wr */ { 0, &BX_CPU_C::BTR_EwGwR },
/* 0F B4 /wr */ { 0, &BX_CPU_C::BxError }, // LFS
/* 0F B5 /wr */ { 0, &BX_CPU_C::BxError }, // LGS
/* 0F B6 /wr */ { 0, &BX_CPU_C::MOVZX_GwEbR },
@ -657,13 +657,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F B8 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fb8w },
/* 0F B9 /wr */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F BA /wr */ { BxGroup8, NULL, BxOpcodeInfoG8EwIb },
/* 0F BB /wr */ { BxLockable, &BX_CPU_C::BTC_EwGw },
/* 0F BB /wr */ { 0, &BX_CPU_C::BTC_EwGwR },
/* 0F BC /wr */ { 0, &BX_CPU_C::BSF_GwEw },
/* 0F BD /wr */ { 0, &BX_CPU_C::BSR_GwEw },
/* 0F BE /wr */ { 0, &BX_CPU_C::MOVSX_GwEbR },
/* 0F BF /wr */ { 0, &BX_CPU_C::MOV_GwEwR }, // MOVSX_GwEw
/* 0F C0 /wr */ { BxLockable, &BX_CPU_C::XADD_EbGb },
/* 0F C1 /wr */ { BxLockable, &BX_CPU_C::XADD_EwGw },
/* 0F C0 /wr */ { 0, &BX_CPU_C::XADD_EbGbR },
/* 0F C1 /wr */ { 0, &BX_CPU_C::XADD_EwGwR },
/* 0F C2 /wr */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
/* 0F C3 /wr */ { 0, &BX_CPU_C::BxError }, // MOVNTI SSE group
/* 0F C4 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
@ -728,56 +728,56 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F FF /wr */ { 0, &BX_CPU_C::BxError },
// 512 entries for 32bit mode
/* 00 /dr */ { BxLockable, &BX_CPU_C::ADD_EbGbR },
/* 01 /dr */ { BxLockable, &BX_CPU_C::ADD_EdGdR },
/* 00 /dr */ { 0, &BX_CPU_C::ADD_EbGbR },
/* 01 /dr */ { 0, &BX_CPU_C::ADD_EdGdR },
/* 02 /dr */ { 0, &BX_CPU_C::ADD_GbEb },
/* 03 /dr */ { 0, &BX_CPU_C::ADD_GdEdR },
/* 04 /dr */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
/* 05 /dr */ { BxImmediate_Iv, &BX_CPU_C::ADD_EAXId },
/* 06 /dr */ { 0, &BX_CPU_C::PUSH32_ES },
/* 07 /dr */ { 0, &BX_CPU_C::POP32_ES },
/* 08 /dr */ { BxLockable, &BX_CPU_C::OR_EbGbR },
/* 09 /dr */ { BxLockable, &BX_CPU_C::OR_EdGdR },
/* 08 /dr */ { 0, &BX_CPU_C::OR_EbGbR },
/* 09 /dr */ { 0, &BX_CPU_C::OR_EdGdR },
/* 0A /dr */ { 0, &BX_CPU_C::OR_GbEb },
/* 0B /dr */ { 0, &BX_CPU_C::OR_GdEd },
/* 0C /dr */ { BxImmediate_Ib, &BX_CPU_C::OR_ALIb },
/* 0D /dr */ { BxImmediate_Iv, &BX_CPU_C::OR_EAXId },
/* 0E /dr */ { 0, &BX_CPU_C::PUSH32_CS },
/* 0F /dr */ { 0, &BX_CPU_C::BxError }, // 2-byte escape
/* 10 /dr */ { BxLockable, &BX_CPU_C::ADC_EbGbR },
/* 11 /dr */ { BxLockable, &BX_CPU_C::ADC_EdGdR },
/* 10 /dr */ { 0, &BX_CPU_C::ADC_EbGbR },
/* 11 /dr */ { 0, &BX_CPU_C::ADC_EdGdR },
/* 12 /dr */ { 0, &BX_CPU_C::ADC_GbEb },
/* 13 /dr */ { 0, &BX_CPU_C::ADC_GdEd },
/* 14 /dr */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
/* 15 /dr */ { BxImmediate_Iv, &BX_CPU_C::ADC_EAXId },
/* 16 /dr */ { 0, &BX_CPU_C::PUSH32_SS },
/* 17 /dr */ { 0, &BX_CPU_C::POP32_SS },
/* 18 /dr */ { BxLockable, &BX_CPU_C::SBB_EbGbR },
/* 19 /dr */ { BxLockable, &BX_CPU_C::SBB_EdGdR },
/* 18 /dr */ { 0, &BX_CPU_C::SBB_EbGbR },
/* 19 /dr */ { 0, &BX_CPU_C::SBB_EdGdR },
/* 1A /dr */ { 0, &BX_CPU_C::SBB_GbEb },
/* 1B /dr */ { 0, &BX_CPU_C::SBB_GdEd },
/* 1C /dr */ { BxImmediate_Ib, &BX_CPU_C::SBB_ALIb },
/* 1D /dr */ { BxImmediate_Iv, &BX_CPU_C::SBB_EAXId },
/* 1E /dr */ { 0, &BX_CPU_C::PUSH32_DS },
/* 1F /dr */ { 0, &BX_CPU_C::POP32_DS },
/* 20 /dr */ { BxLockable, &BX_CPU_C::AND_EbGbR },
/* 21 /dr */ { BxLockable, &BX_CPU_C::AND_EdGdR },
/* 20 /dr */ { 0, &BX_CPU_C::AND_EbGbR },
/* 21 /dr */ { 0, &BX_CPU_C::AND_EdGdR },
/* 22 /dr */ { 0, &BX_CPU_C::AND_GbEb },
/* 23 /dr */ { 0, &BX_CPU_C::AND_GdEd },
/* 24 /dr */ { BxImmediate_Ib, &BX_CPU_C::AND_ALIb },
/* 25 /dr */ { BxImmediate_Iv, &BX_CPU_C::AND_EAXId },
/* 26 /dr */ { BxPrefix, &BX_CPU_C::BxError }, // ES:
/* 27 /dr */ { 0, &BX_CPU_C::DAA },
/* 28 /dr */ { BxLockable, &BX_CPU_C::SUB_EbGbR },
/* 29 /dr */ { BxLockable, &BX_CPU_C::SUB_EdGdR },
/* 28 /dr */ { 0, &BX_CPU_C::SUB_EbGbR },
/* 29 /dr */ { 0, &BX_CPU_C::SUB_EdGdR },
/* 2A /dr */ { 0, &BX_CPU_C::SUB_GbEb },
/* 2B /dr */ { 0, &BX_CPU_C::SUB_GdEd },
/* 2C /dr */ { BxImmediate_Ib, &BX_CPU_C::SUB_ALIb },
/* 2D /dr */ { BxImmediate_Iv, &BX_CPU_C::SUB_EAXId },
/* 2E /dr */ { BxPrefix, &BX_CPU_C::BxError }, // CS:
/* 2F /dr */ { 0, &BX_CPU_C::DAS },
/* 30 /dr */ { BxLockable, &BX_CPU_C::XOR_EbGbR },
/* 31 /dr */ { BxLockable, &BX_CPU_C::XOR_EdGdR },
/* 30 /dr */ { 0, &BX_CPU_C::XOR_EbGbR },
/* 31 /dr */ { 0, &BX_CPU_C::XOR_EdGdR },
/* 32 /dr */ { 0, &BX_CPU_C::XOR_GbEb },
/* 33 /dr */ { 0, &BX_CPU_C::XOR_GdEd },
/* 34 /dr */ { BxImmediate_Ib, &BX_CPU_C::XOR_ALIb },
@ -862,8 +862,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 83 /dr */ { BxGroup1 | BxImmediate_Ib_SE, NULL, BxOpcodeInfoG1EdR },
/* 84 /dr */ { 0, &BX_CPU_C::TEST_EbGbR },
/* 85 /dr */ { 0, &BX_CPU_C::TEST_EdGdR },
/* 86 /dr */ { BxLockable, &BX_CPU_C::XCHG_EbGb },
/* 87 /dr */ { BxLockable, &BX_CPU_C::XCHG_EdGdR },
/* 86 /dr */ { 0, &BX_CPU_C::XCHG_EbGbR },
/* 87 /dr */ { 0, &BX_CPU_C::XCHG_EdGdR },
/* 88 /dr */ { 0, &BX_CPU_C::MOV_EbGbR },
/* 89 /dr */ { 0, &BX_CPU_C::MOV_EdGdR },
/* 8A /dr */ { 0, &BX_CPU_C::MOV_GbEbR },
@ -1205,15 +1205,15 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F A8 /dr */ { 0, &BX_CPU_C::PUSH32_GS },
/* 0F A9 /dr */ { 0, &BX_CPU_C::POP32_GS },
/* 0F AA /dr */ { 0, &BX_CPU_C::RSM },
/* 0F AB /dr */ { BxLockable, &BX_CPU_C::BTS_EdGdR },
/* 0F AB /dr */ { 0, &BX_CPU_C::BTS_EdGdR },
/* 0F AC /dr */ { BxImmediate_Ib, &BX_CPU_C::SHRD_EdGd },
/* 0F AD /dr */ { 0, &BX_CPU_C::SHRD_EdGd },
/* 0F AE /dr */ { BxGroup15, NULL, BxOpcodeInfoG15R },
/* 0F AF /dr */ { 0, &BX_CPU_C::IMUL_GdEd },
/* 0F B0 /dr */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 /dr */ { BxLockable, &BX_CPU_C::CMPXCHG_EdGd },
/* 0F B0 /dr */ { 0, &BX_CPU_C::CMPXCHG_EbGbR },
/* 0F B1 /dr */ { 0, &BX_CPU_C::CMPXCHG_EdGdR },
/* 0F B2 /dr */ { 0, &BX_CPU_C::BxError }, // LSS
/* 0F B3 /dr */ { BxLockable, &BX_CPU_C::BTR_EdGdR },
/* 0F B3 /dr */ { 0, &BX_CPU_C::BTR_EdGdR },
/* 0F B4 /dr */ { 0, &BX_CPU_C::BxError }, // LFS
/* 0F B5 /dr */ { 0, &BX_CPU_C::BxError }, // LGS
/* 0F B6 /dr */ { 0, &BX_CPU_C::MOVZX_GdEbR },
@ -1221,13 +1221,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F B8 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fb8d },
/* 0F B9 /dr */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F BA /dr */ { BxGroup8, NULL, BxOpcodeInfoG8EdIb },
/* 0F BB /dr */ { BxLockable, &BX_CPU_C::BTC_EdGdR },
/* 0F BB /dr */ { 0, &BX_CPU_C::BTC_EdGdR },
/* 0F BC /dr */ { 0, &BX_CPU_C::BSF_GdEd },
/* 0F BD /dr */ { 0, &BX_CPU_C::BSR_GdEd },
/* 0F BE /dr */ { 0, &BX_CPU_C::MOVSX_GdEbR },
/* 0F BF /dr */ { 0, &BX_CPU_C::MOVSX_GdEwR },
/* 0F C0 /dr */ { BxLockable, &BX_CPU_C::XADD_EbGb },
/* 0F C1 /dr */ { BxLockable, &BX_CPU_C::XADD_EdGd },
/* 0F C0 /dr */ { 0, &BX_CPU_C::XADD_EbGbR },
/* 0F C1 /dr */ { 0, &BX_CPU_C::XADD_EdGdR },
/* 0F C2 /dr */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
/* 0F C3 /dr */ { 0, &BX_CPU_C::BxError }, // MOVNTI SSE group
/* 0F C4 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
@ -1433,7 +1433,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 83 /wm */ { BxGroup1 | BxImmediate_Ib_SE, NULL, BxOpcodeInfoG1EwM },
/* 84 /wm */ { 0, &BX_CPU_C::TEST_EbGbM },
/* 85 /wm */ { 0, &BX_CPU_C::TEST_EwGwM },
/* 86 /wm */ { BxLockable, &BX_CPU_C::XCHG_EbGb },
/* 86 /wm */ { BxLockable, &BX_CPU_C::XCHG_EbGbM },
/* 87 /wm */ { BxLockable, &BX_CPU_C::XCHG_EwGw },
/* 88 /wm */ { 0, &BX_CPU_C::MOV_EbGbM },
/* 89 /wm */ { 0, &BX_CPU_C::MOV_EwGwM },
@ -1768,7 +1768,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F A0 /wm */ { 0, &BX_CPU_C::PUSH16_FS },
/* 0F A1 /wm */ { 0, &BX_CPU_C::POP16_FS },
/* 0F A2 /wm */ { 0, &BX_CPU_C::CPUID },
/* 0F A3 /wm */ { 0, &BX_CPU_C::BT_EwGw },
/* 0F A3 /wm */ { 0, &BX_CPU_C::BT_EwGwM },
/* 0F A4 /wm */ { BxImmediate_Ib, &BX_CPU_C::SHLD_EwGw },
/* 0F A5 /wm */ { 0, &BX_CPU_C::SHLD_EwGw },
/* 0F A6 /wm */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
@ -1776,15 +1776,15 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F A8 /wm */ { 0, &BX_CPU_C::PUSH16_GS },
/* 0F A9 /wm */ { 0, &BX_CPU_C::POP16_GS },
/* 0F AA /wm */ { 0, &BX_CPU_C::RSM },
/* 0F AB /wm */ { BxLockable, &BX_CPU_C::BTS_EwGw },
/* 0F AB /wm */ { BxLockable, &BX_CPU_C::BTS_EwGwM },
/* 0F AC /wm */ { BxImmediate_Ib, &BX_CPU_C::SHRD_EwGw },
/* 0F AD /wm */ { 0, &BX_CPU_C::SHRD_EwGw },
/* 0F AE /wm */ { BxGroup15, NULL, BxOpcodeInfoG15M },
/* 0F AF /wm */ { 0, &BX_CPU_C::IMUL_GwEw },
/* 0F B0 /wm */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 /wm */ { BxLockable, &BX_CPU_C::CMPXCHG_EwGw },
/* 0F B0 /wm */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGbM },
/* 0F B1 /wm */ { BxLockable, &BX_CPU_C::CMPXCHG_EwGwM },
/* 0F B2 /wm */ { 0, &BX_CPU_C::LSS_GwMp },
/* 0F B3 /wm */ { BxLockable, &BX_CPU_C::BTR_EwGw },
/* 0F B3 /wm */ { BxLockable, &BX_CPU_C::BTR_EwGwM },
/* 0F B4 /wm */ { 0, &BX_CPU_C::LFS_GwMp },
/* 0F B5 /wm */ { 0, &BX_CPU_C::LGS_GwMp },
/* 0F B6 /wm */ { 0, &BX_CPU_C::MOVZX_GwEbM },
@ -1792,13 +1792,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F B8 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fb8w },
/* 0F B9 /wm */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F BA /wm */ { BxGroup8, NULL, BxOpcodeInfoG8EwIb },
/* 0F BB /wm */ { BxLockable, &BX_CPU_C::BTC_EwGw },
/* 0F BB /wm */ { BxLockable, &BX_CPU_C::BTC_EwGwM },
/* 0F BC /wm */ { 0, &BX_CPU_C::BSF_GwEw },
/* 0F BD /wm */ { 0, &BX_CPU_C::BSR_GwEw },
/* 0F BE /wm */ { 0, &BX_CPU_C::MOVSX_GwEbM },
/* 0F BF /wm */ { 0, &BX_CPU_C::MOV_GwEwM }, // MOVSX_GwEw
/* 0F C0 /wm */ { BxLockable, &BX_CPU_C::XADD_EbGb },
/* 0F C1 /wm */ { BxLockable, &BX_CPU_C::XADD_EwGw },
/* 0F C0 /wm */ { BxLockable, &BX_CPU_C::XADD_EbGbM },
/* 0F C1 /wm */ { BxLockable, &BX_CPU_C::XADD_EwGwM },
/* 0F C2 /wm */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
/* 0F C3 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc3M },
/* 0F C4 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
@ -1997,7 +1997,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 83 /dm */ { BxGroup1 | BxImmediate_Ib_SE, NULL, BxOpcodeInfoG1EdM },
/* 84 /dm */ { 0, &BX_CPU_C::TEST_EbGbM },
/* 85 /dm */ { 0, &BX_CPU_C::TEST_EdGdM },
/* 86 /dm */ { BxLockable, &BX_CPU_C::XCHG_EbGb },
/* 86 /dm */ { BxLockable, &BX_CPU_C::XCHG_EbGbM },
/* 87 /dm */ { BxLockable, &BX_CPU_C::XCHG_EdGdM },
/* 88 /dm */ { 0, &BX_CPU_C::MOV_EbGbM },
/* 89 /dm */ { 0, &BX_CPU_C::MOV_EdGdM },
@ -2345,8 +2345,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F AD /dm */ { 0, &BX_CPU_C::SHRD_EdGd },
/* 0F AE /dm */ { BxGroup15, NULL, BxOpcodeInfoG15M },
/* 0F AF /dm */ { 0, &BX_CPU_C::IMUL_GdEd },
/* 0F B0 /dm */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 /dm */ { BxLockable, &BX_CPU_C::CMPXCHG_EdGd },
/* 0F B0 /dm */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGbM },
/* 0F B1 /dm */ { BxLockable, &BX_CPU_C::CMPXCHG_EdGdM },
/* 0F B2 /dm */ { 0, &BX_CPU_C::LSS_GdMp },
/* 0F B3 /dm */ { BxLockable, &BX_CPU_C::BTR_EdGdM },
/* 0F B4 /dm */ { 0, &BX_CPU_C::LFS_GdMp },
@ -2361,8 +2361,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F BD /dm */ { 0, &BX_CPU_C::BSR_GdEd },
/* 0F BE /dm */ { 0, &BX_CPU_C::MOVSX_GdEbM },
/* 0F BF /dm */ { 0, &BX_CPU_C::MOVSX_GdEwM },
/* 0F C0 /dm */ { BxLockable, &BX_CPU_C::XADD_EbGb },
/* 0F C1 /dm */ { BxLockable, &BX_CPU_C::XADD_EdGd },
/* 0F C0 /dm */ { BxLockable, &BX_CPU_C::XADD_EbGbM },
/* 0F C1 /dm */ { BxLockable, &BX_CPU_C::XADD_EdGdM },
/* 0F C2 /dm */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
/* 0F C3 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc3M },
/* 0F C4 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
@ -2793,7 +2793,8 @@ modrm_done:
if (lock) { // lock prefix invalid opcode
// lock prefix not allowed or destination operand is not memory
if ((mod == 0xc0) || !(attr & BxLockable)) {
// only memory destination is marked BxLockable
if (/*(mod == 0xc0) || */ !(attr & BxLockable)) {
BX_INFO(("LOCK prefix unallowed (op1=0x%x, attr=0x%x, mod=0x%x, nnn=%u)", b1, attr, mod, nnn));
UndefinedOpcode(instruction);
}
@ -2940,9 +2941,9 @@ modrm_done:
void BX_CPU_C::BxError(bxInstruction_c *i)
{
BX_INFO(("BxError: instruction with opcode=0x%x", i->b1()));
BX_INFO(("mod was %x, nnn was %u, rm was %u", i->mod(), i->nnn(), i->rm()));
BX_INFO(("WARNING: Encountered an unknown instruction (signalling illegal instruction)"));
BX_DEBUG(("BxError: instruction with opcode=0x%x", i->b1()));
BX_DEBUG(("mod was %x, nnn was %u, rm was %u", i->mod(), i->nnn(), i->rm()));
BX_DEBUG(("WARNING: Encountered an unknown instruction (signalling illegal instruction)"));
BX_CPU_THIS_PTR UndefinedOpcode(i);
}

245
bochs/cpu/fetchdecode64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode64.cc,v 1.136 2007-11-17 23:28:31 sshwarts Exp $
// $Id: fetchdecode64.cc,v 1.137 2007-11-18 18:24:45 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -211,56 +211,56 @@ static BxExecutePtr_tR Resolve64Mod0BaseIndex[16] = {
static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
// 512 entries for 16bit operand size
/* 00 /wr */ { BxLockable, &BX_CPU_C::ADD_EbGbR },
/* 01 /wr */ { BxLockable, &BX_CPU_C::ADD_EwGwR },
/* 00 /wr */ { 0, &BX_CPU_C::ADD_EbGbR },
/* 01 /wr */ { 0, &BX_CPU_C::ADD_EwGwR },
/* 02 /wr */ { 0, &BX_CPU_C::ADD_GbEb },
/* 03 /wr */ { 0, &BX_CPU_C::ADD_GwEwR },
/* 04 /wr */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
/* 05 /wr */ { BxImmediate_Iv, &BX_CPU_C::ADD_AXIw },
/* 06 /wr */ { 0, &BX_CPU_C::BxError },
/* 07 /wr */ { 0, &BX_CPU_C::BxError },
/* 08 /wr */ { BxLockable, &BX_CPU_C::OR_EbGbR },
/* 09 /wr */ { BxLockable, &BX_CPU_C::OR_EwGwR },
/* 08 /wr */ { 0, &BX_CPU_C::OR_EbGbR },
/* 09 /wr */ { 0, &BX_CPU_C::OR_EwGwR },
/* 0A /wr */ { 0, &BX_CPU_C::OR_GbEb },
/* 0B /wr */ { 0, &BX_CPU_C::OR_GwEw },
/* 0C /wr */ { BxImmediate_Ib, &BX_CPU_C::OR_ALIb },
/* 0D /wr */ { BxImmediate_Iv, &BX_CPU_C::OR_AXIw },
/* 0E /wr */ { 0, &BX_CPU_C::BxError },
/* 0F /wr */ { 0, &BX_CPU_C::BxError }, // 2-byte escape
/* 10 /wr */ { BxLockable, &BX_CPU_C::ADC_EbGbR },
/* 11 /wr */ { BxLockable, &BX_CPU_C::ADC_EwGwR },
/* 10 /wr */ { 0, &BX_CPU_C::ADC_EbGbR },
/* 11 /wr */ { 0, &BX_CPU_C::ADC_EwGwR },
/* 12 /wr */ { 0, &BX_CPU_C::ADC_GbEb },
/* 13 /wr */ { 0, &BX_CPU_C::ADC_GwEw },
/* 14 /wr */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
/* 15 /wr */ { BxImmediate_Iv, &BX_CPU_C::ADC_AXIw },
/* 16 /wr */ { 0, &BX_CPU_C::BxError },
/* 17 /wr */ { 0, &BX_CPU_C::BxError },
/* 18 /wr */ { BxLockable, &BX_CPU_C::SBB_EbGbR },
/* 19 /wr */ { BxLockable, &BX_CPU_C::SBB_EwGwR },
/* 18 /wr */ { 0, &BX_CPU_C::SBB_EbGbR },
/* 19 /wr */ { 0, &BX_CPU_C::SBB_EwGwR },
/* 1A /wr */ { 0, &BX_CPU_C::SBB_GbEb },
/* 1B /wr */ { 0, &BX_CPU_C::SBB_GwEw },
/* 1C /wr */ { BxImmediate_Ib, &BX_CPU_C::SBB_ALIb },
/* 1D /wr */ { BxImmediate_Iv, &BX_CPU_C::SBB_AXIw },
/* 1E /wr */ { 0, &BX_CPU_C::BxError },
/* 1F /wr */ { 0, &BX_CPU_C::BxError },
/* 20 /wr */ { BxLockable, &BX_CPU_C::AND_EbGbR },
/* 21 /wr */ { BxLockable, &BX_CPU_C::AND_EwGwR },
/* 20 /wr */ { 0, &BX_CPU_C::AND_EbGbR },
/* 21 /wr */ { 0, &BX_CPU_C::AND_EwGwR },
/* 22 /wr */ { 0, &BX_CPU_C::AND_GbEb },
/* 23 /wr */ { 0, &BX_CPU_C::AND_GwEw },
/* 24 /wr */ { BxImmediate_Ib, &BX_CPU_C::AND_ALIb },
/* 25 /wr */ { BxImmediate_Iv, &BX_CPU_C::AND_AXIw },
/* 26 /wr */ { BxPrefix, &BX_CPU_C::BxError }, // ES:
/* 27 /wr */ { 0, &BX_CPU_C::BxError },
/* 28 /wr */ { BxLockable, &BX_CPU_C::SUB_EbGbR },
/* 29 /wr */ { BxLockable, &BX_CPU_C::SUB_EwGwR },
/* 28 /wr */ { 0, &BX_CPU_C::SUB_EbGbR },
/* 29 /wr */ { 0, &BX_CPU_C::SUB_EwGwR },
/* 2A /wr */ { 0, &BX_CPU_C::SUB_GbEb },
/* 2B /wr */ { 0, &BX_CPU_C::SUB_GwEw },
/* 2C /wr */ { BxImmediate_Ib, &BX_CPU_C::SUB_ALIb },
/* 2D /wr */ { BxImmediate_Iv, &BX_CPU_C::SUB_AXIw },
/* 2E /wr */ { BxPrefix, &BX_CPU_C::BxError }, // CS:
/* 2F /wr */ { 0, &BX_CPU_C::BxError },
/* 30 /wr */ { BxLockable, &BX_CPU_C::XOR_EbGbR },
/* 31 /wr */ { BxLockable, &BX_CPU_C::XOR_EwGwR },
/* 30 /wr */ { 0, &BX_CPU_C::XOR_EbGbR },
/* 31 /wr */ { 0, &BX_CPU_C::XOR_EwGwR },
/* 32 /wr */ { 0, &BX_CPU_C::XOR_GbEb },
/* 33 /wr */ { 0, &BX_CPU_C::XOR_GwEw },
/* 34 /wr */ { BxImmediate_Ib, &BX_CPU_C::XOR_ALIb },
@ -345,8 +345,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 83 /wr */ { BxGroup1 | BxImmediate_Ib_SE, NULL, BxOpcodeInfoG1EwR },
/* 84 /wr */ { 0, &BX_CPU_C::TEST_EbGbR },
/* 85 /wr */ { 0, &BX_CPU_C::TEST_EwGwR },
/* 86 /wr */ { BxLockable, &BX_CPU_C::XCHG_EbGb },
/* 87 /wr */ { BxLockable, &BX_CPU_C::XCHG_EwGw },
/* 86 /wr */ { 0, &BX_CPU_C::XCHG_EbGbR },
/* 87 /wr */ { 0, &BX_CPU_C::XCHG_EwGw },
/* 88 /wr */ { 0, &BX_CPU_C::MOV_EbGbR },
/* 89 /wr */ { 0, &BX_CPU_C::MOV_EwGwR },
/* 8A /wr */ { 0, &BX_CPU_C::MOV_GbEbR },
@ -645,7 +645,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 0F A0 /wr */ { 0, &BX_CPU_C::PUSH16_FS },
/* 0F A1 /wr */ { 0, &BX_CPU_C::POP16_FS },
/* 0F A2 /wr */ { 0, &BX_CPU_C::CPUID },
/* 0F A3 /wr */ { 0, &BX_CPU_C::BT_EwGw },
/* 0F A3 /wr */ { 0, &BX_CPU_C::BT_EwGwR },
/* 0F A4 /wr */ { BxImmediate_Ib, &BX_CPU_C::SHLD_EwGw },
/* 0F A5 /wr */ { 0, &BX_CPU_C::SHLD_EwGw },
/* 0F A6 /wr */ { 0, &BX_CPU_C::BxError },
@ -653,15 +653,15 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 0F A8 /wr */ { 0, &BX_CPU_C::PUSH16_GS },
/* 0F A9 /wr */ { 0, &BX_CPU_C::POP16_GS },
/* 0F AA /wr */ { 0, &BX_CPU_C::RSM },
/* 0F AB /wr */ { BxLockable, &BX_CPU_C::BTS_EwGw },
/* 0F AB /wr */ { 0, &BX_CPU_C::BTS_EwGwR },
/* 0F AC /wr */ { BxImmediate_Ib, &BX_CPU_C::SHRD_EwGw },
/* 0F AD /wr */ { 0, &BX_CPU_C::SHRD_EwGw },
/* 0F AE /wr */ { BxGroup15, NULL, BxOpcodeInfoG15R },
/* 0F AF /wr */ { 0, &BX_CPU_C::IMUL_GwEw },
/* 0F B0 /wr */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 /wr */ { BxLockable, &BX_CPU_C::CMPXCHG_EwGw },
/* 0F B0 /wr */ { 0, &BX_CPU_C::CMPXCHG_EbGbR },
/* 0F B1 /wr */ { 0, &BX_CPU_C::CMPXCHG_EwGwR },
/* 0F B2 /wr */ { 0, &BX_CPU_C::BxError }, // LSS
/* 0F B3 /wr */ { BxLockable, &BX_CPU_C::BTR_EwGw },
/* 0F B3 /wr */ { 0, &BX_CPU_C::BTR_EwGwR },
/* 0F B4 /wr */ { 0, &BX_CPU_C::BxError }, // LFS
/* 0F B5 /wr */ { 0, &BX_CPU_C::BxError }, // LGS
/* 0F B6 /wr */ { 0, &BX_CPU_C::MOVZX_GwEbR },
@ -669,13 +669,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 0F B8 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fb8w },
/* 0F B9 /wr */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F BA /wr */ { BxGroup8, NULL, BxOpcodeInfoG8EwIb },
/* 0F BB /wr */ { BxLockable, &BX_CPU_C::BTC_EwGw },
/* 0F BB /wr */ { 0, &BX_CPU_C::BTC_EwGwR },
/* 0F BC /wr */ { 0, &BX_CPU_C::BSF_GwEw },
/* 0F BD /wr */ { 0, &BX_CPU_C::BSR_GwEw },
/* 0F BE /wr */ { 0, &BX_CPU_C::MOVSX_GwEbR },
/* 0F BF /wr */ { 0, &BX_CPU_C::MOV_GwEwR }, // MOVSX_GwEw
/* 0F C0 /wr */ { BxLockable, &BX_CPU_C::XADD_EbGb },
/* 0F C1 /wr */ { BxLockable, &BX_CPU_C::XADD_EwGw },
/* 0F C0 /wr */ { 0, &BX_CPU_C::XADD_EbGbR },
/* 0F C1 /wr */ { 0, &BX_CPU_C::XADD_EwGwR },
/* 0F C2 /wr */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
/* 0F C3 /wr */ { 0, &BX_CPU_C::BxError }, // MOVNTI SSE group
/* 0F C4 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
@ -740,56 +740,56 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 0F FF /wr */ { 0, &BX_CPU_C::BxError },
// 512 entries for 32bit operand size
/* 00 /dr */ { BxLockable, &BX_CPU_C::ADD_EbGbR },
/* 01 /dr */ { BxLockable, &BX_CPU_C::ADD_EdGdR },
/* 00 /dr */ { 0, &BX_CPU_C::ADD_EbGbR },
/* 01 /dr */ { 0, &BX_CPU_C::ADD_EdGdR },
/* 02 /dr */ { 0, &BX_CPU_C::ADD_GbEb },
/* 03 /dr */ { 0, &BX_CPU_C::ADD_GdEdR },
/* 04 /dr */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
/* 05 /dr */ { BxImmediate_Iv, &BX_CPU_C::ADD_EAXId },
/* 06 /dr */ { 0, &BX_CPU_C::BxError },
/* 07 /dr */ { 0, &BX_CPU_C::BxError },
/* 08 /dr */ { BxLockable, &BX_CPU_C::OR_EbGbR },
/* 09 /dr */ { BxLockable, &BX_CPU_C::OR_EdGdR },
/* 08 /dr */ { 0, &BX_CPU_C::OR_EbGbR },
/* 09 /dr */ { 0, &BX_CPU_C::OR_EdGdR },
/* 0A /dr */ { 0, &BX_CPU_C::OR_GbEb },
/* 0B /dr */ { 0, &BX_CPU_C::OR_GdEd },
/* 0C /dr */ { BxImmediate_Ib, &BX_CPU_C::OR_ALIb },
/* 0D /dr */ { BxImmediate_Iv, &BX_CPU_C::OR_EAXId },
/* 0E /dr */ { 0, &BX_CPU_C::BxError },
/* 0F /dr */ { 0, &BX_CPU_C::BxError }, // 2-byte escape
/* 10 /dr */ { BxLockable, &BX_CPU_C::ADC_EbGbR },
/* 11 /dr */ { BxLockable, &BX_CPU_C::ADC_EdGdR },
/* 10 /dr */ { 0, &BX_CPU_C::ADC_EbGbR },
/* 11 /dr */ { 0, &BX_CPU_C::ADC_EdGdR },
/* 12 /dr */ { 0, &BX_CPU_C::ADC_GbEb },
/* 13 /dr */ { 0, &BX_CPU_C::ADC_GdEd },
/* 14 /dr */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
/* 15 /dr */ { BxImmediate_Iv, &BX_CPU_C::ADC_EAXId },
/* 16 /dr */ { 0, &BX_CPU_C::BxError },
/* 17 /dr */ { 0, &BX_CPU_C::BxError },
/* 18 /dr */ { BxLockable, &BX_CPU_C::SBB_EbGbR },
/* 19 /dr */ { BxLockable, &BX_CPU_C::SBB_EdGdR },
/* 18 /dr */ { 0, &BX_CPU_C::SBB_EbGbR },
/* 19 /dr */ { 0, &BX_CPU_C::SBB_EdGdR },
/* 1A /dr */ { 0, &BX_CPU_C::SBB_GbEb },
/* 1B /dr */ { 0, &BX_CPU_C::SBB_GdEd },
/* 1C /dr */ { BxImmediate_Ib, &BX_CPU_C::SBB_ALIb },
/* 1D /dr */ { BxImmediate_Iv, &BX_CPU_C::SBB_EAXId },
/* 1E /dr */ { 0, &BX_CPU_C::BxError },
/* 1F /dr */ { 0, &BX_CPU_C::BxError },
/* 20 /dr */ { BxLockable, &BX_CPU_C::AND_EbGbR },
/* 21 /dr */ { BxLockable, &BX_CPU_C::AND_EdGdR },
/* 20 /dr */ { 0, &BX_CPU_C::AND_EbGbR },
/* 21 /dr */ { 0, &BX_CPU_C::AND_EdGdR },
/* 22 /dr */ { 0, &BX_CPU_C::AND_GbEb },
/* 23 /dr */ { 0, &BX_CPU_C::AND_GdEd },
/* 24 /dr */ { BxImmediate_Ib, &BX_CPU_C::AND_ALIb },
/* 25 /dr */ { BxImmediate_Iv, &BX_CPU_C::AND_EAXId },
/* 26 /dr */ { BxPrefix, &BX_CPU_C::BxError }, // ES:
/* 27 /dr */ { 0, &BX_CPU_C::BxError },
/* 28 /dr */ { BxLockable, &BX_CPU_C::SUB_EbGbR },
/* 29 /dr */ { BxLockable, &BX_CPU_C::SUB_EdGdR },
/* 28 /dr */ { 0, &BX_CPU_C::SUB_EbGbR },
/* 29 /dr */ { 0, &BX_CPU_C::SUB_EdGdR },
/* 2A /dr */ { 0, &BX_CPU_C::SUB_GbEb },
/* 2B /dr */ { 0, &BX_CPU_C::SUB_GdEd },
/* 2C /dr */ { BxImmediate_Ib, &BX_CPU_C::SUB_ALIb },
/* 2D /dr */ { BxImmediate_Iv, &BX_CPU_C::SUB_EAXId },
/* 2E /dr */ { BxPrefix, &BX_CPU_C::BxError }, // CS:
/* 2F /dr */ { 0, &BX_CPU_C::BxError },
/* 30 /dr */ { BxLockable, &BX_CPU_C::XOR_EbGbR },
/* 31 /dr */ { BxLockable, &BX_CPU_C::XOR_EdGdR },
/* 30 /dr */ { 0, &BX_CPU_C::XOR_EbGbR },
/* 31 /dr */ { 0, &BX_CPU_C::XOR_EdGdR },
/* 32 /dr */ { 0, &BX_CPU_C::XOR_GbEb },
/* 33 /dr */ { 0, &BX_CPU_C::XOR_GdEd },
/* 34 /dr */ { BxImmediate_Ib, &BX_CPU_C::XOR_ALIb },
@ -874,8 +874,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 83 /dr */ { BxGroup5 | BxImmediate_Ib_SE, NULL, BxOpcodeInfoG1EdR },
/* 84 /dr */ { 0, &BX_CPU_C::TEST_EbGbR },
/* 85 /dr */ { 0, &BX_CPU_C::TEST_EdGdR },
/* 86 /dr */ { BxLockable, &BX_CPU_C::XCHG_EbGb },
/* 87 /dr */ { BxLockable, &BX_CPU_C::XCHG_EdGdR },
/* 86 /dr */ { 0, &BX_CPU_C::XCHG_EbGbR },
/* 87 /dr */ { 0, &BX_CPU_C::XCHG_EdGdR },
/* 88 /dr */ { 0, &BX_CPU_C::MOV_EbGbR },
/* 89 /dr */ { 0, &BX_CPU_C::MOV_EdGdR },
/* 8A /dr */ { 0, &BX_CPU_C::MOV_GbEbR },
@ -1182,15 +1182,15 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 0F A8 /dr */ { 0, &BX_CPU_C::PUSH64_GS },
/* 0F A9 /dr */ { 0, &BX_CPU_C::POP64_GS },
/* 0F AA /dr */ { 0, &BX_CPU_C::RSM },
/* 0F AB /dr */ { BxLockable, &BX_CPU_C::BTS_EdGdR },
/* 0F AB /dr */ { 0, &BX_CPU_C::BTS_EdGdR },
/* 0F AC /dr */ { BxImmediate_Ib, &BX_CPU_C::SHRD_EdGd },
/* 0F AD /dr */ { 0, &BX_CPU_C::SHRD_EdGd },
/* 0F AE /dr */ { BxGroup15, NULL, BxOpcodeInfoG15R },
/* 0F AF /dr */ { 0, &BX_CPU_C::IMUL_GdEd },
/* 0F B0 /dr */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 /dr */ { BxLockable, &BX_CPU_C::CMPXCHG_EdGd },
/* 0F B0 /dr */ { 0, &BX_CPU_C::CMPXCHG_EbGbR },
/* 0F B1 /dr */ { 0, &BX_CPU_C::CMPXCHG_EdGdR },
/* 0F B2 /dr */ { 0, &BX_CPU_C::BxError }, // LSS
/* 0F B3 /dr */ { BxLockable, &BX_CPU_C::BTR_EdGdR },
/* 0F B3 /dr */ { 0, &BX_CPU_C::BTR_EdGdR },
/* 0F B4 /dr */ { 0, &BX_CPU_C::BxError }, // LFS
/* 0F B5 /dr */ { 0, &BX_CPU_C::BxError }, // LFS
/* 0F B6 /dr */ { 0, &BX_CPU_C::MOVZX_GdEbR },
@ -1198,13 +1198,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 0F B8 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fb8d },
/* 0F B9 /dr */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F BA /dr */ { BxGroup8, NULL, BxOpcodeInfoG8EdIb },
/* 0F BB /dr */ { BxLockable, &BX_CPU_C::BTC_EdGdR },
/* 0F BB /dr */ { 0, &BX_CPU_C::BTC_EdGdR },
/* 0F BC /dr */ { 0, &BX_CPU_C::BSF_GdEd },
/* 0F BD /dr */ { 0, &BX_CPU_C::BSR_GdEd },
/* 0F BE /dr */ { 0, &BX_CPU_C::MOVSX_GdEbR },
/* 0F BF /dr */ { 0, &BX_CPU_C::MOVSX_GdEwR },
/* 0F C0 /dr */ { BxLockable, &BX_CPU_C::XADD_EbGb },
/* 0F C1 /dr */ { BxLockable, &BX_CPU_C::XADD_EdGd },
/* 0F C0 /dr */ { 0, &BX_CPU_C::XADD_EbGbR },
/* 0F C1 /dr */ { 0, &BX_CPU_C::XADD_EdGdR },
/* 0F C2 /dr */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
/* 0F C3 /dr */ { 0, &BX_CPU_C::BxError }, // MOVNTI SSE group
/* 0F C4 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
@ -1269,8 +1269,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 0F FF /dr */ { 0, &BX_CPU_C::BxError },
// 512 entries for 64bit operand size
/* 00 /qr */ { BxLockable, &BX_CPU_C::ADD_EbGbR },
/* 01 /qr */ { BxLockable, &BX_CPU_C::ADD_EqGq },
/* 00 /qr */ { 0, &BX_CPU_C::ADD_EbGbR },
/* 01 /qr */ { 0, &BX_CPU_C::ADD_EqGqR },
/* 02 /qr */ { 0, &BX_CPU_C::ADD_GbEb },
/* 03 /qr */ { 0, &BX_CPU_C::ADD_GqEq },
/* 04 /qr */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
@ -1278,47 +1278,47 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 06 /qr */ { 0, &BX_CPU_C::BxError },
/* 07 /qr */ { 0, &BX_CPU_C::BxError },
/* 08 /qr */ { 0, &BX_CPU_C::OR_EbGbR },
/* 09 /qr */ { BxLockable, &BX_CPU_C::OR_EqGq },
/* 0A /qr */ { BxLockable, &BX_CPU_C::OR_GbEb },
/* 09 /qr */ { 0, &BX_CPU_C::OR_EqGqR },
/* 0A /qr */ { 0, &BX_CPU_C::OR_GbEb },
/* 0B /qr */ { 0, &BX_CPU_C::OR_GqEq },
/* 0C /qr */ { BxImmediate_Ib, &BX_CPU_C::OR_ALIb },
/* 0D /qr */ { BxImmediate_Iv, &BX_CPU_C::OR_RAXId },
/* 0E /qr */ { 0, &BX_CPU_C::BxError },
/* 0F /qr */ { 0, &BX_CPU_C::BxError }, // 2-byte escape
/* 10 /qr */ { BxLockable, &BX_CPU_C::ADC_EbGbR },
/* 11 /qr */ { BxLockable, &BX_CPU_C::ADC_EqGq },
/* 10 /qr */ { 0, &BX_CPU_C::ADC_EbGbR },
/* 11 /qr */ { 0, &BX_CPU_C::ADC_EqGqR },
/* 12 /qr */ { 0, &BX_CPU_C::ADC_GbEb },
/* 13 /qr */ { 0, &BX_CPU_C::ADC_GqEq },
/* 14 /qr */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
/* 15 /qr */ { BxImmediate_Iv, &BX_CPU_C::ADC_RAXId },
/* 16 /qr */ { 0, &BX_CPU_C::BxError },
/* 17 /qr */ { 0, &BX_CPU_C::BxError },
/* 18 /qr */ { BxLockable, &BX_CPU_C::SBB_EbGbR },
/* 19 /qr */ { BxLockable, &BX_CPU_C::SBB_EqGq },
/* 18 /qr */ { 0, &BX_CPU_C::SBB_EbGbR },
/* 19 /qr */ { 0, &BX_CPU_C::SBB_EqGqR },
/* 1A /qr */ { 0, &BX_CPU_C::SBB_GbEb },
/* 1B /qr */ { 0, &BX_CPU_C::SBB_GqEq },
/* 1C /qr */ { BxImmediate_Ib, &BX_CPU_C::SBB_ALIb },
/* 1D /qr */ { BxImmediate_Iv, &BX_CPU_C::SBB_RAXId },
/* 1E /qr */ { 0, &BX_CPU_C::BxError },
/* 1F /qr */ { 0, &BX_CPU_C::BxError },
/* 20 /qr */ { BxLockable, &BX_CPU_C::AND_EbGbR },
/* 21 /qr */ { BxLockable, &BX_CPU_C::AND_EqGq },
/* 20 /qr */ { 0, &BX_CPU_C::AND_EbGbR },
/* 21 /qr */ { 0, &BX_CPU_C::AND_EqGqR },
/* 22 /qr */ { 0, &BX_CPU_C::AND_GbEb },
/* 23 /qr */ { 0, &BX_CPU_C::AND_GqEq },
/* 24 /qr */ { BxImmediate_Ib, &BX_CPU_C::AND_ALIb },
/* 25 /qr */ { BxImmediate_Iv, &BX_CPU_C::AND_RAXId },
/* 26 /qr */ { BxPrefix, &BX_CPU_C::BxError }, // ES:
/* 27 /qr */ { 0, &BX_CPU_C::BxError },
/* 28 /qr */ { BxLockable, &BX_CPU_C::SUB_EbGbR },
/* 29 /qr */ { BxLockable, &BX_CPU_C::SUB_EqGq },
/* 28 /qr */ { 0, &BX_CPU_C::SUB_EbGbR },
/* 29 /qr */ { 0, &BX_CPU_C::SUB_EqGqR },
/* 2A /qr */ { 0, &BX_CPU_C::SUB_GbEb },
/* 2B /qr */ { 0, &BX_CPU_C::SUB_GqEq },
/* 2C /qr */ { BxImmediate_Ib, &BX_CPU_C::SUB_ALIb },
/* 2D /qr */ { BxImmediate_Iv, &BX_CPU_C::SUB_RAXId },
/* 2E /qr */ { BxPrefix, &BX_CPU_C::BxError }, // CS:
/* 2F /qr */ { 0, &BX_CPU_C::BxError },
/* 30 /qr */ { BxLockable, &BX_CPU_C::XOR_EbGbR },
/* 31 /qr */ { BxLockable, &BX_CPU_C::XOR_EqGq },
/* 30 /qr */ { 0, &BX_CPU_C::XOR_EbGbR },
/* 31 /qr */ { 0, &BX_CPU_C::XOR_EqGqR },
/* 32 /qr */ { 0, &BX_CPU_C::XOR_GbEb },
/* 33 /qr */ { 0, &BX_CPU_C::XOR_GqEq },
/* 34 /qr */ { BxImmediate_Ib, &BX_CPU_C::XOR_ALIb },
@ -1326,7 +1326,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 36 /qr */ { BxPrefix, &BX_CPU_C::BxError }, // SS:
/* 37 /qr */ { 0, &BX_CPU_C::BxError },
/* 38 /qr */ { 0, &BX_CPU_C::CMP_EbGbR },
/* 39 /qr */ { 0, &BX_CPU_C::CMP_EqGq },
/* 39 /qr */ { 0, &BX_CPU_C::CMP_EqGqR },
/* 3A /qr */ { 0, &BX_CPU_C::CMP_GbEb },
/* 3B /qr */ { 0, &BX_CPU_C::CMP_GqEq },
/* 3C /qr */ { BxImmediate_Ib, &BX_CPU_C::CMP_ALIb },
@ -1368,7 +1368,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 60 /qr */ { 0, &BX_CPU_C::BxError },
/* 61 /qr */ { 0, &BX_CPU_C::BxError },
/* 62 /qr */ { 0, &BX_CPU_C::BxError },
/* 63 /qr */ { 0, &BX_CPU_C::MOVSX_GqEd },
/* 63 /qr */ { 0, &BX_CPU_C::MOVSX_GqEdR },
/* 64 /qr */ { BxPrefix, &BX_CPU_C::BxError }, // FS:
/* 65 /qr */ { BxPrefix, &BX_CPU_C::BxError }, // GS:
/* 66 /qr */ { BxPrefix, &BX_CPU_C::BxError }, // OS:
@ -1402,13 +1402,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 82 /qr */ { 0, &BX_CPU_C::BxError },
/* 83 /qr */ { BxGroup1 | BxImmediate_Ib_SE, NULL, BxOpcodeInfo64G1EqR },
/* 84 /qr */ { 0, &BX_CPU_C::TEST_EbGbR },
/* 85 /qr */ { 0, &BX_CPU_C::TEST_EqGq },
/* 86 /qr */ { BxLockable, &BX_CPU_C::XCHG_EbGb },
/* 87 /qr */ { BxLockable, &BX_CPU_C::XCHG_EqGq },
/* 85 /qr */ { 0, &BX_CPU_C::TEST_EqGqR },
/* 86 /qr */ { 0, &BX_CPU_C::XCHG_EbGbR },
/* 87 /qr */ { 0, &BX_CPU_C::XCHG_EqGqR },
/* 88 /qr */ { 0, &BX_CPU_C::MOV_EbGbR },
/* 89 /qr */ { 0, &BX_CPU_C::MOV_EqGq },
/* 89 /qr */ { 0, &BX_CPU_C::MOV_EqGqR },
/* 8A /qr */ { 0, &BX_CPU_C::MOV_GbEbR },
/* 8B /qr */ { 0, &BX_CPU_C::MOV_GqEq },
/* 8B /qr */ { 0, &BX_CPU_C::MOV_GqEqR },
/* 8C /qr */ { 0, &BX_CPU_C::MOV_EwSw },
/* 8D /qr */ { 0, &BX_CPU_C::BxError }, // LEA
/* 8E /qr */ { 0, &BX_CPU_C::MOV_SwEw },
@ -1703,7 +1703,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 0F A0 /qr */ { 0, &BX_CPU_C::PUSH64_FS },
/* 0F A1 /qr */ { 0, &BX_CPU_C::POP64_FS },
/* 0F A2 /qr */ { 0, &BX_CPU_C::CPUID },
/* 0F A3 /qr */ { 0, &BX_CPU_C::BT_EqGq },
/* 0F A3 /qr */ { 0, &BX_CPU_C::BT_EqGqR },
/* 0F A4 /qr */ { BxImmediate_Ib, &BX_CPU_C::SHLD_EqGq },
/* 0F A5 /qr */ { 0, &BX_CPU_C::SHLD_EqGq },
/* 0F A6 /qr */ { 0, &BX_CPU_C::BxError },
@ -1711,29 +1711,29 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 0F A8 /qr */ { 0, &BX_CPU_C::PUSH64_GS },
/* 0F A9 /qr */ { 0, &BX_CPU_C::POP64_GS },
/* 0F AA /qr */ { 0, &BX_CPU_C::RSM },
/* 0F AB /qr */ { BxLockable, &BX_CPU_C::BTS_EqGq },
/* 0F AB /qr */ { 0, &BX_CPU_C::BTS_EqGqR },
/* 0F AC /qr */ { BxImmediate_Ib, &BX_CPU_C::SHRD_EqGq },
/* 0F AD /qr */ { 0, &BX_CPU_C::SHRD_EqGq },
/* 0F AE /qr */ { BxGroup15, NULL, BxOpcodeInfoG15R },
/* 0F AF /qr */ { 0, &BX_CPU_C::IMUL_GqEq },
/* 0F B0 /qr */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 /qr */ { BxLockable, &BX_CPU_C::CMPXCHG_EqGq },
/* 0F B0 /qr */ { 0, &BX_CPU_C::CMPXCHG_EbGbR },
/* 0F B1 /qr */ { 0, &BX_CPU_C::CMPXCHG_EqGqR },
/* 0F B2 /qr */ { 0, &BX_CPU_C::BxError }, // LSS
/* 0F B3 /qr */ { BxLockable, &BX_CPU_C::BTR_EqGq },
/* 0F B3 /qr */ { 0, &BX_CPU_C::BTR_EqGqR },
/* 0F B4 /qr */ { 0, &BX_CPU_C::BxError }, // LFS
/* 0F B5 /qr */ { 0, &BX_CPU_C::BxError }, // LGS
/* 0F B6 /qr */ { 0, &BX_CPU_C::MOVZX_GqEb },
/* 0F B7 /qr */ { 0, &BX_CPU_C::MOVZX_GqEw },
/* 0F B6 /qr */ { 0, &BX_CPU_C::MOVZX_GqEbR },
/* 0F B7 /qr */ { 0, &BX_CPU_C::MOVZX_GqEwR },
/* 0F B8 /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fb8q },
/* 0F B9 /qr */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F BA /qr */ { BxGroup8, NULL, BxOpcodeInfo64G8EqIb },
/* 0F BB /qr */ { BxLockable, &BX_CPU_C::BTC_EqGq },
/* 0F BB /qr */ { 0, &BX_CPU_C::BTC_EqGqR },
/* 0F BC /qr */ { 0, &BX_CPU_C::BSF_GqEq },
/* 0F BD /qr */ { 0, &BX_CPU_C::BSR_GqEq },
/* 0F BE /qr */ { 0, &BX_CPU_C::MOVSX_GqEb },
/* 0F BF /qr */ { 0, &BX_CPU_C::MOVSX_GqEw },
/* 0F C0 /qr */ { BxLockable, &BX_CPU_C::XADD_EbGb },
/* 0F C1 /qr */ { BxLockable, &BX_CPU_C::XADD_EqGq },
/* 0F BE /qr */ { 0, &BX_CPU_C::MOVSX_GqEbR },
/* 0F BF /qr */ { 0, &BX_CPU_C::MOVSX_GqEwR },
/* 0F C0 /qr */ { 0, &BX_CPU_C::XADD_EbGbR },
/* 0F C1 /qr */ { 0, &BX_CPU_C::XADD_EqGqR },
/* 0F C2 /qr */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
/* 0F C3 /qr */ { 0, &BX_CPU_C::BxError }, // MOVNTI SSE group
/* 0F C4 /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
@ -1938,7 +1938,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 83 /wm */ { BxGroup1 | BxImmediate_Ib_SE, NULL, BxOpcodeInfoG1EwM },
/* 84 /wm */ { 0, &BX_CPU_C::TEST_EbGbM },
/* 85 /wm */ { 0, &BX_CPU_C::TEST_EwGwM },
/* 86 /wm */ { BxLockable, &BX_CPU_C::XCHG_EbGb },
/* 86 /wm */ { BxLockable, &BX_CPU_C::XCHG_EbGbM },
/* 87 /wm */ { BxLockable, &BX_CPU_C::XCHG_EwGw },
/* 88 /wm */ { 0, &BX_CPU_C::MOV_EbGbM },
/* 89 /wm */ { 0, &BX_CPU_C::MOV_EwGwM },
@ -2238,7 +2238,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 0F A0 /wm */ { 0, &BX_CPU_C::PUSH16_FS },
/* 0F A1 /wm */ { 0, &BX_CPU_C::POP16_FS },
/* 0F A2 /wm */ { 0, &BX_CPU_C::CPUID },
/* 0F A3 /wm */ { 0, &BX_CPU_C::BT_EwGw },
/* 0F A3 /wm */ { 0, &BX_CPU_C::BT_EwGwM },
/* 0F A4 /wm */ { BxImmediate_Ib, &BX_CPU_C::SHLD_EwGw },
/* 0F A5 /wm */ { 0, &BX_CPU_C::SHLD_EwGw },
/* 0F A6 /wm */ { 0, &BX_CPU_C::BxError },
@ -2246,15 +2246,15 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 0F A8 /wm */ { 0, &BX_CPU_C::PUSH16_GS },
/* 0F A9 /wm */ { 0, &BX_CPU_C::POP16_GS },
/* 0F AA /wm */ { 0, &BX_CPU_C::RSM },
/* 0F AB /wm */ { BxLockable, &BX_CPU_C::BTS_EwGw },
/* 0F AB /wm */ { BxLockable, &BX_CPU_C::BTS_EwGwM },
/* 0F AC /wm */ { BxImmediate_Ib, &BX_CPU_C::SHRD_EwGw },
/* 0F AD /wm */ { 0, &BX_CPU_C::SHRD_EwGw },
/* 0F AE /wm */ { BxGroup15, NULL, BxOpcodeInfoG15M },
/* 0F AF /wm */ { 0, &BX_CPU_C::IMUL_GwEw },
/* 0F B0 /wm */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 /wm */ { BxLockable, &BX_CPU_C::CMPXCHG_EwGw },
/* 0F B0 /wm */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGbM },
/* 0F B1 /wm */ { BxLockable, &BX_CPU_C::CMPXCHG_EwGwM },
/* 0F B2 /wm */ { 0, &BX_CPU_C::LSS_GwMp },
/* 0F B3 /wm */ { BxLockable, &BX_CPU_C::BTR_EwGw },
/* 0F B3 /wm */ { BxLockable, &BX_CPU_C::BTR_EwGwM },
/* 0F B4 /wm */ { 0, &BX_CPU_C::LFS_GwMp },
/* 0F B5 /wm */ { 0, &BX_CPU_C::LGS_GwMp },
/* 0F B6 /wm */ { 0, &BX_CPU_C::MOVZX_GwEbM },
@ -2262,13 +2262,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 0F B8 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fb8w },
/* 0F B9 /wm */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F BA /wm */ { BxGroup8, NULL, BxOpcodeInfoG8EwIb },
/* 0F BB /wm */ { BxLockable, &BX_CPU_C::BTC_EwGw },
/* 0F BB /wm */ { BxLockable, &BX_CPU_C::BTC_EwGwM },
/* 0F BC /wm */ { 0, &BX_CPU_C::BSF_GwEw },
/* 0F BD /wm */ { 0, &BX_CPU_C::BSR_GwEw },
/* 0F BE /wm */ { 0, &BX_CPU_C::MOVSX_GwEbM },
/* 0F BF /wm */ { 0, &BX_CPU_C::MOV_GwEwM }, // MOVSX_GwEw
/* 0F C0 /wm */ { BxLockable, &BX_CPU_C::XADD_EbGb },
/* 0F C1 /wm */ { BxLockable, &BX_CPU_C::XADD_EwGw },
/* 0F C0 /wm */ { BxLockable, &BX_CPU_C::XADD_EbGbM },
/* 0F C1 /wm */ { BxLockable, &BX_CPU_C::XADD_EwGwM },
/* 0F C2 /wm */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
/* 0F C3 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc3M },
/* 0F C4 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
@ -2467,7 +2467,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 83 /dm */ { BxGroup1 | BxImmediate_Ib_SE, NULL, BxOpcodeInfoG1EdM },
/* 84 /dm */ { 0, &BX_CPU_C::TEST_EbGbM },
/* 85 /dm */ { 0, &BX_CPU_C::TEST_EdGdM },
/* 86 /dm */ { BxLockable, &BX_CPU_C::XCHG_EbGb },
/* 86 /dm */ { BxLockable, &BX_CPU_C::XCHG_EbGbM },
/* 87 /dm */ { BxLockable, &BX_CPU_C::XCHG_EdGdM },
/* 88 /dm */ { 0, &BX_CPU_C::MOV_EbGbM },
/* 89 /dm */ { 0, &BX_CPU_C::MOV_EdGdM },
@ -2780,8 +2780,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 0F AD /dm */ { 0, &BX_CPU_C::SHRD_EdGd },
/* 0F AE /dm */ { BxGroup15, NULL, BxOpcodeInfoG15M },
/* 0F AF /dm */ { 0, &BX_CPU_C::IMUL_GdEd },
/* 0F B0 /dm */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 /dm */ { BxLockable, &BX_CPU_C::CMPXCHG_EdGd },
/* 0F B0 /dm */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGbM },
/* 0F B1 /dm */ { BxLockable, &BX_CPU_C::CMPXCHG_EdGdM },
/* 0F B2 /dm */ { 0, &BX_CPU_C::LSS_GdMp },
/* 0F B3 /dm */ { BxLockable, &BX_CPU_C::BTR_EdGdM },
/* 0F B4 /dm */ { 0, &BX_CPU_C::LFS_GdMp },
@ -2796,8 +2796,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 0F BD /dm */ { 0, &BX_CPU_C::BSR_GdEd },
/* 0F BE /dm */ { 0, &BX_CPU_C::MOVSX_GdEbM },
/* 0F BF /dm */ { 0, &BX_CPU_C::MOVSX_GdEwM },
/* 0F C0 /dm */ { BxLockable, &BX_CPU_C::XADD_EbGb },
/* 0F C1 /dm */ { BxLockable, &BX_CPU_C::XADD_EdGd },
/* 0F C0 /dm */ { BxLockable, &BX_CPU_C::XADD_EbGbM },
/* 0F C1 /dm */ { BxLockable, &BX_CPU_C::XADD_EdGdM },
/* 0F C2 /dm */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
/* 0F C3 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc3M },
/* 0F C4 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
@ -2863,7 +2863,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
// 512 entries for 64bit operand size
/* 00 /qm */ { BxLockable, &BX_CPU_C::ADD_EbGbM },
/* 01 /qm */ { BxLockable, &BX_CPU_C::ADD_EqGq },
/* 01 /qm */ { BxLockable, &BX_CPU_C::ADD_EqGqM },
/* 02 /qm */ { 0, &BX_CPU_C::ADD_GbEb },
/* 03 /qm */ { 0, &BX_CPU_C::ADD_GqEq },
/* 04 /qm */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
@ -2871,7 +2871,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 06 /qm */ { 0, &BX_CPU_C::BxError },
/* 07 /qm */ { 0, &BX_CPU_C::BxError },
/* 08 /qm */ { 0, &BX_CPU_C::OR_EbGbM },
/* 09 /qm */ { BxLockable, &BX_CPU_C::OR_EqGq },
/* 09 /qm */ { BxLockable, &BX_CPU_C::OR_EqGqM },
/* 0A /qm */ { BxLockable, &BX_CPU_C::OR_GbEb },
/* 0B /qm */ { 0, &BX_CPU_C::OR_GqEq },
/* 0C /qm */ { BxImmediate_Ib, &BX_CPU_C::OR_ALIb },
@ -2879,7 +2879,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 0E /qm */ { 0, &BX_CPU_C::BxError },
/* 0F /qm */ { 0, &BX_CPU_C::BxError }, // 2-byte escape
/* 10 /qm */ { BxLockable, &BX_CPU_C::ADC_EbGbM },
/* 11 /qm */ { BxLockable, &BX_CPU_C::ADC_EqGq },
/* 11 /qm */ { BxLockable, &BX_CPU_C::ADC_EqGqM },
/* 12 /qm */ { 0, &BX_CPU_C::ADC_GbEb },
/* 13 /qm */ { 0, &BX_CPU_C::ADC_GqEq },
/* 14 /qm */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
@ -2887,7 +2887,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 16 /qm */ { 0, &BX_CPU_C::BxError },
/* 17 /qm */ { 0, &BX_CPU_C::BxError },
/* 18 /qm */ { BxLockable, &BX_CPU_C::SBB_EbGbM },
/* 19 /qm */ { BxLockable, &BX_CPU_C::SBB_EqGq },
/* 19 /qm */ { BxLockable, &BX_CPU_C::SBB_EqGqM },
/* 1A /qm */ { 0, &BX_CPU_C::SBB_GbEb },
/* 1B /qm */ { 0, &BX_CPU_C::SBB_GqEq },
/* 1C /qm */ { BxImmediate_Ib, &BX_CPU_C::SBB_ALIb },
@ -2895,7 +2895,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 1E /qm */ { 0, &BX_CPU_C::BxError },
/* 1F /qm */ { 0, &BX_CPU_C::BxError },
/* 20 /qm */ { BxLockable, &BX_CPU_C::AND_EbGbM },
/* 21 /qm */ { BxLockable, &BX_CPU_C::AND_EqGq },
/* 21 /qm */ { BxLockable, &BX_CPU_C::AND_EqGqM },
/* 22 /qm */ { 0, &BX_CPU_C::AND_GbEb },
/* 23 /qm */ { 0, &BX_CPU_C::AND_GqEq },
/* 24 /qm */ { BxImmediate_Ib, &BX_CPU_C::AND_ALIb },
@ -2903,7 +2903,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 26 /qm */ { BxPrefix, &BX_CPU_C::BxError }, // ES:
/* 27 /qm */ { 0, &BX_CPU_C::BxError },
/* 28 /qm */ { BxLockable, &BX_CPU_C::SUB_EbGbM },
/* 29 /qm */ { BxLockable, &BX_CPU_C::SUB_EqGq },
/* 29 /qm */ { BxLockable, &BX_CPU_C::SUB_EqGqM },
/* 2A /qm */ { 0, &BX_CPU_C::SUB_GbEb },
/* 2B /qm */ { 0, &BX_CPU_C::SUB_GqEq },
/* 2C /qm */ { BxImmediate_Ib, &BX_CPU_C::SUB_ALIb },
@ -2911,7 +2911,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 2E /qm */ { BxPrefix, &BX_CPU_C::BxError }, // CS:
/* 2F /qm */ { 0, &BX_CPU_C::BxError },
/* 30 /qm */ { BxLockable, &BX_CPU_C::XOR_EbGbM },
/* 31 /qm */ { BxLockable, &BX_CPU_C::XOR_EqGq },
/* 31 /qm */ { BxLockable, &BX_CPU_C::XOR_EqGqM },
/* 32 /qm */ { 0, &BX_CPU_C::XOR_GbEb },
/* 33 /qm */ { 0, &BX_CPU_C::XOR_GqEq },
/* 34 /qm */ { BxImmediate_Ib, &BX_CPU_C::XOR_ALIb },
@ -2919,7 +2919,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 36 /qm */ { BxPrefix, &BX_CPU_C::BxError }, // SS:
/* 37 /qm */ { 0, &BX_CPU_C::BxError },
/* 38 /qm */ { 0, &BX_CPU_C::CMP_EbGbM },
/* 39 /qm */ { 0, &BX_CPU_C::CMP_EqGq },
/* 39 /qm */ { 0, &BX_CPU_C::CMP_EqGqM },
/* 3A /qm */ { 0, &BX_CPU_C::CMP_GbEb },
/* 3B /qm */ { 0, &BX_CPU_C::CMP_GqEq },
/* 3C /qm */ { BxImmediate_Ib, &BX_CPU_C::CMP_ALIb },
@ -2961,7 +2961,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 60 /qm */ { 0, &BX_CPU_C::BxError },
/* 61 /qm */ { 0, &BX_CPU_C::BxError },
/* 62 /qm */ { 0, &BX_CPU_C::BxError },
/* 63 /qm */ { 0, &BX_CPU_C::MOVSX_GqEd },
/* 63 /qm */ { 0, &BX_CPU_C::MOVSX_GqEdM },
/* 64 /qm */ { BxPrefix, &BX_CPU_C::BxError }, // FS:
/* 65 /qm */ { BxPrefix, &BX_CPU_C::BxError }, // GS:
/* 66 /qm */ { BxPrefix, &BX_CPU_C::BxError }, // OS:
@ -2995,13 +2995,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 82 /qm */ { 0, &BX_CPU_C::BxError },
/* 83 /qm */ { BxGroup1 | BxImmediate_Ib_SE, NULL, BxOpcodeInfo64G1EqM },
/* 84 /qm */ { 0, &BX_CPU_C::TEST_EbGbM },
/* 85 /qm */ { 0, &BX_CPU_C::TEST_EqGq },
/* 86 /qm */ { BxLockable, &BX_CPU_C::XCHG_EbGb },
/* 87 /qm */ { BxLockable, &BX_CPU_C::XCHG_EqGq },
/* 85 /qm */ { 0, &BX_CPU_C::TEST_EqGqM },
/* 86 /qm */ { BxLockable, &BX_CPU_C::XCHG_EbGbM },
/* 87 /qm */ { BxLockable, &BX_CPU_C::XCHG_EqGqM },
/* 88 /qm */ { 0, &BX_CPU_C::MOV_EbGbM },
/* 89 /qm */ { 0, &BX_CPU_C::MOV_EqGq },
/* 89 /qm */ { 0, &BX_CPU_C::MOV_EqGqM },
/* 8A /qm */ { 0, &BX_CPU_C::MOV_GbEbM },
/* 8B /qm */ { 0, &BX_CPU_C::MOV_GqEq },
/* 8B /qm */ { 0, &BX_CPU_C::MOV_GqEqM },
/* 8C /qm */ { 0, &BX_CPU_C::MOV_EwSw },
/* 8D /qm */ { 0, &BX_CPU_C::LEA_GqM },
/* 8E /qm */ { 0, &BX_CPU_C::MOV_SwEw },
@ -3296,7 +3296,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 0F A0 /qm */ { 0, &BX_CPU_C::PUSH64_FS },
/* 0F A1 /qm */ { 0, &BX_CPU_C::POP64_FS },
/* 0F A2 /qm */ { 0, &BX_CPU_C::CPUID },
/* 0F A3 /qm */ { 0, &BX_CPU_C::BT_EqGq },
/* 0F A3 /qm */ { 0, &BX_CPU_C::BT_EqGqM },
/* 0F A4 /qm */ { BxImmediate_Ib, &BX_CPU_C::SHLD_EqGq },
/* 0F A5 /qm */ { 0, &BX_CPU_C::SHLD_EqGq },
/* 0F A6 /qm */ { 0, &BX_CPU_C::BxError },
@ -3304,29 +3304,29 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 0F A8 /qm */ { 0, &BX_CPU_C::PUSH64_GS },
/* 0F A9 /qm */ { 0, &BX_CPU_C::POP64_GS },
/* 0F AA /qm */ { 0, &BX_CPU_C::RSM },
/* 0F AB /qm */ { BxLockable, &BX_CPU_C::BTS_EqGq },
/* 0F AB /qm */ { BxLockable, &BX_CPU_C::BTS_EqGqM },
/* 0F AC /qm */ { BxImmediate_Ib, &BX_CPU_C::SHRD_EqGq },
/* 0F AD /qm */ { 0, &BX_CPU_C::SHRD_EqGq },
/* 0F AE /qm */ { BxGroup15, NULL, BxOpcodeInfoG15M },
/* 0F AF /qm */ { 0, &BX_CPU_C::IMUL_GqEq },
/* 0F B0 /qm */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
/* 0F B1 /qm */ { BxLockable, &BX_CPU_C::CMPXCHG_EqGq },
/* 0F B0 /qm */ { BxLockable, &BX_CPU_C::CMPXCHG_EbGbM },
/* 0F B1 /qm */ { BxLockable, &BX_CPU_C::CMPXCHG_EqGqM },
/* 0F B2 /qm */ { 0, &BX_CPU_C::LSS_GqMp }, // TODO: LSS_GdMp for AMD CPU
/* 0F B3 /qm */ { BxLockable, &BX_CPU_C::BTR_EqGq },
/* 0F B3 /qm */ { BxLockable, &BX_CPU_C::BTR_EqGqM },
/* 0F B4 /qm */ { 0, &BX_CPU_C::LFS_GqMp }, // TODO: LFS_GdMp for AMD CPU
/* 0F B5 /qm */ { 0, &BX_CPU_C::LGS_GqMp }, // TODO: LGS_GdMp for AMD CPU
/* 0F B6 /qm */ { 0, &BX_CPU_C::MOVZX_GqEb },
/* 0F B7 /qm */ { 0, &BX_CPU_C::MOVZX_GqEw },
/* 0F B6 /qm */ { 0, &BX_CPU_C::MOVZX_GqEbM },
/* 0F B7 /qm */ { 0, &BX_CPU_C::MOVZX_GqEwM },
/* 0F B8 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fb8q },
/* 0F B9 /qm */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F BA /qm */ { BxGroup8, NULL, BxOpcodeInfo64G8EqIb },
/* 0F BB /qm */ { BxLockable, &BX_CPU_C::BTC_EqGq },
/* 0F BB /qm */ { BxLockable, &BX_CPU_C::BTC_EqGqM },
/* 0F BC /qm */ { 0, &BX_CPU_C::BSF_GqEq },
/* 0F BD /qm */ { 0, &BX_CPU_C::BSR_GqEq },
/* 0F BE /qm */ { 0, &BX_CPU_C::MOVSX_GqEb },
/* 0F BF /qm */ { 0, &BX_CPU_C::MOVSX_GqEw },
/* 0F C0 /qm */ { BxLockable, &BX_CPU_C::XADD_EbGb },
/* 0F C1 /qm */ { BxLockable, &BX_CPU_C::XADD_EqGq },
/* 0F BE /qm */ { 0, &BX_CPU_C::MOVSX_GqEbM },
/* 0F BF /qm */ { 0, &BX_CPU_C::MOVSX_GqEwM },
/* 0F C0 /qm */ { BxLockable, &BX_CPU_C::XADD_EbGbM },
/* 0F C1 /qm */ { BxLockable, &BX_CPU_C::XADD_EqGqM },
/* 0F C2 /qm */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc2 },
/* 0F C3 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc3qM },
/* 0F C4 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc4 },
@ -3834,7 +3834,8 @@ modrm_done:
if (lock) { // lock prefix invalid opcode
// lock prefix not allowed or destination operand is not memory
if ((mod == 0xc0) || !(attr & BxLockable)) {
// only memory destination is marked BxLockable
if (/*(mod == 0xc0) || */ !(attr & BxLockable)) {
BX_INFO(("LOCK prefix unallowed (op1=0x%x, mod=%u, nnn=%u)", b1, mod, nnn));
UndefinedOpcode(instruction);
}

110
bochs/cpu/logical64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: logical64.cc,v 1.21 2007-11-17 23:28:31 sshwarts Exp $
// $Id: logical64.cc,v 1.22 2007-11-18 18:24:46 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -32,24 +32,27 @@
#if BX_SUPPORT_X86_64
void BX_CPU_C::XOR_EqGq(bxInstruction_c *i)
void BX_CPU_C::XOR_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 ^= op2_64;
write_RMW_virtual_qword(op1_64);
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 ^= op2_64;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op1_64 ^= op2_64;
write_RMW_virtual_qword(op1_64);
}
SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_LOGIC64);
}
void BX_CPU_C::XOR_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 ^= op2_64;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_LOGIC64);
}
@ -153,24 +156,27 @@ void BX_CPU_C::NOT_EqR(bxInstruction_c *i)
BX_WRITE_64BIT_REG(i->rm(), op1_64);
}
void BX_CPU_C::OR_EqGq(bxInstruction_c *i)
void BX_CPU_C::OR_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 |= op2_64;
write_RMW_virtual_qword(op1_64);
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 |= op2_64;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op1_64 |= op2_64;
write_RMW_virtual_qword(op1_64);
}
SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_LOGIC64);
}
void BX_CPU_C::OR_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 |= op2_64;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_LOGIC64);
}
@ -211,24 +217,27 @@ void BX_CPU_C::OR_RAXId(bxInstruction_c *i)
SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_LOGIC64);
}
void BX_CPU_C::AND_EqGq(bxInstruction_c *i)
void BX_CPU_C::AND_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 &= op2_64;
write_RMW_virtual_qword(op1_64);
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 &= op2_64;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op1_64 &= op2_64;
write_RMW_virtual_qword(op1_64);
}
SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_LOGIC64);
}
void BX_CPU_C::AND_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 &= op2_64;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_LOGIC64);
}
@ -292,21 +301,24 @@ void BX_CPU_C::AND_EqIdR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_LOGIC64);
}
void BX_CPU_C::TEST_EqGq(bxInstruction_c *i)
void BX_CPU_C::TEST_EqGqM(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
/* pointer, segment address pair */
read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 &= op2_64;
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_LOGIC64);
}
void BX_CPU_C::TEST_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 &= op2_64;
SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_LOGIC64);

12
bochs/cpu/protect_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: protect_ctrl.cc,v 1.64 2007-11-17 23:28:31 sshwarts Exp $
// $Id: protect_ctrl.cc,v 1.65 2007-11-18 18:24:46 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -387,8 +387,6 @@ void BX_CPU_C::LTR_Ew(bxInstruction_c *i)
UndefinedOpcode(i);
}
invalidate_prefetch_q();
/* #GP(0) if the current privilege level is not 0 */
if (CPL != 0) {
BX_ERROR(("LTR: The current priveledge level is not 0"));
@ -402,6 +400,8 @@ void BX_CPU_C::LTR_Ew(bxInstruction_c *i)
read_virtual_word(i->seg(), RMAddr(i), &raw_selector);
}
invalidate_prefetch_q();
/* if selector is NULL, invalidate and done */
if ((raw_selector & BX_SELECTOR_RPL_MASK) == 0) {
BX_ERROR(("LTR: loading with NULL selector!"));
@ -743,12 +743,6 @@ void BX_CPU_C::LGDT64_Ms(bxInstruction_c *i)
{
BX_ASSERT(protected_mode());
/* operand might be a register or memory reference */
if (i->modC0()) {
BX_ERROR(("LGDT64_Ms: must be memory reference"));
UndefinedOpcode(i);
}
if (CPL!=0) {
BX_ERROR(("LGDT64_Ms: CPL != 0 in long mode"));
exception(BX_GP_EXCEPTION, 0, 0);

6
bochs/main.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: main.cc,v 1.363 2007-11-09 21:14:56 sshwarts Exp $
// $Id: main.cc,v 1.364 2007-11-18 18:24:44 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -1234,8 +1234,8 @@ void bx_signal_handler(int signum)
bx_gui->show_ips((Bit32u) ips_count);
ticks_count = bx_pc_system.time_ticks();
counts++;
// if ((counts % 10) == 0)
// BX_INFO(("average IPS: ticks_count/counts = %u (%u)", (unsigned) (ticks_count/counts), (unsigned) ips_count));
printf("MIPS: %u\tticks/counts = %u\t(%us)\n",
(unsigned) ips_count, (unsigned) (ticks_count/counts), (unsigned) counts);
}
#if !defined(__MINGW32__) && !defined(_MSC_VER)
signal(SIGALRM, bx_signal_handler);