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split11b on opcode tables level - split almost eevery splittable instruction

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will be continued
This commit is contained in:
Stanislav Shwartsman 2007-11-17 12:44:10 +00:00
parent abe3f4c5c2
commit d9e58bd598
24 changed files with 6097 additions and 3418 deletions
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183
bochs/cpu/arith16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith16.cc,v 1.51 2007-11-16 17:45:58 sshwarts Exp $
// $Id: arith16.cc,v 1.52 2007-11-17 12:44:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -43,22 +43,26 @@ void BX_CPU_C::DEC_RX(bxInstruction_c *i)
SET_FLAGS_OSZAP_RESULT_16(rx, BX_INSTR_DEC16);
}
void BX_CPU_C::ADD_EwGw(bxInstruction_c *i)
void BX_CPU_C::ADD_EwGwM(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, sum_16;
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op2_16 = BX_READ_16BIT_REG(i->nnn());
sum_16 = op1_16 + op2_16;
write_RMW_virtual_word(sum_16);
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
sum_16 = op1_16 + op2_16;
BX_WRITE_16BIT_REG(i->rm(), sum_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
sum_16 = op1_16 + op2_16;
write_RMW_virtual_word(sum_16);
}
SET_FLAGS_OSZAPC_S1_16(op1_16, sum_16, BX_INSTR_ADD16);
}
void BX_CPU_C::ADD_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, sum_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
sum_16 = op1_16 + op2_16;
BX_WRITE_16BIT_REG(i->rm(), sum_16);
SET_FLAGS_OSZAPC_S1_16(op1_16, sum_16, BX_INSTR_ADD16);
}
@ -103,23 +107,28 @@ void BX_CPU_C::ADD_AXIw(bxInstruction_c *i)
SET_FLAGS_OSZAPC_S1_16(op1_16, sum_16, BX_INSTR_ADD16);
}
void BX_CPU_C::ADC_EwGw(bxInstruction_c *i)
void BX_CPU_C::ADC_EwGwM(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, sum_16;
bx_bool temp_CF = getB_CF();
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op2_16 = BX_READ_16BIT_REG(i->nnn());
sum_16 = op1_16 + op2_16 + temp_CF;
write_RMW_virtual_word(sum_16);
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
sum_16 = op1_16 + op2_16 + temp_CF;
BX_WRITE_16BIT_REG(i->rm(), sum_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
sum_16 = op1_16 + op2_16 + temp_CF;
write_RMW_virtual_word(sum_16);
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD_ADC16(temp_CF));
}
void BX_CPU_C::ADC_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, sum_16;
bx_bool temp_CF = getB_CF();
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
sum_16 = op1_16 + op2_16 + temp_CF;
BX_WRITE_16BIT_REG(i->rm(), sum_16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD_ADC16(temp_CF));
}
@ -160,23 +169,28 @@ void BX_CPU_C::ADC_AXIw(bxInstruction_c *i)
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD_ADC16(temp_CF));
}
void BX_CPU_C::SBB_EwGw(bxInstruction_c *i)
void BX_CPU_C::SBB_EwGwM(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, diff_16;
bx_bool temp_CF = getB_CF();
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op2_16 = BX_READ_16BIT_REG(i->nnn());
diff_16 = op1_16 - (op2_16 + temp_CF);
write_RMW_virtual_word(diff_16);
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
diff_16 = op1_16 - (op2_16 + temp_CF);
BX_WRITE_16BIT_REG(i->rm(), diff_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
diff_16 = op1_16 - (op2_16 + temp_CF);
write_RMW_virtual_word(diff_16);
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_SUB_SBB16(temp_CF));
}
void BX_CPU_C::SBB_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, diff_16;
bx_bool temp_CF = getB_CF();
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
diff_16 = op1_16 - (op2_16 + temp_CF);
BX_WRITE_16BIT_REG(i->rm(), diff_16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_SUB_SBB16(temp_CF));
}
@ -238,22 +252,26 @@ void BX_CPU_C::SBB_EwIwR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_SUB_SBB16(temp_CF));
}
void BX_CPU_C::SUB_EwGw(bxInstruction_c *i)
void BX_CPU_C::SUB_EwGwM(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, diff_16;
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op2_16 = BX_READ_16BIT_REG(i->nnn());
diff_16 = op1_16 - op2_16;
write_RMW_virtual_word(diff_16);
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
diff_16 = op1_16 - op2_16;
BX_WRITE_16BIT_REG(i->rm(), diff_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
diff_16 = op1_16 - op2_16;
write_RMW_virtual_word(diff_16);
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_SUB16);
}
void BX_CPU_C::SUB_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, diff_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
diff_16 = op1_16 - op2_16;
BX_WRITE_16BIT_REG(i->rm(), diff_16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_SUB16);
}
@ -290,19 +308,23 @@ void BX_CPU_C::SUB_AXIw(bxInstruction_c *i)
AX = diff_16;
}
void BX_CPU_C::CMP_EwGw(bxInstruction_c *i)
void BX_CPU_C::CMP_EwGwM(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, diff_16;
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
op2_16 = BX_READ_16BIT_REG(i->nnn());
diff_16 = op1_16 - op2_16;
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_COMPARE16);
}
void BX_CPU_C::CMP_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, diff_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_COMPARE16);
@ -310,7 +332,7 @@ void BX_CPU_C::CMP_EwGw(bxInstruction_c *i)
void BX_CPU_C::CMP_GwEw(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
Bit16u op1_16, op2_16, diff_16;
op1_16 = BX_READ_16BIT_REG(i->nnn());
@ -321,18 +343,19 @@ void BX_CPU_C::CMP_GwEw(bxInstruction_c *i)
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
Bit16u diff_16 = op1_16 - op2_16;
diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_COMPARE16);
}
void BX_CPU_C::CMP_AXIw(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
Bit16u op1_16, op2_16, diff_16;
op1_16 = AX;
op2_16 = i->Iw();
diff_16 = op1_16 - op2_16;
Bit16u diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_COMPARE16);
}
@ -496,38 +519,42 @@ void BX_CPU_C::NEG_Ew(bxInstruction_c *i)
SET_FLAGS_OSZAPC_RESULT_16(op1_16, BX_INSTR_NEG16);
}
void BX_CPU_C::INC_Ew(bxInstruction_c *i)
void BX_CPU_C::INC_EwM(bxInstruction_c *i)
{
Bit16u op1_16;
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
op1_16++;
BX_WRITE_16BIT_REG(i->rm(), op1_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op1_16++;
write_RMW_virtual_word(op1_16);
}
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op1_16++;
write_RMW_virtual_word(op1_16);
SET_FLAGS_OSZAP_RESULT_16(op1_16, BX_INSTR_INC16);
}
void BX_CPU_C::DEC_Ew(bxInstruction_c *i)
void BX_CPU_C::INC_EwR(bxInstruction_c *i)
{
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
op1_16++;
BX_WRITE_16BIT_REG(i->rm(), op1_16);
SET_FLAGS_OSZAP_RESULT_16(op1_16, BX_INSTR_INC16);
}
void BX_CPU_C::DEC_EwM(bxInstruction_c *i)
{
Bit16u op1_16;
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
op1_16--;
BX_WRITE_16BIT_REG(i->rm(), op1_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op1_16--;
write_RMW_virtual_word(op1_16);
}
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op1_16--;
write_RMW_virtual_word(op1_16);
SET_FLAGS_OSZAP_RESULT_16(op1_16, BX_INSTR_DEC16);
}
void BX_CPU_C::DEC_EwR(bxInstruction_c *i)
{
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
op1_16--;
BX_WRITE_16BIT_REG(i->rm(), op1_16);
SET_FLAGS_OSZAP_RESULT_16(op1_16, BX_INSTR_DEC16);
}

182
bochs/cpu/arith32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith32.cc,v 1.57 2007-11-16 17:45:58 sshwarts Exp $
// $Id: arith32.cc,v 1.58 2007-11-17 12:44:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -53,22 +53,26 @@ void BX_CPU_C::DEC_ERX(bxInstruction_c *i)
BX_CLEAR_64BIT_HIGH(i->opcodeReg());
}
void BX_CPU_C::ADD_EdGd(bxInstruction_c *i)
void BX_CPU_C::ADD_EdGdM(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, sum_32;
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op2_32 = BX_READ_32BIT_REG(i->nnn());
sum_32 = op1_32 + op2_32;
write_RMW_virtual_dword(sum_32);
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
sum_32 = op1_32 + op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
sum_32 = op1_32 + op2_32;
write_RMW_virtual_dword(sum_32);
}
SET_FLAGS_OSZAPC_S1_32(op1_32, sum_32, BX_INSTR_ADD32);
}
void BX_CPU_C::ADD_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, sum_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
sum_32 = op1_32 + op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
SET_FLAGS_OSZAPC_S1_32(op1_32, sum_32, BX_INSTR_ADD32);
}
@ -78,7 +82,6 @@ void BX_CPU_C::ADD_GdEdM(bxInstruction_c *i)
Bit32u op1_32, op2_32, sum_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
sum_32 = op1_32 + op2_32;
SET_FLAGS_OSZAPC_S1_32(op1_32, sum_32, BX_INSTR_ADD32);
@ -110,24 +113,30 @@ void BX_CPU_C::ADD_EAXId(bxInstruction_c *i)
SET_FLAGS_OSZAPC_S1_32(op1_32, sum_32, BX_INSTR_ADD32);
}
void BX_CPU_C::ADC_EdGd(bxInstruction_c *i)
void BX_CPU_C::ADC_EdGdM(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
Bit32u op1_32, op2_32, sum_32;
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op2_32 = BX_READ_32BIT_REG(i->nnn());
sum_32 = op1_32 + op2_32 + temp_CF;
write_RMW_virtual_dword(sum_32);
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
sum_32 = op1_32 + op2_32 + temp_CF;
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
sum_32 = op1_32 + op2_32 + temp_CF;
write_RMW_virtual_dword(sum_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD_ADC32(temp_CF));
}
void BX_CPU_C::ADC_EdGdR(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
Bit32u op1_32, op2_32, sum_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
sum_32 = op1_32 + op2_32 + temp_CF;
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD_ADC32(temp_CF));
}
@ -167,24 +176,30 @@ void BX_CPU_C::ADC_EAXId(bxInstruction_c *i)
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD_ADC32(temp_CF));
}
void BX_CPU_C::SBB_EdGd(bxInstruction_c *i)
void BX_CPU_C::SBB_EdGdM(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
Bit32u op1_32, op2_32, diff_32;
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op2_32 = BX_READ_32BIT_REG(i->nnn());
diff_32 = op1_32 - (op2_32 + temp_CF);
write_RMW_virtual_dword(diff_32);
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
diff_32 = op1_32 - (op2_32 + temp_CF);
BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
diff_32 = op1_32 - (op2_32 + temp_CF);
write_RMW_virtual_dword(diff_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB_SBB32(temp_CF));
}
void BX_CPU_C::SBB_EdGdR(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
Bit32u op1_32, op2_32, diff_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
diff_32 = op1_32 - (op2_32 + temp_CF);
BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB_SBB32(temp_CF));
}
@ -252,22 +267,26 @@ void BX_CPU_C::SBB_EdIdR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB_SBB32(temp_CF));
}
void BX_CPU_C::SUB_EdGd(bxInstruction_c *i)
void BX_CPU_C::SUB_EdGdM(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, diff_32;
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op2_32 = BX_READ_32BIT_REG(i->nnn());
diff_32 = op1_32 - op2_32;
write_RMW_virtual_dword(diff_32);
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
diff_32 = op1_32 - op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
diff_32 = op1_32 - op2_32;
write_RMW_virtual_dword(diff_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
}
void BX_CPU_C::SUB_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, diff_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
diff_32 = op1_32 - op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
}
@ -304,19 +323,23 @@ void BX_CPU_C::SUB_EAXId(bxInstruction_c *i)
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32);
}
void BX_CPU_C::CMP_EdGd(bxInstruction_c *i)
void BX_CPU_C::CMP_EdGdM(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, diff_32;
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op2_32 = BX_READ_32BIT_REG(i->nnn());
diff_32 = op1_32 - op2_32;
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_COMPARE32);
}
void BX_CPU_C::CMP_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, diff_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_COMPARE32);
@ -547,38 +570,42 @@ void BX_CPU_C::NEG_Ed(bxInstruction_c *i)
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_NEG32);
}
void BX_CPU_C::INC_Ed(bxInstruction_c *i)
void BX_CPU_C::INC_EdM(bxInstruction_c *i)
{
Bit32u op1_32;
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32++;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op1_32++;
write_RMW_virtual_dword(op1_32);
}
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op1_32++;
write_RMW_virtual_dword(op1_32);
SET_FLAGS_OSZAP_RESULT_32(op1_32, BX_INSTR_INC32);
}
void BX_CPU_C::DEC_Ed(bxInstruction_c *i)
void BX_CPU_C::INC_EdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32++;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
SET_FLAGS_OSZAP_RESULT_32(op1_32, BX_INSTR_INC32);
}
void BX_CPU_C::DEC_EdM(bxInstruction_c *i)
{
Bit32u op1_32;
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32--;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op1_32--;
write_RMW_virtual_dword(op1_32);
}
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op1_32--;
write_RMW_virtual_dword(op1_32);
SET_FLAGS_OSZAP_RESULT_32(op1_32, BX_INSTR_DEC32);
}
void BX_CPU_C::DEC_EdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32--;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
SET_FLAGS_OSZAP_RESULT_32(op1_32, BX_INSTR_DEC32);
}
@ -625,11 +652,6 @@ void BX_CPU_C::CMPXCHG8B(bxInstruction_c *i)
#if (BX_CPU_LEVEL >= 5) || (BX_CPU_LEVEL_HACKED >= 5)
Bit32u op1_64_lo, op1_64_hi, diff;
if (i->modC0()) {
BX_INFO(("CMPXCHG8B: dest is not memory location (#UD)"));
UndefinedOpcode(i);
}
read_virtual_dword(i->seg(), RMAddr(i), &op1_64_lo);
read_RMW_virtual_dword(i->seg(), RMAddr(i) + 4, &op1_64_hi);

85
bochs/cpu/arith64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith64.cc,v 1.33 2007-11-06 08:39:25 sshwarts Exp $
// $Id: arith64.cc,v 1.34 2007-11-17 12:44:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -37,7 +37,7 @@
void BX_CPU_C::ADD_EqGq(bxInstruction_c *i)
{
/* for 64 bit operand size mode */
Bit64u op2_64, op1_64, sum_64;
Bit64u op1_64, op2_64, sum_64;
op2_64 = BX_READ_64BIT_REG(i->nnn());
@ -101,7 +101,7 @@ void BX_CPU_C::ADC_EqGq(bxInstruction_c *i)
bx_bool temp_CF = getB_CF();
/* for 64 bit operand size mode */
Bit64u op2_64, op1_64, sum_64;
Bit64u op1_64, op2_64, sum_64;
op2_64 = BX_READ_64BIT_REG(i->nnn());
@ -169,7 +169,7 @@ void BX_CPU_C::SBB_EqGq(bxInstruction_c *i)
bx_bool temp_CF = getB_CF();
/* for 64 bit operand size mode */
Bit64u op2_64, op1_64, diff_64;
Bit64u op1_64, op2_64, diff_64;
op2_64 = BX_READ_64BIT_REG(i->nnn());
@ -237,7 +237,7 @@ void BX_CPU_C::SBB_EqId(bxInstruction_c *i)
bx_bool temp_CF = getB_CF();
/* for 64 bit operand size mode */
Bit64u op2_64, op1_64, diff_64;
Bit64u op1_64, op2_64, diff_64;
op2_64 = (Bit32s) i->Id();
@ -260,7 +260,7 @@ void BX_CPU_C::SBB_EqId(bxInstruction_c *i)
void BX_CPU_C::SUB_EqGq(bxInstruction_c *i)
{
/* for 64 bit operand size mode */
Bit64u op2_64, op1_64, diff_64;
Bit64u op1_64, op2_64, diff_64;
op2_64 = BX_READ_64BIT_REG(i->nnn());
@ -322,7 +322,7 @@ void BX_CPU_C::SUB_RAXId(bxInstruction_c *i)
void BX_CPU_C::CMP_EqGq(bxInstruction_c *i)
{
/* for 64 bit operand size mode */
Bit64u op2_64, op1_64, diff_64;
Bit64u op1_64, op2_64, diff_64;
op2_64 = BX_READ_64BIT_REG(i->nnn());
@ -391,7 +391,7 @@ void BX_CPU_C::CQO(bxInstruction_c *i)
void BX_CPU_C::XADD_EqGq(bxInstruction_c *i)
{
Bit64u op2_64, op1_64, sum_64;
Bit64u op1_64, op2_64, sum_64;
/* XADD dst(r/m), src(r)
* temp <-- src + dst | sum = op2 + op1
@ -433,7 +433,7 @@ void BX_CPU_C::XADD_EqGq(bxInstruction_c *i)
void BX_CPU_C::ADD_EqId(bxInstruction_c *i)
{
/* for 64 bit operand size mode */
Bit64u op2_64, op1_64, sum_64;
Bit64u op1_64, op2_64, sum_64;
op2_64 = (Bit32s) i->Id();
@ -458,7 +458,7 @@ void BX_CPU_C::ADC_EqId(bxInstruction_c *i)
bx_bool temp_CF = getB_CF();
/* for 64 bit operand size mode */
Bit64u op2_64, op1_64, sum_64;
Bit64u op1_64, op2_64, sum_64;
op2_64 = (Bit32s) i->Id();
@ -481,7 +481,7 @@ void BX_CPU_C::ADC_EqId(bxInstruction_c *i)
void BX_CPU_C::SUB_EqId(bxInstruction_c *i)
{
/* for 64 bit operand size mode */
Bit64u op2_64, op1_64, diff_64;
Bit64u op1_64, op2_64, diff_64;
op2_64 = (Bit32s) i->Id();
@ -504,7 +504,7 @@ void BX_CPU_C::SUB_EqId(bxInstruction_c *i)
void BX_CPU_C::CMP_EqId(bxInstruction_c *i)
{
/* for 64 bit operand size mode */
Bit64u op2_64, op1_64, diff_64;
Bit64u op1_64, op2_64, diff_64;
op2_64 = (Bit32s) i->Id();
@ -543,49 +543,51 @@ void BX_CPU_C::NEG_Eq(bxInstruction_c *i)
SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_NEG64);
}
void BX_CPU_C::INC_Eq(bxInstruction_c *i)
void BX_CPU_C::INC_EqM(bxInstruction_c *i)
{
Bit64u op1_64;
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64++;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op1_64++;
write_RMW_virtual_qword(op1_64);
}
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op1_64++;
write_RMW_virtual_qword(op1_64);
SET_FLAGS_OSZAP_RESULT_64(op1_64, BX_INSTR_INC64);
}
void BX_CPU_C::DEC_Eq(bxInstruction_c *i)
void BX_CPU_C::INC_EqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64++;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
SET_FLAGS_OSZAP_RESULT_64(op1_64, BX_INSTR_INC64);
}
void BX_CPU_C::DEC_EqM(bxInstruction_c *i)
{
Bit64u op1_64;
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64--;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op1_64--;
write_RMW_virtual_qword(op1_64);
}
/* pointer, segment address pair */
read_RMW_virtual_qword(i->seg(), RMAddr(i), &op1_64);
op1_64--;
write_RMW_virtual_qword(op1_64);
SET_FLAGS_OSZAP_RESULT_64(op1_64, BX_INSTR_DEC64);
}
void BX_CPU_C::DEC_EqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64--;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
SET_FLAGS_OSZAP_RESULT_64(op1_64, BX_INSTR_DEC64);
}
void BX_CPU_C::CMPXCHG_EqGq(bxInstruction_c *i)
{
Bit64u op2_64, op1_64, diff_64;
Bit64u op1_64, op2_64, diff_64;
/* op1_64 is a register or memory reference */
if (i->modC0()) {
@ -621,11 +623,6 @@ void BX_CPU_C::CMPXCHG16B(bxInstruction_c *i)
{
Bit64u op1_64_lo, op1_64_hi, diff;
if (i->modC0()) {
BX_ERROR(("CMPXCHG16B: dest is not memory location (#UD)"));
UndefinedOpcode(i);
}
if (RMAddr(i) & 0xf) {
BX_ERROR(("CMPXCHG16B: not aligned memory location (#GP)"));
exception(BX_GP_EXCEPTION, 0, 0);

117
bochs/cpu/bit.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bit.cc,v 1.34 2007-10-21 22:07:32 sshwarts Exp $
// $Id: bit.cc,v 1.35 2007-11-17 12:44:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -579,7 +579,7 @@ void BX_CPU_C::BT_EwGw(bxInstruction_c *i)
setB_CF((op1_16 >> index) & 0x01);
}
void BX_CPU_C::BT_EdGd(bxInstruction_c *i)
void BX_CPU_C::BT_EdGdM(bxInstruction_c *i)
{
bx_address op1_addr;
Bit32u op1_32, op2_32, index;
@ -587,14 +587,6 @@ void BX_CPU_C::BT_EdGd(bxInstruction_c *i)
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 &= 0x1f;
setB_CF((op1_32 >> op2_32) & 0x01);
return;
}
index = op2_32 & 0x1f;
displacement32 = ((Bit32s) (op2_32&0xffffffe0)) / 32;
op1_addr = RMAddr(i) + 4 * displacement32;
@ -605,6 +597,17 @@ void BX_CPU_C::BT_EdGd(bxInstruction_c *i)
setB_CF((op1_32 >> index) & 0x01);
}
void BX_CPU_C::BT_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 &= 0x1f;
setB_CF((op1_32 >> op2_32) & 0x01);
}
#if BX_SUPPORT_X86_64
void BX_CPU_C::BT_EqGq(bxInstruction_c *i)
{
@ -669,7 +672,7 @@ void BX_CPU_C::BTS_EwGw(bxInstruction_c *i)
setB_CF(bit_i);
}
void BX_CPU_C::BTS_EdGd(bxInstruction_c *i)
void BX_CPU_C::BTS_EdGdM(bxInstruction_c *i)
{
bx_address op1_addr;
Bit32u op1_32, op2_32, bit_i, index;
@ -677,18 +680,6 @@ void BX_CPU_C::BTS_EdGd(bxInstruction_c *i)
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 &= 0x1f;
setB_CF((op1_32 >> op2_32) & 0x01);
op1_32 |= (((Bit32u) 1) << op2_32);
/* now write diff back to destination */
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
return;
}
index = op2_32 & 0x1f;
displacement32 = ((Bit32s) (op2_32&0xffffffe0)) / 32;
op1_addr = RMAddr(i) + 4 * displacement32;
@ -704,6 +695,20 @@ void BX_CPU_C::BTS_EdGd(bxInstruction_c *i)
setB_CF(bit_i);
}
void BX_CPU_C::BTS_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 &= 0x1f;
setB_CF((op1_32 >> op2_32) & 0x01);
op1_32 |= (((Bit32u) 1) << op2_32);
/* now write diff back to destination */
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
}
#if BX_SUPPORT_X86_64
void BX_CPU_C::BTS_EqGq(bxInstruction_c *i)
{
@ -778,7 +783,7 @@ void BX_CPU_C::BTR_EwGw(bxInstruction_c *i)
setB_CF(temp_cf);
}
void BX_CPU_C::BTR_EdGd(bxInstruction_c *i)
void BX_CPU_C::BTR_EdGdM(bxInstruction_c *i)
{
bx_address op1_addr;
Bit32u op1_32, op2_32, index;
@ -786,18 +791,6 @@ void BX_CPU_C::BTR_EdGd(bxInstruction_c *i)
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 &= 0x1f;
setB_CF((op1_32 >> op2_32) & 0x01);
op1_32 &= ~(((Bit32u) 1) << op2_32);
/* now write diff back to destination */
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
return;
}
index = op2_32 & 0x1f;
displacement32 = ((Bit32s) (op2_32&0xffffffe0)) / 32;
op1_addr = RMAddr(i) + 4 * displacement32;
@ -814,6 +807,20 @@ void BX_CPU_C::BTR_EdGd(bxInstruction_c *i)
setB_CF(temp_cf);
}
void BX_CPU_C::BTR_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 &= 0x1f;
setB_CF((op1_32 >> op2_32) & 0x01);
op1_32 &= ~(((Bit32u) 1) << op2_32);
/* now write diff back to destination */
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
}
#if BX_SUPPORT_X86_64
void BX_CPU_C::BTR_EqGq(bxInstruction_c *i)
{
@ -887,7 +894,7 @@ void BX_CPU_C::BTC_EwGw(bxInstruction_c *i)
setB_CF(temp_CF);
}
void BX_CPU_C::BTC_EdGd(bxInstruction_c *i)
void BX_CPU_C::BTC_EdGdM(bxInstruction_c *i)
{
bx_address op1_addr;
Bit32u op1_32, op2_32, index_32;
@ -896,28 +903,30 @@ void BX_CPU_C::BTC_EdGd(bxInstruction_c *i)
op2_32 = BX_READ_32BIT_REG(i->nnn());
index_32 = op2_32 & 0x1f;
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_addr = 0; // keep compiler happy
}
else {
displacement32 = ((Bit32s) (op2_32 & 0xffffffe0)) / 32;
op1_addr = RMAddr(i) + 4 * displacement32;
read_RMW_virtual_dword(i->seg(), op1_addr, &op1_32);
}
displacement32 = ((Bit32s) (op2_32 & 0xffffffe0)) / 32;
op1_addr = RMAddr(i) + 4 * displacement32;
read_RMW_virtual_dword(i->seg(), op1_addr, &op1_32);
bx_bool temp_CF = (op1_32 >> index_32) & 0x01;
op1_32 ^= (((Bit32u) 1) << index_32); /* toggle bit */
setB_CF(temp_CF);
/* now write diff back to destination */
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
}
else {
write_RMW_virtual_dword(op1_32);
}
write_RMW_virtual_dword(op1_32);
}
void BX_CPU_C::BTC_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 &= 0x1f;
bx_bool temp_CF = (op1_32 >> op2_32) & 0x01;
op1_32 ^= (((Bit32u) 1) << op2_32); /* toggle bit */
setB_CF(temp_CF);
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
}
#if BX_SUPPORT_X86_64

192
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.359 2007-11-16 21:43:23 sshwarts Exp $
// $Id: cpu.h,v 1.360 2007-11-17 12:44:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1372,7 +1372,6 @@ public: // for now...
// <TAG-CLASS-CPU-START>
// prototypes for CPU instructions...
BX_SMF void ADD_EbGb(bxInstruction_c *);
BX_SMF void ADD_EdGd(bxInstruction_c *);
BX_SMF void ADD_GbEb(bxInstruction_c *);
BX_SMF void ADD_GdEdM(bxInstruction_c *);
@ -1381,8 +1380,6 @@ public: // for now...
BX_SMF void ADD_ALIb(bxInstruction_c *);
BX_SMF void ADD_EAXId(bxInstruction_c *);
BX_SMF void OR_EbGb(bxInstruction_c *);
BX_SMF void OR_EdGd(bxInstruction_c *);
BX_SMF void OR_EwGw(bxInstruction_c *);
BX_SMF void OR_GbEb(bxInstruction_c *);
BX_SMF void OR_GdEd(bxInstruction_c *);
BX_SMF void OR_GwEw(bxInstruction_c *);
@ -1415,30 +1412,24 @@ public: // for now...
BX_SMF void POP32_SS(bxInstruction_c *);
BX_SMF void ADC_EbGb(bxInstruction_c *);
BX_SMF void ADC_EdGd(bxInstruction_c *);
BX_SMF void ADC_GbEb(bxInstruction_c *);
BX_SMF void ADC_GdEd(bxInstruction_c *);
BX_SMF void ADC_ALIb(bxInstruction_c *);
BX_SMF void ADC_EAXId(bxInstruction_c *);
BX_SMF void SBB_EbGb(bxInstruction_c *);
BX_SMF void SBB_EdGd(bxInstruction_c *);
BX_SMF void SBB_GbEb(bxInstruction_c *);
BX_SMF void SBB_GdEd(bxInstruction_c *);
BX_SMF void SBB_ALIb(bxInstruction_c *);
BX_SMF void SBB_EAXId(bxInstruction_c *);
BX_SMF void AND_EbGb(bxInstruction_c *);
BX_SMF void AND_EdGd(bxInstruction_c *);
BX_SMF void AND_EwGw(bxInstruction_c *);
BX_SMF void AND_GbEb(bxInstruction_c *);
BX_SMF void AND_GdEd(bxInstruction_c *);
BX_SMF void AND_GwEw(bxInstruction_c *);
BX_SMF void AND_ALIb(bxInstruction_c *);
BX_SMF void AND_EAXId(bxInstruction_c *);
BX_SMF void AND_AXIw(bxInstruction_c *);
BX_SMF void DAA(bxInstruction_c *);
BX_SMF void SUB_EbGb(bxInstruction_c *);
BX_SMF void SUB_EdGd(bxInstruction_c *);
BX_SMF void SUB_GbEb(bxInstruction_c *);
BX_SMF void SUB_GdEd(bxInstruction_c *);
BX_SMF void SUB_ALIb(bxInstruction_c *);
@ -1446,17 +1437,13 @@ public: // for now...
BX_SMF void DAS(bxInstruction_c *);
BX_SMF void XOR_EbGb(bxInstruction_c *);
BX_SMF void XOR_EdGd(bxInstruction_c *);
BX_SMF void XOR_EwGw(bxInstruction_c *);
BX_SMF void XOR_GbEb(bxInstruction_c *);
BX_SMF void XOR_GdEd(bxInstruction_c *);
BX_SMF void XOR_GwEw(bxInstruction_c *);
BX_SMF void XOR_ALIb(bxInstruction_c *);
BX_SMF void XOR_EAXId(bxInstruction_c *);
BX_SMF void XOR_AXIw(bxInstruction_c *);
BX_SMF void AAA(bxInstruction_c *);
BX_SMF void CMP_EbGb(bxInstruction_c *);
BX_SMF void CMP_EdGd(bxInstruction_c *);
BX_SMF void CMP_GbEb(bxInstruction_c *);
BX_SMF void CMP_GdEd(bxInstruction_c *);
BX_SMF void CMP_ALIb(bxInstruction_c *);
@ -1488,11 +1475,14 @@ public: // for now...
BX_SMF void BOUND_GwMa(bxInstruction_c *);
BX_SMF void BOUND_GdMa(bxInstruction_c *);
BX_SMF void TEST_EdGdR(bxInstruction_c *);
BX_SMF void TEST_EdGdM(bxInstruction_c *);
BX_SMF void TEST_EbGb(bxInstruction_c *);
BX_SMF void TEST_EdGd(bxInstruction_c *);
BX_SMF void TEST_EwGw(bxInstruction_c *);
BX_SMF void XCHG_EdGdR(bxInstruction_c *);
BX_SMF void XCHG_EdGdM(bxInstruction_c *);
BX_SMF void XCHG_EbGb(bxInstruction_c *);
BX_SMF void XCHG_EdGd(bxInstruction_c *);
BX_SMF void XCHG_EwGw(bxInstruction_c *);
BX_SMF void MOV_EbGbM(bxInstruction_c *);
@ -1567,11 +1557,16 @@ public: // for now...
BX_SMF void REP_LODSD_EAXXd(bxInstruction_c *);
BX_SMF void REP_SCASD_EAXXd(bxInstruction_c *);
BX_SMF void MOV_EdIdM(bxInstruction_c *);
BX_SMF void MOV_EwIwM(bxInstruction_c *);
BX_SMF void MOV_EbIbM(bxInstruction_c *);
BX_SMF void MOV_EdIdR(bxInstruction_c *);
BX_SMF void MOV_EwIwR(bxInstruction_c *);
BX_SMF void MOV_EbIbR(bxInstruction_c *);
BX_SMF void RETnear32(bxInstruction_c *);
BX_SMF void RETnear16(bxInstruction_c *);
BX_SMF void MOV_EbIb(bxInstruction_c *);
BX_SMF void MOV_EdId(bxInstruction_c *);
BX_SMF void MOV_EwIw(bxInstruction_c *);
BX_SMF void ENTER_IwIb(bxInstruction_c *);
BX_SMF void LEAVE(bxInstruction_c *);
BX_SMF void RETfar32(bxInstruction_c *);
@ -1697,21 +1692,26 @@ public: // for now...
BX_SMF void BSR_GwEw(bxInstruction_c *);
BX_SMF void BSR_GdEd(bxInstruction_c *);
BX_SMF void BT_EdGdR(bxInstruction_c *);
BX_SMF void BT_EdGdM(bxInstruction_c *);
BX_SMF void BTS_EdGdR(bxInstruction_c *);
BX_SMF void BTS_EdGdM(bxInstruction_c *);
BX_SMF void BTR_EdGdR(bxInstruction_c *);
BX_SMF void BTR_EdGdM(bxInstruction_c *);
BX_SMF void BTC_EdGdR(bxInstruction_c *);
BX_SMF void BTC_EdGdM(bxInstruction_c *);
BX_SMF void BT_EwGw(bxInstruction_c *);
BX_SMF void BT_EdGd(bxInstruction_c *);
BX_SMF void BT_EwIb(bxInstruction_c *);
BX_SMF void BT_EdIb(bxInstruction_c *);
BX_SMF void BTS_EwGw(bxInstruction_c *);
BX_SMF void BTS_EdGd(bxInstruction_c *);
BX_SMF void BTS_EwIb(bxInstruction_c *);
BX_SMF void BTS_EdIb(bxInstruction_c *);
BX_SMF void BTR_EwGw(bxInstruction_c *);
BX_SMF void BTR_EdGd(bxInstruction_c *);
BX_SMF void BTR_EwIb(bxInstruction_c *);
BX_SMF void BTR_EdIb(bxInstruction_c *);
BX_SMF void BTC_EwGw(bxInstruction_c *);
BX_SMF void BTC_EdGd(bxInstruction_c *);
BX_SMF void BTC_EwIb(bxInstruction_c *);
BX_SMF void BTC_EdIb(bxInstruction_c *);
@ -1735,23 +1735,6 @@ public: // for now...
BX_SMF void BSWAP_ERX(bxInstruction_c *);
BX_SMF void ADD_EdIdR(bxInstruction_c *);
BX_SMF void ADD_EdIdM(bxInstruction_c *);
BX_SMF void OR_EdIdR(bxInstruction_c *);
BX_SMF void OR_EdIdM(bxInstruction_c *);
BX_SMF void ADC_EdIdR(bxInstruction_c *);
BX_SMF void ADC_EdIdM(bxInstruction_c *);
BX_SMF void SBB_EdIdR(bxInstruction_c *);
BX_SMF void SBB_EdIdM(bxInstruction_c *);
BX_SMF void AND_EdIdR(bxInstruction_c *);
BX_SMF void AND_EdIdM(bxInstruction_c *);
BX_SMF void SUB_EdIdR(bxInstruction_c *);
BX_SMF void SUB_EdIdM(bxInstruction_c *);
BX_SMF void XOR_EdIdR(bxInstruction_c *);
BX_SMF void XOR_EdIdM(bxInstruction_c *);
BX_SMF void CMP_EdIdR(bxInstruction_c *);
BX_SMF void CMP_EdIdM(bxInstruction_c *);
BX_SMF void ADD_EbIb(bxInstruction_c *);
BX_SMF void OR_EbIb(bxInstruction_c *);
BX_SMF void ADC_EbIb(bxInstruction_c *);
@ -1762,22 +1745,82 @@ public: // for now...
BX_SMF void CMP_EbIb(bxInstruction_c *);
BX_SMF void ADD_EwIwM(bxInstruction_c *);
BX_SMF void ADD_EwIwR(bxInstruction_c *);
BX_SMF void OR_EwIwM(bxInstruction_c *);
BX_SMF void OR_EwIwR(bxInstruction_c *);
BX_SMF void ADC_EwIwM(bxInstruction_c *);
BX_SMF void ADC_EwIwR(bxInstruction_c *);
BX_SMF void SBB_EwIwM(bxInstruction_c *);
BX_SMF void SBB_EwIwR(bxInstruction_c *);
BX_SMF void AND_EwIwM(bxInstruction_c *);
BX_SMF void AND_EwIwR(bxInstruction_c *);
BX_SMF void SUB_EwIwM(bxInstruction_c *);
BX_SMF void SUB_EwIwR(bxInstruction_c *);
BX_SMF void XOR_EwIwM(bxInstruction_c *);
BX_SMF void XOR_EwIwR(bxInstruction_c *);
BX_SMF void CMP_EwIwM(bxInstruction_c *);
BX_SMF void ADD_EwIwR(bxInstruction_c *);
BX_SMF void OR_EwIwR(bxInstruction_c *);
BX_SMF void ADC_EwIwR(bxInstruction_c *);
BX_SMF void SBB_EwIwR(bxInstruction_c *);
BX_SMF void AND_EwIwR(bxInstruction_c *);
BX_SMF void SUB_EwIwR(bxInstruction_c *);
BX_SMF void XOR_EwIwR(bxInstruction_c *);
BX_SMF void CMP_EwIwR(bxInstruction_c *);
BX_SMF void ADD_EdIdM(bxInstruction_c *);
BX_SMF void OR_EdIdM(bxInstruction_c *);
BX_SMF void ADC_EdIdM(bxInstruction_c *);
BX_SMF void SBB_EdIdM(bxInstruction_c *);
BX_SMF void AND_EdIdM(bxInstruction_c *);
BX_SMF void SUB_EdIdM(bxInstruction_c *);
BX_SMF void XOR_EdIdM(bxInstruction_c *);
BX_SMF void CMP_EdIdM(bxInstruction_c *);
BX_SMF void ADD_EdIdR(bxInstruction_c *);
BX_SMF void OR_EdIdR(bxInstruction_c *);
BX_SMF void ADC_EdIdR(bxInstruction_c *);
BX_SMF void SBB_EdIdR(bxInstruction_c *);
BX_SMF void AND_EdIdR(bxInstruction_c *);
BX_SMF void SUB_EdIdR(bxInstruction_c *);
BX_SMF void XOR_EdIdR(bxInstruction_c *);
BX_SMF void CMP_EdIdR(bxInstruction_c *);
BX_SMF void ADD_EwGwM(bxInstruction_c *);
BX_SMF void OR_EwGwM(bxInstruction_c *);
BX_SMF void ADC_EwGwM(bxInstruction_c *);
BX_SMF void SBB_EwGwM(bxInstruction_c *);
BX_SMF void AND_EwGwM(bxInstruction_c *);
BX_SMF void SUB_EwGwM(bxInstruction_c *);
BX_SMF void XOR_EwGwM(bxInstruction_c *);
BX_SMF void CMP_EwGwM(bxInstruction_c *);
BX_SMF void ADD_EwGwR(bxInstruction_c *);
BX_SMF void OR_EwGwR(bxInstruction_c *);
BX_SMF void ADC_EwGwR(bxInstruction_c *);
BX_SMF void SBB_EwGwR(bxInstruction_c *);
BX_SMF void AND_EwGwR(bxInstruction_c *);
BX_SMF void SUB_EwGwR(bxInstruction_c *);
BX_SMF void XOR_EwGwR(bxInstruction_c *);
BX_SMF void CMP_EwGwR(bxInstruction_c *);
BX_SMF void ADD_EdGdM(bxInstruction_c *);
BX_SMF void OR_EdGdM(bxInstruction_c *);
BX_SMF void ADC_EdGdM(bxInstruction_c *);
BX_SMF void SBB_EdGdM(bxInstruction_c *);
BX_SMF void AND_EdGdM(bxInstruction_c *);
BX_SMF void SUB_EdGdM(bxInstruction_c *);
BX_SMF void XOR_EdGdM(bxInstruction_c *);
BX_SMF void CMP_EdGdM(bxInstruction_c *);
BX_SMF void ADD_EdGdR(bxInstruction_c *);
BX_SMF void OR_EdGdR(bxInstruction_c *);
BX_SMF void ADC_EdGdR(bxInstruction_c *);
BX_SMF void SBB_EdGdR(bxInstruction_c *);
BX_SMF void AND_EdGdR(bxInstruction_c *);
BX_SMF void SUB_EdGdR(bxInstruction_c *);
BX_SMF void XOR_EdGdR(bxInstruction_c *);
BX_SMF void CMP_EdGdR(bxInstruction_c *);
BX_SMF void AND_GdEd(bxInstruction_c *);
BX_SMF void XOR_GdEd(bxInstruction_c *);
BX_SMF void CMP_GwEw(bxInstruction_c *);
BX_SMF void ROL_Eb(bxInstruction_c *);
BX_SMF void ROR_Eb(bxInstruction_c *);
BX_SMF void RCL_Eb(bxInstruction_c *);
@ -1822,12 +1865,19 @@ public: // for now...
BX_SMF void IDIV_EAXEd(bxInstruction_c *);
BX_SMF void INC_EbR(bxInstruction_c *);
BX_SMF void INC_EbM(bxInstruction_c *);
BX_SMF void INC_EwR(bxInstruction_c *);
BX_SMF void INC_EdR(bxInstruction_c *);
BX_SMF void DEC_EbR(bxInstruction_c *);
BX_SMF void DEC_EbM(bxInstruction_c *);
BX_SMF void DEC_EwR(bxInstruction_c *);
BX_SMF void DEC_EdR(bxInstruction_c *);
BX_SMF void INC_EbM(bxInstruction_c *);
BX_SMF void INC_EwM(bxInstruction_c *);
BX_SMF void INC_EdM(bxInstruction_c *);
BX_SMF void DEC_EbM(bxInstruction_c *);
BX_SMF void DEC_EwM(bxInstruction_c *);
BX_SMF void DEC_EdM(bxInstruction_c *);
BX_SMF void INC_Ed(bxInstruction_c *);
BX_SMF void DEC_Ed(bxInstruction_c *);
BX_SMF void CALL_Ed(bxInstruction_c *);
BX_SMF void CALL_Ew(bxInstruction_c *);
BX_SMF void CALL32_Ep(bxInstruction_c *);
@ -1836,8 +1886,11 @@ public: // for now...
BX_SMF void JMP_Ew(bxInstruction_c *);
BX_SMF void JMP32_Ep(bxInstruction_c *);
BX_SMF void JMP16_Ep(bxInstruction_c *);
BX_SMF void PUSH_Ed(bxInstruction_c *);
BX_SMF void PUSH_Ew(bxInstruction_c *);
BX_SMF void PUSH_EwR(bxInstruction_c *);
BX_SMF void PUSH_EdR(bxInstruction_c *);
BX_SMF void PUSH_EwM(bxInstruction_c *);
BX_SMF void PUSH_EdM(bxInstruction_c *);
BX_SMF void SLDT_Ew(bxInstruction_c *);
BX_SMF void STR_Ew(bxInstruction_c *);
@ -2478,30 +2531,22 @@ public: // for now...
BX_SMF void CMOV_GdEd(bxInstruction_c *);
BX_SMF void CMOV_GwEw(bxInstruction_c *);
BX_SMF void CMP_EwGw(bxInstruction_c *);
BX_SMF void ADD_EwGw(bxInstruction_c *);
BX_SMF void ADD_GwEwR(bxInstruction_c *);
BX_SMF void ADD_GwEwM(bxInstruction_c *);
BX_SMF void ADD_AXIw(bxInstruction_c *);
BX_SMF void ADC_EwGw(bxInstruction_c *);
BX_SMF void ADC_GwEw(bxInstruction_c *);
BX_SMF void ADC_AXIw(bxInstruction_c *);
BX_SMF void SBB_EwGw(bxInstruction_c *);
BX_SMF void SBB_GwEw(bxInstruction_c *);
BX_SMF void SBB_AXIw(bxInstruction_c *);
BX_SMF void SUB_EwGw(bxInstruction_c *);
BX_SMF void SUB_GwEw(bxInstruction_c *);
BX_SMF void SUB_AXIw(bxInstruction_c *);
BX_SMF void CMP_GwEw(bxInstruction_c *);
BX_SMF void CMP_AXIw(bxInstruction_c *);
BX_SMF void CWDE(bxInstruction_c *);
BX_SMF void CDQ(bxInstruction_c *);
BX_SMF void XADD_EwGw(bxInstruction_c *);
BX_SMF void NEG_Ew(bxInstruction_c *);
BX_SMF void INC_Ew(bxInstruction_c *);
BX_SMF void DEC_Ew(bxInstruction_c *);
BX_SMF void CMPXCHG_EwGw(bxInstruction_c *);
BX_SMF void MUL_AXEw(bxInstruction_c *);
BX_SMF void IMUL_AXEw(bxInstruction_c *);
@ -2578,7 +2623,9 @@ public: // for now...
BX_SMF void MOV_OqAL(bxInstruction_c *);
BX_SMF void MOV_EqGq(bxInstruction_c *);
BX_SMF void MOV_GqEq(bxInstruction_c *);
BX_SMF void MOV_EqId(bxInstruction_c *);
BX_SMF void MOV_EqIdR(bxInstruction_c *);
BX_SMF void MOV_EqIdM(bxInstruction_c *);
BX_SMF void MOVSQ_XqYq(bxInstruction_c *);
BX_SMF void CMPSQ_XqYq(bxInstruction_c *);
@ -2675,13 +2722,16 @@ public: // for now...
BX_SMF void DIV_RAXEq(bxInstruction_c *);
BX_SMF void IDIV_RAXEq(bxInstruction_c *);
BX_SMF void INC_Eq(bxInstruction_c *);
BX_SMF void DEC_Eq(bxInstruction_c *);
BX_SMF void INC_EqR(bxInstruction_c *);
BX_SMF void DEC_EqR(bxInstruction_c *);
BX_SMF void INC_EqM(bxInstruction_c *);
BX_SMF void DEC_EqM(bxInstruction_c *);
BX_SMF void CALL_Eq(bxInstruction_c *);
BX_SMF void CALL64_Ep(bxInstruction_c *);
BX_SMF void JMP_Eq(bxInstruction_c *);
BX_SMF void JMP64_Ep(bxInstruction_c *);
BX_SMF void PUSH_Eq(bxInstruction_c *);
BX_SMF void PUSH_EqR(bxInstruction_c *);
BX_SMF void PUSH_EqM(bxInstruction_c *);
BX_SMF void PUSHF_Fq(bxInstruction_c *);
BX_SMF void POPF_Fq(bxInstruction_c *);
@ -2728,6 +2778,8 @@ public: // for now...
BX_SMF void CMPXCHG16B(bxInstruction_c *);
BX_SMF void POPCNT_GqEq(bxInstruction_c *);
BX_SMF void MOVNTI_MqGq(bxInstruction_c *i);
#endif // #if BX_SUPPORT_X86_64
BX_SMF void INVLPG(bxInstruction_c *);
@ -3531,11 +3583,11 @@ IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
#define BxGroupX 0x0070 // bits 6..4: opcode groups definition
#define BxGroupN 0x0010 // Group encoding: 001
#define BxPrefixSSE 0x0020 // Group encoding: 010
#define BxSplitMod11b 0x0030 // Group encoding: 011
#define BxFPGroup 0x0040 // Group encoding: 100
#define BxRMGroup 0x0050 // Group encoding: 101
#define Bx3ByteOpIndex 0x0060 // Group encoding: 110
#define Bx3ByteOpTable 0x0070 // Group encoding: 111
#define BxFPGroup 0x0030 // Group encoding: 011
#define BxRMGroup 0x0040 // Group encoding: 100
#define Bx3ByteOpIndex 0x0050 // Group encoding: 101
#define Bx3ByteOpTable 0x0060 // Group encoding: 110
// Group encoding: 111
#define BxPrefix 0x0080 // bit 7
#define BxLockable 0x0100 // bit 8

15
bochs/cpu/ctrl_xfer32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ctrl_xfer32.cc,v 1.52 2007-11-12 18:20:10 sshwarts Exp $
// $Id: ctrl_xfer32.cc,v 1.53 2007-11-17 12:44:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -213,12 +213,6 @@ void BX_CPU_C::CALL32_Ep(bxInstruction_c *i)
BX_CPU_THIS_PTR show_flag |= Flag_call;
#endif
/* op1_32 is a register or memory reference */
if (i->modC0()) {
BX_INFO(("CALL_Ep: op1 is a register"));
exception(BX_UD_EXCEPTION, 0, 0);
}
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
read_virtual_word(i->seg(), RMAddr(i)+4, &cs_raw);
@ -523,13 +517,6 @@ void BX_CPU_C::JMP32_Ep(bxInstruction_c *i)
invalidate_prefetch_q();
/* op1_32 is a register or memory reference */
if (i->modC0()) {
/* far indirect must specify a memory address */
BX_INFO(("JMP_Ep(): op1 is a register"));
exception(BX_UD_EXCEPTION, 0, 0);
}
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
read_virtual_word(i->seg(), RMAddr(i)+4, &cs_raw);

13
bochs/cpu/ctrl_xfer64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ctrl_xfer64.cc,v 1.52 2007-11-12 18:20:10 sshwarts Exp $
// $Id: ctrl_xfer64.cc,v 1.53 2007-11-17 12:44:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -171,12 +171,6 @@ void BX_CPU_C::CALL64_Ep(bxInstruction_c *i)
BX_CPU_THIS_PTR show_flag |= Flag_call;
#endif
/* op1_64 is a register or memory reference */
if (i->modC0()) {
BX_ERROR(("CALL64_Ep: op1 is a register"));
exception(BX_UD_EXCEPTION, 0, 0);
}
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
read_virtual_word(i->seg(), RMAddr(i)+8, &cs_raw);
@ -432,11 +426,6 @@ void BX_CPU_C::JMP64_Ep(bxInstruction_c *i)
invalidate_prefetch_q();
if (i->modC0()) {
BX_ERROR(("JMP64_Ep(): op1 is a register"));
exception(BX_UD_EXCEPTION, 0, 0);
}
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
read_virtual_word(i->seg(), RMAddr(i)+4, &cs_raw);

23
bochs/cpu/data_xfer16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer16.cc,v 1.42 2007-11-16 08:30:21 sshwarts Exp $
// $Id: data_xfer16.cc,v 1.43 2007-11-17 12:44:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -127,11 +127,6 @@ void BX_CPU_C::MOV_SwEw(bxInstruction_c *i)
void BX_CPU_C::LEA_GwM(bxInstruction_c *i)
{
if (i->modC0()) {
BX_INFO(("LEA_GwM: op2 is a register"));
UndefinedOpcode(i);
}
BX_WRITE_16BIT_REG(i->nnn(), (Bit16u) RMAddr(i));
}
@ -145,17 +140,15 @@ void BX_CPU_C::MOV_OdAX(bxInstruction_c *i)
write_virtual_word(i->seg(), i->Id(), &AX);
}
void BX_CPU_C::MOV_EwIw(bxInstruction_c *i)
void BX_CPU_C::MOV_EwIwM(bxInstruction_c *i)
{
Bit16u op2_16 = i->Iw();
Bit16u op_16 = i->Iw();
write_virtual_word(i->seg(), RMAddr(i), &op_16);
}
/* now write sum back to destination */
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), op2_16);
}
else {
write_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
void BX_CPU_C::MOV_EwIwR(bxInstruction_c *i)
{
BX_WRITE_16BIT_REG(i->rm(), i->Iw());
}
#if BX_CPU_LEVEL >= 3

51
bochs/cpu/data_xfer32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer32.cc,v 1.42 2007-11-16 08:30:21 sshwarts Exp $
// $Id: data_xfer32.cc,v 1.43 2007-11-17 12:44:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -79,12 +79,6 @@ void BX_CPU_C::MOV_GdEdM(bxInstruction_c *i)
void BX_CPU_C::LEA_GdM(bxInstruction_c *i)
{
if (i->modC0()) {
BX_INFO(("LEA_GdM: op2 is a register"));
UndefinedOpcode(i);
}
/* write effective address of op2 in op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), RMAddr(i));
}
@ -99,20 +93,17 @@ void BX_CPU_C::MOV_OdEAX(bxInstruction_c *i)
write_virtual_dword(i->seg(), i->Id(), &EAX);
}
void BX_CPU_C::MOV_EdId(bxInstruction_c *i)
void BX_CPU_C::MOV_EdIdM(bxInstruction_c *i)
{
Bit32u op2_32 = i->Id();
/* now write sum back to destination */
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
}
else {
write_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
Bit32u op_32 = i->Id();
write_virtual_dword(i->seg(), RMAddr(i), &op_32);
}
void BX_CPU_C::MOV_EdIdR(bxInstruction_c *i)
{
BX_WRITE_32BIT_REGZ(i->rm(), i->Id());
}
#if BX_CPU_LEVEL >= 3
void BX_CPU_C::MOVZX_GdEb(bxInstruction_c *i)
{
Bit8u op2_8;
@ -176,25 +167,25 @@ void BX_CPU_C::MOVSX_GdEw(bxInstruction_c *i)
/* sign extend word op2 into dword op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), (Bit16s) op2_16);
}
#endif
void BX_CPU_C::XCHG_EdGd(bxInstruction_c *i)
void BX_CPU_C::XCHG_EdGdM(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op2_32 = BX_READ_32BIT_REG(i->nnn());
write_RMW_virtual_dword(op2_32);
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
write_RMW_virtual_dword(op2_32);
}
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
}
void BX_CPU_C::XCHG_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op2_32 = BX_READ_32BIT_REG(i->nnn());
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
}

25
bochs/cpu/data_xfer64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer64.cc,v 1.25 2007-01-12 22:47:20 sshwarts Exp $
// $Id: data_xfer64.cc,v 1.26 2007-11-17 12:44:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -74,12 +74,6 @@ void BX_CPU_C::MOV_GqEq(bxInstruction_c *i)
void BX_CPU_C::LEA_GqM(bxInstruction_c *i)
{
if (i->modC0()) {
BX_INFO(("LEA_GqM: op2 is a register"));
UndefinedOpcode(i);
}
/* write effective address of op2 in op1 */
BX_WRITE_64BIT_REG(i->nnn(), RMAddr(i));
}
@ -128,17 +122,16 @@ void BX_CPU_C::MOV_OqRAX(bxInstruction_c *i)
write_virtual_qword(i->seg(), i->Iq(), &RAX);
}
void BX_CPU_C::MOV_EqId(bxInstruction_c *i)
void BX_CPU_C::MOV_EqIdM(bxInstruction_c *i)
{
Bit64u op2_64 = (Bit32s) i->Id();
Bit64u op_64 = (Bit32s) i->Id();
write_virtual_qword(i->seg(), RMAddr(i), &op_64);
}
/* now write sum back to destination */
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), op2_64);
}
else {
write_virtual_qword(i->seg(), RMAddr(i), &op2_64);
}
void BX_CPU_C::MOV_EqIdR(bxInstruction_c *i)
{
Bit64u op_64 = (Bit32s) i->Id();
BX_WRITE_64BIT_REG(i->rm(), op_64);
}
void BX_CPU_C::MOVZX_GqEb(bxInstruction_c *i)

27
bochs/cpu/data_xfer8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer8.cc,v 1.27 2007-11-16 08:30:21 sshwarts Exp $
// $Id: data_xfer8.cc,v 1.28 2007-11-17 12:44:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -33,7 +33,7 @@
void BX_CPU_C::MOV_RLIb(bxInstruction_c *i)
{
BX_READ_8BIT_REGx(i->opcodeReg(),i->extend8bitL()) = i->Ib();
BX_READ_8BIT_REGx(i->opcodeReg(), i->extend8bitL()) = i->Ib();
}
void BX_CPU_C::MOV_RHIb(bxInstruction_c *i)
@ -43,23 +43,23 @@ void BX_CPU_C::MOV_RHIb(bxInstruction_c *i)
void BX_CPU_C::MOV_EbGbM(bxInstruction_c *i)
{
write_virtual_byte(i->seg(), RMAddr(i), &BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL()));
write_virtual_byte(i->seg(), RMAddr(i), &BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL()));
}
void BX_CPU_C::MOV_EbGbR(bxInstruction_c *i)
{
Bit8u op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
Bit8u op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op2);
}
void BX_CPU_C::MOV_GbEbM(bxInstruction_c *i)
{
read_virtual_byte(i->seg(), RMAddr(i), &BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL()));
read_virtual_byte(i->seg(), RMAddr(i), &BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL()));
}
void BX_CPU_C::MOV_GbEbR(bxInstruction_c *i)
{
Bit8u op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
Bit8u op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op2);
}
@ -73,16 +73,15 @@ void BX_CPU_C::MOV_OdAL(bxInstruction_c *i)
write_virtual_byte(i->seg(), i->Id(), &AL);
}
void BX_CPU_C::MOV_EbIb(bxInstruction_c *i)
void BX_CPU_C::MOV_EbIbM(bxInstruction_c *i)
{
Bit8u op2 = i->Ib();
Bit8u op_8 = i->Ib();
write_virtual_byte(i->seg(), RMAddr(i), &op_8);
}
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op2);
}
else {
write_virtual_byte(i->seg(), RMAddr(i), &op2);
}
void BX_CPU_C::MOV_EbIbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), i->Ib());
}
void BX_CPU_C::XLAT(bxInstruction_c *i)

3269
bochs/cpu/fetchdecode.cc
View File

File diff suppressed because it is too large Load Diff

212
bochs/cpu/fetchdecode.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.h,v 1.37 2007-11-16 21:43:23 sshwarts Exp $
// $Id: fetchdecode.h,v 1.38 2007-11-17 12:44:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005 Stanislav Shwartsman
@ -66,47 +66,6 @@ BX_CPP_INLINE Bit64u FetchQWORD(Bit8u *iptr)
// Common FetchDecode Opcode Tables
//
static const BxOpcodeInfo_t opcodesADD_GwEw[2] = {
/* M */ { 0, &BX_CPU_C::ADD_GwEwM },
/* R */ { 0, &BX_CPU_C::ADD_GwEwR }
};
static const BxOpcodeInfo_t opcodesADD_GdEd[2] = {
/* M */ { 0, &BX_CPU_C::ADD_GdEdM },
/* R */ { 0, &BX_CPU_C::ADD_GdEdR }
};
static const BxOpcodeInfo_t opcodesMOV_GbEb[2] = {
/* M */ { 0, &BX_CPU_C::MOV_GbEbM },
/* R */ { 0, &BX_CPU_C::MOV_GbEbR }
};
static const BxOpcodeInfo_t opcodesMOV_GwEw[2] = {
/* M */ { 0, &BX_CPU_C::MOV_GwEwM },
/* R */ { 0, &BX_CPU_C::MOV_GwEwR }
};
static const BxOpcodeInfo_t opcodesMOV_GdEd[2] = {
/* M */ { 0, &BX_CPU_C::MOV_GdEdM },
/* R */ { 0, &BX_CPU_C::MOV_GdEdR }
};
static const BxOpcodeInfo_t opcodesMOV_EbGb[2] = {
/* M */ { 0, &BX_CPU_C::MOV_EbGbM },
/* R */ { 0, &BX_CPU_C::MOV_EbGbR }
};
static const BxOpcodeInfo_t opcodesMOV_EwGw[2] = {
/* M */ { 0, &BX_CPU_C::MOV_EwGwM },
/* R */ { 0, &BX_CPU_C::MOV_EwGwR }
};
static const BxOpcodeInfo_t opcodesMOV_EdGd[2] = {
/* M */ { 0, &BX_CPU_C::MOV_EdGdM },
/* R */ { 0, &BX_CPU_C::MOV_EdGdR }
};
#if BX_SUPPORT_FPU
/* ************************************************************************ */
@ -1095,7 +1054,7 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2a[4] = {
/* F3 */ { 0, &BX_CPU_C::CVTSI2SS_VssEd }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2b[4] = {
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2bM[4] = {
/* -- */ { 0, &BX_CPU_C::MOVNTPS_MpsVps },
/* 66 */ { 0, &BX_CPU_C::MOVNTPD_MpdVpd },
/* F2 */ { 0, &BX_CPU_C::BxError },
@ -1440,13 +1399,22 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fc2[4] = {
/* F3 */ { 0, &BX_CPU_C::CMPSS_VssWssIb }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fc3[4] = {
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fc3M[4] = {
/* -- */ { 0, &BX_CPU_C::MOVNTI_MdGd },
/* 66 */ { 0, &BX_CPU_C::BxError },
/* F2 */ { 0, &BX_CPU_C::BxError },
/* F3 */ { 0, &BX_CPU_C::BxError }
};
#if BX_SUPPORT_X86_64
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fc3qM[4] = {
/* -- */ { 0, &BX_CPU_C::MOVNTI_MqGq },
/* 66 */ { 0, &BX_CPU_C::BxError },
/* F2 */ { 0, &BX_CPU_C::BxError },
/* F3 */ { 0, &BX_CPU_C::BxError }
};
#endif
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fc4[4] = {
/* -- */ { BxImmediate_Ib, &BX_CPU_C::PINSRW_PqEwIb },
/* 66 */ { BxImmediate_Ib, &BX_CPU_C::PINSRW_VdqEwIb },
@ -1629,7 +1597,7 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fe6[4] = {
/* F3 */ { 0, &BX_CPU_C::CVTDQ2PD_VpdWq }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fe7[4] = {
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fe7M[4] = {
/* -- */ { 0, &BX_CPU_C::MOVNTQ_MqPq },
/* 66 */ { 0, &BX_CPU_C::MOVNTDQ_MdqVdq },
/* F2 */ { 0, &BX_CPU_C::BxError },
@ -1692,7 +1660,7 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fef[4] = {
/* F3 */ { 0, &BX_CPU_C::BxError }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0ff0[4] = {
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0ff0M[4] = {
/* -- */ { 0, &BX_CPU_C::BxError },
/* 66 */ { 0, &BX_CPU_C::BxError },
/* F2 */ { 0, &BX_CPU_C::LDDQU_VdqMdq }, // SSE3
@ -2657,12 +2625,6 @@ static const BxOpcodeInfo_t BxOpcodeInfoG1EwR[8] = {
/* 7 */ { 0, &BX_CPU_C::CMP_EwIwR }
};
static const BxOpcodeInfo_t BxOpcodeInfoModG1Ew[8] = {
// attributes defined in main area
/* M */ { BxGroupN, NULL, BxOpcodeInfoG1EwM },
/* R */ { BxGroupN, NULL, BxOpcodeInfoG1EwR }
};
static const BxOpcodeInfo_t BxOpcodeInfoG1EdM[8] = {
// attributes defined in main area
/* 0 */ { BxLockable, &BX_CPU_C::ADD_EdIdM },
@ -2687,12 +2649,6 @@ static const BxOpcodeInfo_t BxOpcodeInfoG1EdR[8] = {
/* 7 */ { 0, &BX_CPU_C::CMP_EdIdR }
};
static const BxOpcodeInfo_t BxOpcodeInfoModG1Ed[8] = {
// attributes defined in main area
/* M */ { BxGroupN, NULL, BxOpcodeInfoG1EdM },
/* R */ { BxGroupN, NULL, BxOpcodeInfoG1EdR }
};
#if BX_SUPPORT_X86_64
static const BxOpcodeInfo_t BxOpcodeInfo64G1Eq[8] = {
// attributes defined in main area
@ -2837,71 +2793,122 @@ static const BxOpcodeInfo_t BxOpcodeInfoG4R[8] = {
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static const BxOpcodeInfo_t BxOpcodeInfoModG4[8] = {
// attributes defined in main area
/* M */ { BxGroupN, NULL, BxOpcodeInfoG4M },
/* R */ { BxGroupN, NULL, BxOpcodeInfoG4R }
};
/* ******* */
/* Group 5 */
/* ******* */
static const BxOpcodeInfo_t BxOpcodeInfoG5w[8] = {
static const BxOpcodeInfo_t BxOpcodeInfoG5wM[8] = {
// attributes defined in main area
/* 0 */ { BxLockable, &BX_CPU_C::INC_Ew },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_Ew },
/* 0 */ { BxLockable, &BX_CPU_C::INC_EwM },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EwM },
/* 2 */ { 0, &BX_CPU_C::CALL_Ew },
/* 3 */ { 0, &BX_CPU_C::CALL16_Ep },
/* 3 */ { 0, &BX_CPU_C::CALL16_Ep },
/* 4 */ { 0, &BX_CPU_C::JMP_Ew },
/* 5 */ { 0, &BX_CPU_C::JMP16_Ep },
/* 6 */ { 0, &BX_CPU_C::PUSH_Ew },
/* 6 */ { 0, &BX_CPU_C::PUSH_EwM },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static const BxOpcodeInfo_t BxOpcodeInfoG5d[8] = {
static const BxOpcodeInfo_t BxOpcodeInfoG5wR[8] = {
// attributes defined in main area
/* 0 */ { BxLockable, &BX_CPU_C::INC_Ed },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_Ed },
/* 0 */ { BxLockable, &BX_CPU_C::INC_EwR },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EwR },
/* 2 */ { 0, &BX_CPU_C::CALL_Ew },
/* 3 */ { 0, &BX_CPU_C::BxError }, // CALL16_Ep
/* 4 */ { 0, &BX_CPU_C::JMP_Ew },
/* 5 */ { 0, &BX_CPU_C::BxError }, // JMP16_Ep
/* 6 */ { 0, &BX_CPU_C::PUSH_EwR },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static const BxOpcodeInfo_t BxOpcodeInfoG5dM[8] = {
// attributes defined in main area
/* 0 */ { BxLockable, &BX_CPU_C::INC_EdM },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EdM },
/* 2 */ { 0, &BX_CPU_C::CALL_Ed },
/* 3 */ { 0, &BX_CPU_C::CALL32_Ep },
/* 4 */ { 0, &BX_CPU_C::JMP_Ed },
/* 5 */ { 0, &BX_CPU_C::JMP32_Ep },
/* 6 */ { 0, &BX_CPU_C::PUSH_Ed },
/* 6 */ { 0, &BX_CPU_C::PUSH_EdM },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static const BxOpcodeInfo_t BxOpcodeInfoG5dR[8] = {
// attributes defined in main area
/* 0 */ { BxLockable, &BX_CPU_C::INC_EdR },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EdR },
/* 2 */ { 0, &BX_CPU_C::CALL_Ed },
/* 3 */ { 0, &BX_CPU_C::BxError }, // CALL32_Ep
/* 4 */ { 0, &BX_CPU_C::JMP_Ed },
/* 5 */ { 0, &BX_CPU_C::BxError }, // JMP32_Ep
/* 6 */ { 0, &BX_CPU_C::PUSH_EdR },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
#if BX_SUPPORT_X86_64
static const BxOpcodeInfo_t BxOpcodeInfo64G5w[8] = {
/* 0 */ { BxLockable, &BX_CPU_C::INC_Ew },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_Ew },
static const BxOpcodeInfo_t BxOpcodeInfo64G5wM[8] = {
/* 0 */ { BxLockable, &BX_CPU_C::INC_EwM },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EwM },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::CALL16_Ep },
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::JMP16_Ep },
/* 6 */ { 0, &BX_CPU_C::PUSH_Ew },
/* 6 */ { 0, &BX_CPU_C::PUSH_EwM },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static const BxOpcodeInfo_t BxOpcodeInfo64G5d[8] = {
/* 0 */ { BxLockable, &BX_CPU_C::INC_Ed },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_Ed },
static const BxOpcodeInfo_t BxOpcodeInfo64G5wR[8] = {
/* 0 */ { BxLockable, &BX_CPU_C::INC_EwR },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EwR },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::BxError }, // CALL16_Ep
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::BxError }, // JMP16_Ep
/* 6 */ { 0, &BX_CPU_C::PUSH_EwR },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static const BxOpcodeInfo_t BxOpcodeInfo64G5dM[8] = {
/* 0 */ { BxLockable, &BX_CPU_C::INC_EdM },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EdM },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::CALL32_Ep },
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::JMP32_Ep },
/* 6 */ { 0, &BX_CPU_C::PUSH_Eq },
/* 6 */ { 0, &BX_CPU_C::PUSH_EqM },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static const BxOpcodeInfo_t BxOpcodeInfo64G5q[8] = {
/* 0 */ { BxLockable, &BX_CPU_C::INC_Eq },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_Eq },
static const BxOpcodeInfo_t BxOpcodeInfo64G5dR[8] = {
/* 0 */ { BxLockable, &BX_CPU_C::INC_EdR },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EdR },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::BxError }, // CALL32_Ep
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::BxError }, // JMP32_Ep
/* 6 */ { 0, &BX_CPU_C::PUSH_EqR },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static const BxOpcodeInfo_t BxOpcodeInfo64G5qM[8] = {
/* 0 */ { BxLockable, &BX_CPU_C::INC_EqM },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EqM },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::CALL64_Ep },
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::JMP64_Ep },
/* 6 */ { 0, &BX_CPU_C::PUSH_Eq },
/* 6 */ { 0, &BX_CPU_C::PUSH_EqM },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static const BxOpcodeInfo_t BxOpcodeInfo64G5qR[8] = {
/* 0 */ { BxLockable, &BX_CPU_C::INC_EqR },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EqR },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::BxError }, // CALL64_Ep
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::BxError }, // JMP64_Ep
/* 6 */ { 0, &BX_CPU_C::PUSH_EqR },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
#endif
@ -2967,12 +2974,6 @@ static const BxOpcodeInfo_t BxOpcodeInfoG7M[8] = {
/* 7 */ { 0, &BX_CPU_C::INVLPG }
};
static const BxOpcodeInfo_t BxOpcodeInfoModG7[2] = {
// attributes defined in main area
/* M */ { BxGroupN, NULL, BxOpcodeInfoG7M },
/* R */ { BxGroupN, NULL, BxOpcodeInfoG7R }
};
#if BX_SUPPORT_X86_64
static const BxOpcodeInfo_t opcodesGroup64RmINVLPG[8] = {
/* 0 */ { 0, &BX_CPU_C::SWAPGS },
@ -3006,12 +3007,6 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G7M[8] = {
/* 6 */ { 0, &BX_CPU_C::LMSW_Ew },
/* 7 */ { 0, &BX_CPU_C::INVLPG }
};
static const BxOpcodeInfo_t BxOpcodeInfo64ModG7[2] = {
// attributes defined in main area
/* M */ { BxGroupN, NULL, BxOpcodeInfo64G7M },
/* R */ { BxGroupN, NULL, BxOpcodeInfo64G7R }
};
#endif
@ -3058,7 +3053,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G8EqIb[8] = {
/* Group 9 */
/* ******* */
static const BxOpcodeInfo_t BxOpcodeInfoG9[8] = {
static const BxOpcodeInfo_t BxOpcodeInfoG9M[8] = {
/* 0 */ { 0, &BX_CPU_C::BxError },
/* 1 */ { BxLockable, &BX_CPU_C::CMPXCHG8B },
/* 2 */ { 0, &BX_CPU_C::BxError },
@ -3070,7 +3065,7 @@ static const BxOpcodeInfo_t BxOpcodeInfoG9[8] = {
};
#if BX_SUPPORT_X86_64
static const BxOpcodeInfo_t BxOpcodeInfo64G9q[8] = {
static const BxOpcodeInfo_t BxOpcodeInfo64G9qM[8] = {
/* 0 */ { 0, &BX_CPU_C::BxError },
/* 1 */ { BxLockable, &BX_CPU_C::CMPXCHG16B },
/* 2 */ { 0, &BX_CPU_C::BxError },
@ -3131,15 +3126,26 @@ static const BxOpcodeInfo_t BxOpcodeInfoG14[8] = {
/* Group 15 */
/* ******** */
static const BxOpcodeInfo_t BxOpcodeInfoG15[8] = {
static const BxOpcodeInfo_t BxOpcodeInfoG15M[8] = {
/* 0 */ { 0, &BX_CPU_C::FXSAVE },
/* 1 */ { 0, &BX_CPU_C::FXRSTOR },
/* 2 */ { 0, &BX_CPU_C::LDMXCSR },
/* 3 */ { 0, &BX_CPU_C::STMXCSR },
/* 4 */ { 0, &BX_CPU_C::BxError },
/* 5 */ { 0, &BX_CPU_C::NOP }, /* LFENCE */
/* 6 */ { 0, &BX_CPU_C::NOP }, /* MFENCE */
/* 7 */ { 0, &BX_CPU_C::CLFLUSH } /* SFENCE/CFLUSH */
/* 5 */ { 0, &BX_CPU_C::BxError },
/* 6 */ { 0, &BX_CPU_C::BxError },
/* 7 */ { 0, &BX_CPU_C::CLFLUSH }
};
static const BxOpcodeInfo_t BxOpcodeInfoG15R[8] = {
/* 0 */ { 0, &BX_CPU_C::BxError },
/* 1 */ { 0, &BX_CPU_C::BxError },
/* 2 */ { 0, &BX_CPU_C::BxError },
/* 3 */ { 0, &BX_CPU_C::BxError },
/* 4 */ { 0, &BX_CPU_C::BxError },
/* 5 */ { 0, &BX_CPU_C::NOP }, /* LFENCE */
/* 6 */ { 0, &BX_CPU_C::NOP }, /* MFENCE */
/* 7 */ { 0, &BX_CPU_C::NOP } /* SFENCE */
};
#endif // BX_COMMON_FETCHDECODE_TABLES_H

4718
bochs/cpu/fetchdecode64.cc
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File diff suppressed because it is too large Load Diff

79
bochs/cpu/logical16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: logical16.cc,v 1.30 2007-11-16 17:45:58 sshwarts Exp $
// $Id: logical16.cc,v 1.31 2007-11-17 12:44:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -24,30 +24,29 @@
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
void BX_CPU_C::XOR_EwGw(bxInstruction_c *i)
void BX_CPU_C::XOR_EwGwM(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op2_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 ^= op2_16;
write_RMW_virtual_word(op1_16);
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
SET_FLAGS_OSZAPC_RESULT_16(op1_16, BX_INSTR_LOGIC16);
}
op1_16 ^= op2_16;
BX_WRITE_16BIT_REG(i->rm(), op1_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op1_16 ^= op2_16;
write_RMW_virtual_word(op1_16);
}
void BX_CPU_C::XOR_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op2_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 ^= op2_16;
BX_WRITE_16BIT_REG(i->rm(), op1_16);
SET_FLAGS_OSZAPC_RESULT_16(op1_16, BX_INSTR_LOGIC16);
}
@ -140,22 +139,26 @@ void BX_CPU_C::NOT_Ew(bxInstruction_c *i)
}
}
void BX_CPU_C::OR_EwGw(bxInstruction_c *i)
void BX_CPU_C::OR_EwGwM(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op2_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 |= op2_16;
write_RMW_virtual_word(op1_16);
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
op1_16 |= op2_16;
BX_WRITE_16BIT_REG(i->rm(), op1_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op1_16 |= op2_16;
write_RMW_virtual_word(op1_16);
}
SET_FLAGS_OSZAPC_RESULT_16(op1_16, BX_INSTR_LOGIC16);
}
void BX_CPU_C::OR_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 |= op2_16;
BX_WRITE_16BIT_REG(i->rm(), op1_16);
SET_FLAGS_OSZAPC_RESULT_16(op1_16, BX_INSTR_LOGIC16);
}
@ -191,22 +194,26 @@ void BX_CPU_C::OR_AXIw(bxInstruction_c *i)
SET_FLAGS_OSZAPC_RESULT_16(op1_16, BX_INSTR_LOGIC16);
}
void BX_CPU_C::AND_EwGw(bxInstruction_c *i)
void BX_CPU_C::AND_EwGwM(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op2_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 &= op2_16;
write_RMW_virtual_word(op1_16);
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
op1_16 &= op2_16;
BX_WRITE_16BIT_REG(i->rm(), op1_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
op1_16 &= op2_16;
write_RMW_virtual_word(op1_16);
}
SET_FLAGS_OSZAPC_RESULT_16(op1_16, BX_INSTR_LOGIC16);
}
void BX_CPU_C::AND_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 &= op2_16;
BX_WRITE_16BIT_REG(i->rm(), op1_16);
SET_FLAGS_OSZAPC_RESULT_16(op1_16, BX_INSTR_LOGIC16);
}

98
bochs/cpu/logical32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: logical32.cc,v 1.31 2007-11-16 17:45:58 sshwarts Exp $
// $Id: logical32.cc,v 1.32 2007-11-17 12:44:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -35,22 +35,26 @@
#define RAX EAX
#endif
void BX_CPU_C::XOR_EdGd(bxInstruction_c *i)
void BX_CPU_C::XOR_EdGdM(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 ^= op2_32;
write_RMW_virtual_dword(op1_32);
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 ^= op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op1_32 ^= op2_32;
write_RMW_virtual_dword(op1_32);
}
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_LOGIC32);
}
void BX_CPU_C::XOR_EdGdR(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 ^= op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_LOGIC32);
}
@ -143,22 +147,26 @@ void BX_CPU_C::NOT_Ed(bxInstruction_c *i)
}
}
void BX_CPU_C::OR_EdGd(bxInstruction_c *i)
void BX_CPU_C::OR_EdGdM(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 |= op2_32;
write_RMW_virtual_dword(op1_32);
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 |= op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op1_32 |= op2_32;
write_RMW_virtual_dword(op1_32);
}
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_LOGIC32);
}
void BX_CPU_C::OR_EdGdR(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 |= op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_LOGIC32);
}
@ -196,22 +204,26 @@ void BX_CPU_C::OR_EAXId(bxInstruction_c *i)
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_LOGIC32);
}
void BX_CPU_C::AND_EdGd(bxInstruction_c *i)
void BX_CPU_C::AND_EdGdM(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 &= op2_32;
write_RMW_virtual_dword(op1_32);
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 &= op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op1_32 &= op2_32;
write_RMW_virtual_dword(op1_32);
}
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_LOGIC32);
}
void BX_CPU_C::AND_EdGdR(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 &= op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_LOGIC32);
}
@ -269,19 +281,23 @@ void BX_CPU_C::AND_EdIdR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_LOGIC32);
}
void BX_CPU_C::TEST_EdGd(bxInstruction_c *i)
void BX_CPU_C::TEST_EdGdM(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 &= op2_32;
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_LOGIC32);
}
void BX_CPU_C::TEST_EdGdR(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 &= op2_32;
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_LOGIC32);

9
bochs/cpu/mmx.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: mmx.cc,v 1.62 2007-10-11 18:11:59 sshwarts Exp $
// $Id: mmx.cc,v 1.63 2007-11-17 12:44:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002 Stanislav Shwartsman
@ -1958,16 +1958,9 @@ void BX_CPU_C::PMULHW_PqQq(bxInstruction_c *i)
void BX_CPU_C::MOVNTQ_MqPq(bxInstruction_c *i)
{
#if BX_SUPPORT_3DNOW || BX_SUPPORT_SSE >= 1
if (i->modC0()) {
BX_INFO(("MOVNTQ_MqPq: must be memory reference"));
UndefinedOpcode(i);
}
BX_CPU_THIS_PTR prepareMMX();
BxPackedMmxRegister reg = BX_READ_MMX_REG(i->nnn());
write_virtual_qword(i->seg(), RMAddr(i), (Bit64u *) &reg);
#else
BX_INFO(("MOVNTQ_MqPq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);

8
bochs/cpu/proc_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: proc_ctrl.cc,v 1.179 2007-11-09 12:06:34 sshwarts Exp $
// $Id: proc_ctrl.cc,v 1.180 2007-11-17 12:44:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -41,7 +41,7 @@
void BX_CPU_C::UndefinedOpcode(bxInstruction_c *i)
{
BX_DEBUG(("UndefinedOpcode: %02x causes exception 6", (unsigned) i->b1()));
BX_DEBUG(("UndefinedOpcode: 0x%02x causes exception 6", (unsigned) i->b1()));
exception(BX_UD_EXCEPTION, 0, 0);
}
@ -182,10 +182,6 @@ void BX_CPU_C::WBINVD(bxInstruction_c *i)
void BX_CPU_C::CLFLUSH(bxInstruction_c *i)
{
if (i->modC0()) {
return; // SFENCE instruction
}
#if BX_SUPPORT_CLFLUSH
// check if we could access the memory
execute_virtual_checks(&BX_CPU_THIS_PTR sregs[i->seg()], RMAddr(i), 1);

67
bochs/cpu/segment_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: segment_ctrl.cc,v 1.15 2007-04-09 20:28:15 sshwarts Exp $
// $Id: segment_ctrl.cc,v 1.16 2007-11-17 12:44:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -35,11 +35,6 @@
void BX_CPU_C::LES_GwMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LES_GwMp: invalid use of LES, must be memory reference!"));
UndefinedOpcode(i);
}
Bit16u reg_16, es;
read_virtual_word(i->seg(), RMAddr(i), &reg_16);
@ -52,11 +47,6 @@ void BX_CPU_C::LES_GwMp(bxInstruction_c *i)
void BX_CPU_C::LES_GdMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LES_GdMp: invalid use of LES, must be memory reference!"));
UndefinedOpcode(i);
}
Bit16u es;
Bit32u reg_32;
@ -70,11 +60,6 @@ void BX_CPU_C::LES_GdMp(bxInstruction_c *i)
void BX_CPU_C::LDS_GwMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LDS_GwMp: invalid use of LDS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit16u reg_16, ds;
read_virtual_word(i->seg(), RMAddr(i), &reg_16);
@ -87,11 +72,6 @@ void BX_CPU_C::LDS_GwMp(bxInstruction_c *i)
void BX_CPU_C::LDS_GdMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LDS_GdMp: invalid use of LDS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit16u ds;
Bit32u reg_32;
@ -105,11 +85,6 @@ void BX_CPU_C::LDS_GdMp(bxInstruction_c *i)
void BX_CPU_C::LFS_GwMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LFS_GwMp: invalid use of LFS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit16u reg_16, fs;
read_virtual_word(i->seg(), RMAddr(i), &reg_16);
@ -122,11 +97,6 @@ void BX_CPU_C::LFS_GwMp(bxInstruction_c *i)
void BX_CPU_C::LFS_GdMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LFS_GdMp: invalid use of LFS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit32u reg_32;
Bit16u fs;
@ -141,11 +111,6 @@ void BX_CPU_C::LFS_GdMp(bxInstruction_c *i)
#if BX_SUPPORT_X86_64
void BX_CPU_C::LFS_GqMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LFS_GqMp: invalid use of LFS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit64u reg_64;
Bit16u fs;
@ -160,11 +125,6 @@ void BX_CPU_C::LFS_GqMp(bxInstruction_c *i)
void BX_CPU_C::LGS_GwMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LGS_GwMp: invalid use of LGS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit16u reg_16, gs;
read_virtual_word(i->seg(), RMAddr(i), &reg_16);
@ -177,11 +137,6 @@ void BX_CPU_C::LGS_GwMp(bxInstruction_c *i)
void BX_CPU_C::LGS_GdMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LGS_GdMp: invalid use of LGS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit32u reg_32;
Bit16u gs;
@ -196,11 +151,6 @@ void BX_CPU_C::LGS_GdMp(bxInstruction_c *i)
#if BX_SUPPORT_X86_64
void BX_CPU_C::LGS_GqMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LGS_GqMp: invalid use of LGS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit64u reg_64;
Bit16u gs;
@ -215,11 +165,6 @@ void BX_CPU_C::LGS_GqMp(bxInstruction_c *i)
void BX_CPU_C::LSS_GwMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LSS_GwMp: invalid use of LSS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit16u reg_16, ss;
read_virtual_word(i->seg(), RMAddr(i), &reg_16);
@ -232,11 +177,6 @@ void BX_CPU_C::LSS_GwMp(bxInstruction_c *i)
void BX_CPU_C::LSS_GdMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LSS_GdMp: invalid use of LSS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit32u reg_32;
Bit16u ss;
@ -251,11 +191,6 @@ void BX_CPU_C::LSS_GdMp(bxInstruction_c *i)
#if BX_SUPPORT_X86_64
void BX_CPU_C::LSS_GqMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LSS_GqMp: invalid use of LSS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit64u reg_64;
Bit16u ss;

12
bochs/cpu/soft_int.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: soft_int.cc,v 1.32 2006-08-31 18:18:17 sshwarts Exp $
// $Id: soft_int.cc,v 1.33 2007-11-17 12:44:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -36,11 +36,6 @@
void BX_CPU_C::BOUND_GwMa(bxInstruction_c *i)
{
if (i->modC0()) {
BX_INFO(("BOUND_GwMa: op2 must be memory reference"));
UndefinedOpcode(i);
}
Bit16s bound_min, bound_max;
Bit16s op1_16 = BX_READ_16BIT_REG(i->nnn());
@ -55,11 +50,6 @@ void BX_CPU_C::BOUND_GwMa(bxInstruction_c *i)
void BX_CPU_C::BOUND_GdMa(bxInstruction_c *i)
{
if (i->modC0()) {
BX_INFO(("BOUND_GdMa: op2 must be memory reference"));
UndefinedOpcode(i);
}
Bit32s bound_min, bound_max;
Bit32s op1_32 = BX_READ_32BIT_REG(i->nnn());

73
bochs/cpu/sse_move.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse_move.cc,v 1.63 2007-10-20 17:03:33 sshwarts Exp $
// $Id: sse_move.cc,v 1.64 2007-11-17 12:44:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003 Stanislav Shwartsman
@ -63,11 +63,6 @@ void BX_CPU_C::print_state_SSE(void)
void BX_CPU_C::LDMXCSR(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 1
if (i->modC0()) {
BX_ERROR(("LDMXCSR: memory reference required"));
UndefinedOpcode(i);
}
BX_CPU_THIS_PTR prepareSSE();
Bit32u new_mxcsr;
@ -87,11 +82,6 @@ void BX_CPU_C::LDMXCSR(bxInstruction_c *i)
void BX_CPU_C::STMXCSR(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 1
if (i->modC0()) {
BX_ERROR(("STMXCSR: memory reference required"));
UndefinedOpcode(i);
}
BX_CPU_THIS_PTR prepareSSE();
Bit32u mxcsr = BX_MXCSR_REGISTER & MXCSR_MASK;
@ -109,11 +99,6 @@ void BX_CPU_C::FXSAVE(bxInstruction_c *i)
unsigned index;
BxPackedXmmRegister xmm;
if (i->modC0()) {
BX_ERROR(("FXSAVE: memory reference required"));
UndefinedOpcode(i);
}
BX_DEBUG(("FXSAVE: save FPU/MMX/SSE state"));
#if BX_SUPPORT_MMX
@ -238,11 +223,6 @@ void BX_CPU_C::FXRSTOR(bxInstruction_c *i)
BxPackedXmmRegister xmm;
int index;
if (i->modC0()) {
BX_ERROR(("FXRSTOR: memory reference required"));
UndefinedOpcode(i);
}
BX_DEBUG(("FXRSTOR: restore FPU/MMX/SSE state"));
#if BX_SUPPORT_MMX
@ -799,16 +779,9 @@ void BX_CPU_C::MOVHPS_MqVps(bxInstruction_c *i)
void BX_CPU_C::LDDQU_VdqMdq(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 3
/* source must be memory reference */
if (i->modC0()) {
BX_INFO(("LDDQU_VdqMdq: must be memory reference"));
UndefinedOpcode(i);
}
BX_CPU_THIS_PTR prepareSSE();
BxPackedXmmRegister op;
read_virtual_dqword(i->seg(), RMAddr(i), (Bit8u *) &op);
/* now write result back to destination */
@ -1124,46 +1097,38 @@ void BX_CPU_C::PMOVMSKB_GdUdq(bxInstruction_c *i)
void BX_CPU_C::MOVNTI_MdGd(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 2
if (i->modC0()) {
BX_INFO(("MOVNTI_MdGd: must be memory reference"));
UndefinedOpcode(i);
}
#if BX_SUPPORT_X86_64
if (i->os64L()) /* 64 bit operand size mode */
{
Bit64u val64 = BX_READ_64BIT_REG(i->nnn());
write_virtual_qword(i->seg(), RMAddr(i), &val64);
}
else
#endif
{
Bit32u val32 = BX_READ_32BIT_REG(i->nnn());
write_virtual_dword(i->seg(), RMAddr(i), &val32);
}
Bit32u val32 = BX_READ_32BIT_REG(i->nnn());
write_virtual_dword(i->seg(), RMAddr(i), &val32);
#else
BX_INFO(("MOVNTI_MdGd: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
#endif
}
#if BX_SUPPORT_X86_64
/* 0F C3 */
void BX_CPU_C::MOVNTI_MqGq(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 2
Bit64u val64 = BX_READ_64BIT_REG(i->nnn());
write_virtual_qword(i->seg(), RMAddr(i), &val64);
#else
BX_INFO(("MOVNTI_MqGq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);
#endif
}
#endif
/* MOVNTPS: 0F 2B */
/* MOVNTPD: 66 0F 2B */
/* MOVNTDQ: 66 0F E7 */
void BX_CPU_C::MOVNTPS_MpsVps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 1
if (i->modC0()) {
BX_INFO(("MOVNTPS_MpsVps: must be memory reference"));
UndefinedOpcode(i);
}
BX_CPU_THIS_PTR prepareSSE();
write_virtual_dqword_aligned(i->seg(), RMAddr(i), (Bit8u *)(&BX_READ_XMM_REG(i->nnn())));
#else
BX_INFO(("MOVNTPS_MpsVps: required SSE, use --enable-sse option"));
UndefinedOpcode(i);

19
bochs/cpu/stack16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: stack16.cc,v 1.22 2007-11-13 21:07:07 sshwarts Exp $
// $Id: stack16.cc,v 1.23 2007-11-17 12:44:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -213,18 +213,17 @@ void BX_CPU_C::PUSH_Iw(bxInstruction_c *i)
push_16(i->Iw());
}
void BX_CPU_C::PUSH_Ew(bxInstruction_c *i)
void BX_CPU_C::PUSH_EwM(bxInstruction_c *i)
{
Bit16u op1_16;
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op1_16);
push_16(op1_16);
}
void BX_CPU_C::PUSH_EwR(bxInstruction_c *i)
{
push_16(BX_READ_16BIT_REG(i->rm()));
}

19
bochs/cpu/stack32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: stack32.cc,v 1.35 2007-11-13 21:07:08 sshwarts Exp $
// $Id: stack32.cc,v 1.36 2007-11-17 12:44:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -231,22 +231,21 @@ void BX_CPU_C::PUSH_Id(bxInstruction_c *i)
push_32(i->Id());
}
void BX_CPU_C::PUSH_Ed(bxInstruction_c *i)
void BX_CPU_C::PUSH_EdM(bxInstruction_c *i)
{
Bit32u op1_32;
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
push_32(op1_32);
}
void BX_CPU_C::PUSH_EdR(bxInstruction_c *i)
{
push_32(BX_READ_32BIT_REG(i->rm()));
}
#if BX_CPU_LEVEL >= 2
void BX_CPU_C::ENTER_IwIb(bxInstruction_c *i)
{

19
bochs/cpu/stack64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: stack64.cc,v 1.23 2006-03-08 18:21:16 sshwarts Exp $
// $Id: stack64.cc,v 1.24 2007-11-17 12:44:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -96,22 +96,21 @@ void BX_CPU_C::PUSH64_Id(bxInstruction_c *i)
push_64(imm64);
}
void BX_CPU_C::PUSH_Eq(bxInstruction_c *i)
void BX_CPU_C::PUSH_EqM(bxInstruction_c *i)
{
Bit64u op1_64;
/* op1_64 is a register or memory reference */
if (i->modC0()) {
op1_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
}
/* pointer, segment address pair */
read_virtual_qword(i->seg(), RMAddr(i), &op1_64);
push_64(op1_64);
}
void BX_CPU_C::PUSH_EqR(bxInstruction_c *i)
{
push_64(BX_READ_64BIT_REG(i->rm()));
}
void BX_CPU_C::ENTER64_IwIb(bxInstruction_c *i)
{
Bit8u level = i->Ib2();