Support for x86-64 in x86 debugger (DR0-DR7)
This commit is contained in:
Stanislav Shwartsman
parent
9a32d0e98f
commit
f4c7b4074e
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.151 2006-05-12 17:04:18 sshwarts Exp $
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// $Id: cpu.cc,v 1.152 2006-05-13 12:49:45 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -670,10 +670,9 @@ unsigned BX_CPU_C::handleAsyncEvent(void)
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else {
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// only bother comparing if any breakpoints enabled
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if (BX_CPU_THIS_PTR dr7 & 0x000000ff) {
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Bit32u iaddr = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + BX_CPU_THIS_PTR prev_eip;
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Bit32u dr6_bits;
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if ( (dr6_bits = hwdebug_compare(iaddr, 1, BX_HWDebugInstruction,
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BX_HWDebugInstruction)) )
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bx_address iaddr = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS) + BX_CPU_THIS_PTR prev_eip;
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Bit32u dr6_bits = hwdebug_compare(iaddr, 1, BX_HWDebugInstruction, BX_HWDebugInstruction);
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if (dr6_bits)
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{
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// Add to the list of debug events thus far.
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BX_CPU_THIS_PTR async_event = 1;
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@ -681,7 +680,7 @@ unsigned BX_CPU_C::handleAsyncEvent(void)
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// If debug events are not inhibited on this boundary,
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// fire off a debug fault. Otherwise handle it on the next
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// boundary. (becomes a trap)
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if ( !(BX_CPU_THIS_PTR inhibit_mask & BX_INHIBIT_DEBUG) ) {
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if (! (BX_CPU_THIS_PTR inhibit_mask & BX_INHIBIT_DEBUG)) {
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// Commit debug events to DR6
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BX_CPU_THIS_PTR dr6 = BX_CPU_THIS_PTR debug_trap;
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exception(BX_DB_EXCEPTION, 0, 0); // no error, not interrupt
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.290 2006-05-12 17:04:18 sshwarts Exp $
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// $Id: cpu.h,v 1.291 2006-05-13 12:49:45 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1086,14 +1086,14 @@ public: // for now...
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bx_segment_reg_t ldtr; /* local descriptor table register */
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bx_segment_reg_t tr; /* task register */
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/* debug registers 0-7 (unimplemented) */
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/* debug registers DR0-DR7 */
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#if BX_CPU_LEVEL >= 3
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Bit32u dr0;
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Bit32u dr1;
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Bit32u dr2;
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Bit32u dr3;
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Bit32u dr6;
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Bit32u dr7;
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bx_address dr0;
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bx_address dr1;
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bx_address dr2;
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bx_address dr3;
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Bit32u dr6;
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Bit32u dr7;
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#endif
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/* TR3 - TR7 (Test Register 3-7), unimplemented */
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@ -1103,12 +1103,10 @@ public: // for now...
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bx_cr0_t cr0;
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Bit32u cr1;
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bx_address cr2;
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bx_phy_address cr3;
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bx_phy_address cr3_masked;
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#endif
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bx_phy_address cr3, cr3_masked;
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#if BX_CPU_LEVEL >= 4
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bx_cr4_t cr4;
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bx_cr4_t cr4;
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#endif
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#endif
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/* SMM base register */
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@ -2872,7 +2870,7 @@ public: // for now...
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#if BX_X86_DEBUGGER
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// x86 hardware debug support
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BX_SMF Bit32u hwdebug_compare(Bit32u laddr, unsigned size,
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BX_SMF Bit32u hwdebug_compare(bx_address laddr, unsigned size,
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unsigned opa, unsigned opb);
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#endif
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.148 2006-05-13 12:29:12 sshwarts Exp $
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// $Id: proc_ctrl.cc,v 1.149 2006-05-13 12:49:45 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -2247,65 +2247,61 @@ void BX_CPU_C::SWAPGS(bxInstruction_c *i)
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#endif
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#if BX_X86_DEBUGGER
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Bit32u BX_CPU_C::hwdebug_compare(Bit32u laddr_0, unsigned size,
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Bit32u BX_CPU_C::hwdebug_compare(bx_address laddr_0, unsigned size,
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unsigned opa, unsigned opb)
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{
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// Support x86 hardware debug facilities (DR0..DR7)
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Bit32u dr7 = BX_CPU_THIS_PTR dr7;
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bx_bool ibpoint_found = 0;
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Bit32u laddr_n = laddr_0 + (size - 1);
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Bit32u dr0, dr1, dr2, dr3;
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Bit32u dr0_n, dr1_n, dr2_n, dr3_n;
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Bit32u len0, len1, len2, len3;
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static unsigned alignment_mask[4] =
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// 00b=1 01b=2 10b=undef 11b=4
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{ 0xffffffff, 0xfffffffe, 0xffffffff, 0xfffffffc };
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Bit32u dr0_op, dr1_op, dr2_op, dr3_op;
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bx_address laddr_n = laddr_0 + (size - 1);
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static bx_address alignment_mask[4] =
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// 00b=1 01b=2 10b=undef 11b=4
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{ 0x0, 0x1, 0x0, 0x3 };
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len0 = (dr7>>18) & 3;
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len1 = (dr7>>22) & 3;
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len2 = (dr7>>26) & 3;
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len3 = (dr7>>30) & 3;
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Bit32u len0 = (dr7>>18) & 3;
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Bit32u len1 = (dr7>>22) & 3;
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Bit32u len2 = (dr7>>26) & 3;
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Bit32u len3 = (dr7>>30) & 3;
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dr0 = BX_CPU_THIS_PTR dr0 & alignment_mask[len0];
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dr1 = BX_CPU_THIS_PTR dr1 & alignment_mask[len1];
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dr2 = BX_CPU_THIS_PTR dr2 & alignment_mask[len2];
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dr3 = BX_CPU_THIS_PTR dr3 & alignment_mask[len3];
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bx_address dr0 = (BX_CPU_THIS_PTR dr0) & ~(alignment_mask[len0]);
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bx_address dr1 = (BX_CPU_THIS_PTR dr1) & ~(alignment_mask[len1]);
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bx_address dr2 = (BX_CPU_THIS_PTR dr2) & ~(alignment_mask[len2]);
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bx_address dr3 = (BX_CPU_THIS_PTR dr3) & ~(alignment_mask[len3]);
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dr0_n = dr0 + len0;
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dr1_n = dr1 + len1;
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dr2_n = dr2 + len2;
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dr3_n = dr3 + len3;
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bx_address dr0_n = dr0 + len0;
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bx_address dr1_n = dr1 + len1;
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bx_address dr2_n = dr2 + len2;
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bx_address dr3_n = dr3 + len3;
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dr0_op = (dr7>>16) & 3;
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dr1_op = (dr7>>20) & 3;
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dr2_op = (dr7>>24) & 3;
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dr3_op = (dr7>>28) & 3;
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Bit32u dr0_op = (dr7>>16) & 3;
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Bit32u dr1_op = (dr7>>20) & 3;
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Bit32u dr2_op = (dr7>>24) & 3;
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Bit32u dr3_op = (dr7>>28) & 3;
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// See if this instruction address matches any breakpoints
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if ( (dr7 & 0x00000003) ) {
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if ( (dr0_op==opa || dr0_op==opb) &&
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if ((dr7 & 0x00000003)) {
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if ((dr0_op==opa || dr0_op==opb) &&
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(laddr_0 <= dr0_n) &&
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(laddr_n >= dr0) )
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(laddr_n >= dr0))
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ibpoint_found = 1;
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}
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if ( (dr7 & 0x0000000c) ) {
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if ( (dr1_op==opa || dr1_op==opb) &&
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if ((dr7 & 0x0000000c)) {
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if ((dr1_op==opa || dr1_op==opb) &&
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(laddr_0 <= dr1_n) &&
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(laddr_n >= dr1) )
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(laddr_n >= dr1))
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ibpoint_found = 1;
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}
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if ( (dr7 & 0x00000030) ) {
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if ( (dr2_op==opa || dr2_op==opb) &&
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if ((dr7 & 0x00000030)) {
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if ((dr2_op==opa || dr2_op==opb) &&
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(laddr_0 <= dr2_n) &&
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(laddr_n >= dr2) )
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(laddr_n >= dr2))
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ibpoint_found = 1;
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}
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if ( (dr7 & 0x000000c0) ) {
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if ( (dr3_op==opa || dr3_op==opb) &&
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if ((dr7 & 0x000000c0)) {
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if ((dr3_op==opa || dr3_op==opb) &&
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(laddr_0 <= dr3_n) &&
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(laddr_n >= dr3) )
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(laddr_n >= dr3))
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ibpoint_found = 1;
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}
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@ -2318,25 +2314,26 @@ Bit32u BX_CPU_C::hwdebug_compare(Bit32u laddr_0, unsigned size,
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if (ibpoint_found) {
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// dr6_mask is the return value. These bits represent the bits to
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// be OR'd into DR6 as a result of the debug event.
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Bit32u dr6_mask=0;
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if ( (dr0_op==opa || dr0_op==opb) &&
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Bit32u dr6_mask=0;
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if ((dr0_op==opa || dr0_op==opb) &&
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(laddr_0 <= dr0_n) &&
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(laddr_n >= dr0) )
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(laddr_n >= dr0))
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dr6_mask |= 0x01;
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if ( (dr1_op==opa || dr1_op==opb) &&
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if ((dr1_op==opa || dr1_op==opb) &&
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(laddr_0 <= dr1_n) &&
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(laddr_n >= dr1) )
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(laddr_n >= dr1))
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dr6_mask |= 0x02;
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if ( (dr2_op==opa || dr2_op==opb) &&
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if ((dr2_op==opa || dr2_op==opb) &&
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(laddr_0 <= dr2_n) &&
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(laddr_n >= dr2) )
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(laddr_n >= dr2))
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dr6_mask |= 0x04;
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if ( (dr3_op==opa || dr3_op==opb) &&
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if ((dr3_op==opa || dr3_op==opb) &&
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(laddr_0 <= dr3_n) &&
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(laddr_n >= dr3) )
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(laddr_n >= dr3))
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dr6_mask |= 0x08;
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return(dr6_mask);
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}
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return(0);
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}
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#endif
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