Optimize debug registers handling
This commit is contained in:
Stanislav Shwartsman
parent
fc799ab623
commit
9a32d0e98f
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.147 2006-04-23 16:11:16 sshwarts Exp $
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// $Id: proc_ctrl.cc,v 1.148 2006-05-13 12:29:12 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -237,16 +237,17 @@ void BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
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break;
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case 4: // DR4
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case 6: // DR6
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// DR4 aliased to DR6 by default. With Debug Extensions on,
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// access to DR4 causes #UD
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#if BX_CPU_LEVEL >= 4
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if ((i->nnn() == 4) && (BX_CPU_THIS_PTR cr4.get_DE())) {
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// Debug extensions on
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_DdRd: access to DR4 causes #UD"));
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UndefinedOpcode(i);
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}
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#endif
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// Fall through to DR6 case
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case 6: // DR6
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#if BX_CPU_LEVEL <= 4
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// On 386/486 bit12 is settable
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BX_CPU_THIS_PTR dr6 = (BX_CPU_THIS_PTR dr6 & 0xffff0ff0) |
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@ -259,22 +260,23 @@ void BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
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break;
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case 5: // DR5
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// DR5 aliased to DR7 by default. With Debug Extensions on,
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// access to DR5 causes #UD
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#if BX_CPU_LEVEL >= 4
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_DdRd: access to DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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#endif
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// Fall through to DR7 case
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case 7: // DR7
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// Note: 486+ ignore GE and LE flags. On the 386, exact
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// data breakpoint matching does not occur unless it is enabled
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// by setting the LE and/or GE flags.
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// DR5 aliased to DR7 by default. With Debug Extensions on,
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// access to DR5 causes #UD
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#if BX_CPU_LEVEL >= 4
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if ((i->nnn() == 5) && (BX_CPU_THIS_PTR cr4.get_DE())) {
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// Debug extensions (CR4.DE) on
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BX_INFO(("MOV_DdRd: access to DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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#endif
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// Some sanity checks...
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if ( val_32 & 0x00002000 ) {
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if (val_32 & 0x00002000) {
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BX_INFO(("MOV_DdRd: GD bit not supported yet"));
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// Note: processor clears GD upon entering debug exception
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// handler, to allow access to the debug registers
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@ -312,13 +314,13 @@ void BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
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// if we have breakpoints enabled then we must check
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// breakpoints condition in cpu loop
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if(BX_CPU_THIS_PTR dr7 & 0xff)
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BX_CPU_THIS_PTR async_event = 1;
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BX_CPU_THIS_PTR async_event = 1;
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break;
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default:
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BX_PANIC(("MOV_DdRd: control register index out of range"));
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break;
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}
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}
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}
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void BX_CPU_C::MOV_RdDd(bxInstruction_c *i)
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@ -360,37 +362,39 @@ void BX_CPU_C::MOV_RdDd(bxInstruction_c *i)
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break;
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case 4: // DR4
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case 6: // DR6
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// DR4 aliased to DR6 by default. With Debug Extensions on,
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// access to DR4 causes #UD
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#if BX_CPU_LEVEL >= 4
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if ( (i->nnn() == 4) && (BX_CPU_THIS_PTR cr4.get_DE()) ) {
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// Debug extensions on
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_RdDd: access to DR4 causes #UD"));
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UndefinedOpcode(i);
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}
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#endif
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// Fall through to DR6 case
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case 6: // DR6
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val_32 = BX_CPU_THIS_PTR dr6;
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break;
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case 5: // DR5
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case 7: // DR7
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// DR5 aliased to DR7 by default. With Debug Extensions on,
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// access to DR5 causes #UD
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#if BX_CPU_LEVEL >= 4
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if ( (i->nnn() == 5) && (BX_CPU_THIS_PTR cr4.get_DE()) ) {
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// Debug extensions on
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_RdDd: access to DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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#endif
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// Fall through to DR7 case
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case 7: // DR7
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val_32 = BX_CPU_THIS_PTR dr7;
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break;
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default:
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BX_PANIC(("MOV_RdDd: control register index out of range"));
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val_32 = 0;
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}
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}
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BX_WRITE_32BIT_REGZ(i->rm(), val_32);
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}
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@ -444,35 +448,36 @@ void BX_CPU_C::MOV_DqRq(bxInstruction_c *i)
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break;
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case 4: // DR4
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case 6: // DR6
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// DR4 aliased to DR6 by default. With Debug Extensions on,
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// access to DR4 causes #UD
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if ( (i->nnn() == 4) && (BX_CPU_THIS_PTR cr4.get_DE()) ) {
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// Debug extensions on
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_DqRq: access to DR4 causes #UD"));
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UndefinedOpcode(i);
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}
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// Fall through to DR6 case
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case 6: // DR6
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// On Pentium+, bit12 is always zero
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BX_CPU_THIS_PTR dr6 = (BX_CPU_THIS_PTR dr6 & 0xffff0ff0) |
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(val_64 & 0x0000e00f);
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break;
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case 5: // DR5
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// DR5 aliased to DR7 by default. With Debug Extensions on,
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// access to DR5 causes #UD
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_DqRq: access to DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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// Fall through to DR7 case
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case 7: // DR7
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// Note: 486+ ignore GE and LE flags. On the 386, exact
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// data breakpoint matching does not occur unless it is enabled
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// by setting the LE and/or GE flags.
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// DR5 aliased to DR7 by default. With Debug Extensions on,
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// access to DR5 causes #UD
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if ( (i->nnn() == 5) && (BX_CPU_THIS_PTR cr4.get_DE()) ) {
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// Debug extensions (CR4.DE) on
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BX_INFO(("MOV_DqRq: access to DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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// Some sanity checks...
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if ( val_64 & 0x00002000 ) {
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if (val_64 & 0x00002000) {
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BX_PANIC(("MOV_DqRq: GD bit not supported yet"));
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// Note: processor clears GD upon entering debug exception
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// handler, to allow access to the debug registers
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@ -513,7 +518,7 @@ void BX_CPU_C::MOV_DqRq(bxInstruction_c *i)
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default:
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BX_PANIC(("MOV_DqRq: control register index out of range"));
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break;
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}
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}
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}
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void BX_CPU_C::MOV_RqDq(bxInstruction_c *i)
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@ -555,26 +560,28 @@ void BX_CPU_C::MOV_RqDq(bxInstruction_c *i)
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break;
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case 4: // DR4
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case 6: // DR6
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// DR4 aliased to DR6 by default. With Debug Extensions on,
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// access to DR4 causes #UD
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if ( (i->nnn() == 4) && (BX_CPU_THIS_PTR cr4.get_DE()) ) {
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// Debug extensions on
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_RqDq: access to DR4 causes #UD"));
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UndefinedOpcode(i);
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}
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// Fall through to DR6 case
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case 6: // DR6
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val_64 = BX_CPU_THIS_PTR dr6;
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break;
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case 5: // DR5
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case 7: // DR7
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// DR5 aliased to DR7 by default. With Debug Extensions on,
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// access to DR5 causes #UD
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if ( (i->nnn() == 5) && (BX_CPU_THIS_PTR cr4.get_DE()) ) {
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// Debug extensions on
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_RqDq: access to DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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// Fall through to DR7 case
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case 7: // DR7
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val_64 = BX_CPU_THIS_PTR dr7;
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break;
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