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Implemented MOVBE Intel Atom(R) instruction

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This commit is contained in:
Stanislav Shwartsman 2008-08-11 18:53:24 +00:00
parent 87103c2437
commit a8adb36dc2
16 changed files with 1914 additions and 5639 deletions
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7
bochs/config.h.in
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@ -719,6 +719,7 @@ typedef
#define BX_SUPPORT_MONITOR_MWAIT 0
#define BX_SUPPORT_XSAVE 0
#define BX_SUPPORT_AES 0
#define BX_SUPPORT_MOVBE 0
#define BX_SUPPORT_MTRR 0
#define BX_SUPPORT_LARGE_PAGES 0
@ -794,6 +795,12 @@ typedef
#error "SYSENTER/SYSEXIT only supported with CPU_LEVEL >= 6 !"
#endif
#if (BX_SUPPORT_SSE < 3) || (BX_SUPPORT_SSE == 3 && BX_SUPPORT_SSE_EXTENSION == 0)
#if BX_SUPPORT_MOVBE
#error "MOVBE only supported with SSE3E !"
#endif
#endif
#if (BX_CPU_LEVEL<6 && BX_SUPPORT_PAE)
#error "Physical Address Extensions (PAE) only supported with CPU_LEVEL >= 6 !"
#endif

7108
bochs/configure vendored
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File diff suppressed because it is too large Load Diff

19
bochs/configure.in
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@ -2,7 +2,7 @@ dnl // Process this file with autoconf to produce a configure script.
AC_PREREQ(2.50)
AC_INIT(bochs.h)
AC_REVISION([[$Id: configure.in,v 1.372 2008-07-12 15:20:18 vruppert Exp $]])
AC_REVISION([[$Id: configure.in,v 1.373 2008-08-11 18:53:21 sshwarts Exp $]])
AC_CONFIG_HEADER(config.h)
AC_CONFIG_HEADER(ltdlconf.h)
@ -1830,6 +1830,23 @@ AC_ARG_ENABLE(popcnt,
]
)
AC_MSG_CHECKING(for MOVBE instruction support)
AC_ARG_ENABLE(movbe,
[ --enable-movbe support for MOVBE Intel Atom(R) instruction],
[if test "$enableval" = yes; then
AC_MSG_RESULT(yes)
AC_DEFINE(BX_SUPPORT_MOVBE, 1)
elif test "$enableval" = no; then
AC_MSG_RESULT(no)
AC_DEFINE(BX_SUPPORT_MOVBE, 0)
fi
],
[
AC_MSG_RESULT(no)
AC_DEFINE(BX_SUPPORT_MOVBE, 0)
]
)
AC_MSG_CHECKING(for MONITOR/MWAIT instructions support (experimental))
AC_ARG_ENABLE(monitor_mwait,
[ --enable-monitor-mwait support for MONITOR/MWAIT instructions (experimental)],

9
bochs/cpu/Makefile.in
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@ -110,6 +110,7 @@ OBJS = \
ctrl_xfer_pro.o \
segment_ctrl_pro.o \
io.o \
crc32.o \
bit.o \
bit16.o \
bit32.o \
@ -251,6 +252,14 @@ bcd.o: bcd.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
crregs.h descriptor.h instr.h lazy_flags.h icache.h apic.h \
../cpu/i387.h ../fpu/softfloat.h ../config.h ../fpu/tag_w.h \
../fpu/status_w.h ../fpu/control_w.h ../cpu/xmm.h stack.h
crc32.o: crc32.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
../config.h ../osdep.h ../bxversion.h ../gui/siminterface.h \
../memory/memory.h ../pc_system.h ../plugin.h ../extplugin.h \
../gui/gui.h ../gui/textconfig.h ../config.h ../gui/keymap.h \
../instrument/stubs/instrument.h cpu.h ../disasm/disasm.h ../config.h \
crregs.h descriptor.h instr.h lazy_flags.h icache.h apic.h \
../cpu/i387.h ../fpu/softfloat.h ../config.h ../fpu/tag_w.h \
../fpu/status_w.h ../fpu/control_w.h ../cpu/xmm.h stack.h
bit.o: bit.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
../config.h ../osdep.h ../bxversion.h ../gui/siminterface.h \
../memory/memory.h ../pc_system.h ../plugin.h ../extplugin.h \

284
bochs/cpu/bit.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bit.cc,v 1.58 2008-08-08 09:22:46 sshwarts Exp $
// $Id: bit.cc,v 1.59 2008-08-11 18:53:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -252,13 +252,12 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_ERX(bxInstruction_c *i)
}
val32 = BX_READ_32BIT_REG(i->opcodeReg());
b0 = val32 & 0xff; val32 >>= 8;
b1 = val32 & 0xff; val32 >>= 8;
b2 = val32 & 0xff; val32 >>= 8;
b3 = val32;
val32 = (b0<<24) | (b1<<16) | (b2<<8) | b3; // zero extended
b0 = val32 & 0xff; val32 >>= 8;
b1 = val32 & 0xff; val32 >>= 8;
b2 = val32 & 0xff; val32 >>= 8;
b3 = val32;
val32 = (b0<<24) | (b1<<16) | (b2<<8) | b3;
// in 64-bit mode, hi-order 32 bits are not modified
BX_WRITE_32BIT_REGZ(i->opcodeReg(), val32);
#else
BX_INFO(("BSWAP_ERX: required CPU >= 4, use --enable-cpu-level=4 option"));
@ -272,14 +271,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_RRX(bxInstruction_c *i)
Bit64u val64, b0, b1, b2, b3, b4, b5, b6, b7;
val64 = BX_READ_64BIT_REG(i->opcodeReg());
b0 = val64 & 0xff; val64 >>= 8;
b1 = val64 & 0xff; val64 >>= 8;
b2 = val64 & 0xff; val64 >>= 8;
b3 = val64 & 0xff; val64 >>= 8;
b4 = val64 & 0xff; val64 >>= 8;
b5 = val64 & 0xff; val64 >>= 8;
b6 = val64 & 0xff; val64 >>= 8;
b7 = val64;
b0 = val64 & 0xff; val64 >>= 8;
b1 = val64 & 0xff; val64 >>= 8;
b2 = val64 & 0xff; val64 >>= 8;
b3 = val64 & 0xff; val64 >>= 8;
b4 = val64 & 0xff; val64 >>= 8;
b5 = val64 & 0xff; val64 >>= 8;
b6 = val64 & 0xff; val64 >>= 8;
b7 = val64;
val64 = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b4<<16) | (b4<<8) | b7;
BX_WRITE_64BIT_REG(i->opcodeReg(), val64);
@ -289,156 +288,165 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_RRX(bxInstruction_c *i)
// 3-byte opcodes
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
#define CRC32_POLYNOMIAL BX_CONST64(0x11edc6f41)
#if (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
// primitives for CRC32 usage
BX_CPP_INLINE Bit8u BitReflect8(Bit8u val8)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_GwEw(bxInstruction_c *i)
{
return ((val8 & 0x80) >> 7) |
((val8 & 0x40) >> 5) |
((val8 & 0x20) >> 3) |
((val8 & 0x10) >> 1) |
((val8 & 0x08) << 1) |
((val8 & 0x04) << 3) |
((val8 & 0x02) << 5) |
((val8 & 0x01) << 7);
}
BX_CPP_INLINE Bit16u BitReflect16(Bit16u val16)
{
return ((Bit16u)(BitReflect8(val16 & 0xff)) << 8) | BitReflect8(val16 >> 8);
}
BX_CPP_INLINE Bit32u BitReflect32(Bit32u val32)
{
return ((Bit32u)(BitReflect16(val32 & 0xffff)) << 16) | BitReflect16(val32 >> 16);
}
static Bit32u mod2_64bit(Bit64u divisor, Bit64u dividend)
{
Bit64u remainder = dividend >> 32;
for (int bitpos=31; bitpos>=0; bitpos--) {
// copy one more bit from the dividend
remainder = (remainder << 1) | ((dividend >> bitpos) & 1);
// if MSB is set, then XOR divisor and get new remainder
if (((remainder >> 32) & 1) == 1) {
remainder ^= divisor;
}
}
return remainder;
}
#endif // (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEb(bxInstruction_c *i)
{
#if (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
Bit8u op1;
#if BX_SUPPORT_MOVBE
Bit16u val16, b0, b1;
if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
val16 = BX_READ_16BIT_REG(i->rm());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1 = read_virtual_byte(i->seg(), eaddr);
val16 = read_virtual_word(i->seg(), eaddr);
}
b0 = val16 & 0xff; val16 >>= 8;
b1 = val16;
val16 = (b1<<8) | b0;
Bit32u op2 = BX_READ_32BIT_REG(i->nnn());
op2 = BitReflect32(op2);
Bit64u tmp1 = ((Bit64u) BitReflect8 (op1)) << 32;
Bit64u tmp2 = ((Bit64u) op2) << 8;
Bit64u tmp3 = tmp1 ^ tmp2;
op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), BitReflect32(op2));
BX_WRITE_16BIT_REG(i->nnn(), val16);
#else
BX_INFO(("CRC32_GdEb: required SSE4_2 support, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("MOVBE_GwEw: required MOVBE support, use --enable-movbe option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEv(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_EwGw(bxInstruction_c *i)
{
#if (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
#if BX_SUPPORT_MOVBE
Bit16u val16 = BX_READ_16BIT_REG(i->nnn()), b0, b1;
Bit32u op2 = BX_READ_32BIT_REG(i->nnn());
op2 = BitReflect32(op2);
b0 = val16 & 0xff; val16 >>= 8;
b1 = val16;
val16 = (b1<<8) | b0;
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), val16);
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_word(i->seg(), eaddr, val16);
}
#else
BX_INFO(("MOVBE_EwGw: required MOVBE support, use --enable-movbe option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_GdEd(bxInstruction_c *i)
{
#if BX_SUPPORT_MOVBE
Bit32u val32, b0, b1, b2, b3;
if (i->modC0()) {
val32 = BX_READ_32BIT_REG(i->rm());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
val32 = read_virtual_dword(i->seg(), eaddr);
}
b0 = val32 & 0xff; val32 >>= 8;
b1 = val32 & 0xff; val32 >>= 8;
b2 = val32 & 0xff; val32 >>= 8;
b3 = val32;
val32 = (b0<<24) | (b1<<16) | (b2<<8) | b3;
BX_WRITE_32BIT_REGZ(i->nnn(), val32);
#else
BX_INFO(("MOVBE_GdEd: required MOVBE support, use --enable-movbe option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_EdGd(bxInstruction_c *i)
{
#if BX_SUPPORT_MOVBE
Bit32u val32 = BX_READ_32BIT_REG(i->nnn()), b0, b1, b2, b3;
b0 = val32 & 0xff; val32 >>= 8;
b1 = val32 & 0xff; val32 >>= 8;
b2 = val32 & 0xff; val32 >>= 8;
b3 = val32;
val32 = (b0<<24) | (b1<<16) | (b2<<8) | b3;
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), val32);
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dword(i->seg(), eaddr, val32);
}
#else
BX_INFO(("MOVBE_EdGd: required MOVBE support, use --enable-movbe option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
#if BX_SUPPORT_X86_64
if (i->os64L()) /* 64 bit operand size */
{
Bit64u op1;
if (i->modC0()) {
op1 = BX_READ_64BIT_REG(i->rm());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1 = read_virtual_qword_64(i->seg(), eaddr);
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_GqEq(bxInstruction_c *i)
{
#if BX_SUPPORT_MOVBE
Bit64u val64, b0, b1, b2, b3, b4, b5, b6, b7;
Bit64u tmp1 = ((Bit64u) BitReflect32(op1 & 0xffffffff)) << 32;
Bit64u tmp2 = ((Bit64u) op2) << 32;
Bit64u tmp3 = tmp1 ^ tmp2;
op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
tmp1 = ((Bit64u) BitReflect32(op1 >> 32)) << 32;
tmp2 = ((Bit64u) op2) << 32;
tmp3 = tmp1 ^ tmp2;
op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
if (i->modC0()) {
val64 = BX_READ_64BIT_REG(i->rm());
}
else
#endif
{
if (i->os32L()) /* 32 bit operand size */
{
Bit32u op1;
if (i->modC0()) {
op1 = BX_READ_32BIT_REG(i->rm());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1 = read_virtual_dword(i->seg(), eaddr);
}
Bit64u tmp1 = ((Bit64u) BitReflect32(op1)) << 32;
Bit64u tmp2 = ((Bit64u) op2) << 32;
Bit64u tmp3 = tmp1 ^ tmp2;
op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
}
else { /* 16 bit operand size */
Bit16u op1;
if (i->modC0()) {
op1 = BX_READ_16BIT_REG(i->rm());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1 = read_virtual_word(i->seg(), eaddr);
}
Bit64u tmp1 = ((Bit64u) BitReflect16(op1)) << 32;
Bit64u tmp2 = ((Bit64u) op2) << 16;
Bit64u tmp3 = tmp1 ^ tmp2;
op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
val64 = read_virtual_qword(i->seg(), eaddr);
}
b0 = val64 & 0xff; val64 >>= 8;
b1 = val64 & 0xff; val64 >>= 8;
b2 = val64 & 0xff; val64 >>= 8;
b3 = val64 & 0xff; val64 >>= 8;
b4 = val64 & 0xff; val64 >>= 8;
b5 = val64 & 0xff; val64 >>= 8;
b6 = val64 & 0xff; val64 >>= 8;
b7 = val64;
val64 = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b4<<16) | (b4<<8) | b7;
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), BitReflect32(op2));
BX_WRITE_64BIT_REG(i->nnn(), val64);
#else
BX_INFO(("CRC32_GdEv: required SSE4_2 support, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("MOVBE_GqEq: required MOVBE support, use --enable-movbe option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_EqGq(bxInstruction_c *i)
{
#if BX_SUPPORT_MOVBE
Bit64u val64 = BX_READ_64BIT_REG(i->nnn());
Bit64u b0, b1, b2, b3, b4, b5, b6, b7;
b0 = val64 & 0xff; val64 >>= 8;
b1 = val64 & 0xff; val64 >>= 8;
b2 = val64 & 0xff; val64 >>= 8;
b3 = val64 & 0xff; val64 >>= 8;
b4 = val64 & 0xff; val64 >>= 8;
b5 = val64 & 0xff; val64 >>= 8;
b6 = val64 & 0xff; val64 >>= 8;
b7 = val64;
val64 = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b4<<16) | (b4<<8) | b7;
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), val64);
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_qword(i->seg(), eaddr, val64);
}
#else
BX_INFO(("MOVBE_EqGq: required MOVBE support, use --enable-movbe option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
#endif // (BX_SUPPORT_X86_64)
#endif // (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
#endif // (BX_CPU_LEVEL >= 3)

4
bochs/cpu/bit16.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bit16.cc,v 1.14 2008-08-10 21:16:12 sshwarts Exp $
// $Id: bit16.cc,v 1.15 2008-08-11 18:53:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -339,7 +339,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwIbR(bxInstruction_c *i)
/* 0F B8 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GwEwR(bxInstruction_c *i)
{
#if BX_SUPPORT_POPCNT || (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
#if BX_SUPPORT_POPCNT || (BX_SUPPORT_SSE > 4) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = 0;

4
bochs/cpu/bit32.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bit32.cc,v 1.13 2008-08-10 21:16:12 sshwarts Exp $
// $Id: bit32.cc,v 1.14 2008-08-11 18:53:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -344,7 +344,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EdIbR(bxInstruction_c *i)
/* 0F B8 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GdEdR(bxInstruction_c *i)
{
#if BX_SUPPORT_POPCNT || (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
#if BX_SUPPORT_POPCNT || (BX_SUPPORT_SSE > 4) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = 0;

4
bochs/cpu/bit64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bit64.cc,v 1.18 2008-08-10 21:16:12 sshwarts Exp $
// $Id: bit64.cc,v 1.19 2008-08-11 18:53:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -324,7 +324,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EqIbR(bxInstruction_c *i)
/* 0F B8 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GqEqR(bxInstruction_c *i)
{
#if BX_SUPPORT_POPCNT || (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
#if BX_SUPPORT_POPCNT || (BX_SUPPORT_SSE > 4) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = 0;

20
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.504 2008-08-10 21:16:12 sshwarts Exp $
// $Id: cpu.h,v 1.505 2008-08-11 18:53:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -2197,7 +2197,11 @@ public: // for now...
/* SSE4.2 */
BX_SMF void CRC32_GdEb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CRC32_GdEv(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CRC32_GdEw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CRC32_GdEd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#if BX_SUPPORT_X86_64
BX_SMF void CRC32_GdEq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
BX_SMF void PCMPGTQ_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void PCMPESTRM_VdqWdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void PCMPESTRI_VdqWdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2206,6 +2210,16 @@ public: // for now...
/* SSE4.2 */
#endif
/* MOVBE Intel Atom(R) instruction */
BX_SMF void MOVBE_GwEw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void MOVBE_GdEd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void MOVBE_EwGw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void MOVBE_EdGd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#if BX_SUPPORT_X86_64
BX_SMF void MOVBE_GqEq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void MOVBE_EqGq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
/* XSAVE/XRSTOR extensions */
BX_SMF void XSAVE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void XRSTOR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -3681,7 +3695,7 @@ IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
#define BxFPEscape 0x0030 // Group encoding: 011
#define BxRMGroup 0x0040 // Group encoding: 100
#define Bx3ByteOp 0x0050 // Group encoding: 101
// Group encoding: 110
#define BxOSizeGrp 0x0060 // Group encoding: 110
// Group encoding: 111
#define BxLockable 0x0080 // bit 7

14
bochs/cpu/cpuid.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpuid.cc,v 1.70 2008-07-13 15:35:09 sshwarts Exp $
// $Id: cpuid.cc,v 1.71 2008-08-11 18:53:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007 Stanislav Shwartsman
@ -141,7 +141,7 @@ Bit32u BX_CPU_C::get_extended_cpuid_features(void)
// [19:19] SSE4.1 Instructions
// [20:20] SSE4.2 Instructions
// [21:22] X2APIC
// [22:22] Reserved
// [22:22] MOVBE instruction
// [23:23] POPCNT instruction
// [24:24] reserved
// [25:25] AES Instructions
@ -170,11 +170,15 @@ Bit32u BX_CPU_C::get_extended_cpuid_features(void)
features |= (1<<19); // support SSE4.1
#endif
#if (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
features |= (1<<20); // support SSE4.2 (SSE4E)
#if (BX_SUPPORT_SSE > 4) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
features |= (1<<20); // support SSE4.2
#endif
#if BX_SUPPORT_POPCNT || (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
#if BX_SUPPORT_MOVBE
features |= (1<<22); // support MOVBE instruction
#endif
#if BX_SUPPORT_POPCNT || (BX_SUPPORT_SSE > 4) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
features |= (1<<23); // support POPCNT instruction
#endif

5
bochs/cpu/fetchdecode.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.cc,v 1.200 2008-08-10 21:16:12 sshwarts Exp $
// $Id: fetchdecode.cc,v 1.201 2008-08-11 18:53:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -2740,6 +2740,9 @@ modrm_done:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[b3]);
break;
#endif
case BxOSizeGrp:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[os_32]);
break;
case BxPrefixSSE:
/* For SSE opcodes look into another 4 entries table
with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3) */

33
bochs/cpu/fetchdecode.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.h,v 1.72 2008-08-10 21:16:12 sshwarts Exp $
// $Id: fetchdecode.h,v 1.73 2008-08-11 18:53:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005 Stanislav Shwartsman
@ -2236,7 +2236,6 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f38de[4] = {
/* F3 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f38df[4] = {
/* -- */ { 0, BX_IA_ERROR },
/* 66 */ { 0, BX_IA_AESDECLAST_VdqWdq }, // AES
@ -2244,17 +2243,41 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f38df[4] = {
/* F3 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f38f0_movbe[BX_SUPPORT_X86_64 + 2] = {
/* 16 */ { 0, BX_IA_MOVBE_GwEw },
/* 32 */ { 0, BX_IA_MOVBE_GdEd },
#if BX_SUPPORT_X86_64
/* 64 */ { 0, BX_IA_MOVBE_GqEq }
#endif
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f38f1_movbe[BX_SUPPORT_X86_64 + 2] = {
/* 16 */ { 0, BX_IA_MOVBE_EwGw },
/* 32 */ { 0, BX_IA_MOVBE_EdGd },
#if BX_SUPPORT_X86_64
/* 64 */ { 0, BX_IA_MOVBE_EqGq }
#endif
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f38f0[4] = {
/* -- */ { 0, BX_IA_ERROR },
/* -- */ { BxOSizeGrp, BX_IA_ERROR, BxOpcodeGroupSSE_0f38f0_movbe },
/* 66 */ { 0, BX_IA_ERROR },
/* F2 */ { 0, BX_IA_CRC32_GdEb },
/* F3 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f38f1_crc32[BX_SUPPORT_X86_64 + 2] = {
/* 16 */ { 0, BX_IA_CRC32_GdEw },
/* 32 */ { 0, BX_IA_CRC32_GdEd },
#if BX_SUPPORT_X86_64
/* 64 */ { 0, BX_IA_CRC32_GdEq }
#endif
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f38f1[4] = {
/* -- */ { 0, BX_IA_ERROR },
/* -- */ { BxOSizeGrp, BX_IA_ERROR, BxOpcodeGroupSSE_0f38f1_movbe },
/* 66 */ { 0, BX_IA_ERROR },
/* F2 */ { 0, BX_IA_CRC32_GdEv },
/* F2 */ { BxOSizeGrp, BX_IA_ERROR, BxOpcodeGroupSSE_0f38f1_crc32 },
/* F3 */ { 0, BX_IA_ERROR }
};

5
bochs/cpu/fetchdecode64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode64.cc,v 1.208 2008-08-10 21:16:12 sshwarts Exp $
// $Id: fetchdecode64.cc,v 1.209 2008-08-11 18:53:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -3690,6 +3690,9 @@ modrm_done:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[b3]);
break;
#endif
case BxOSizeGrp:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[offset >> 8]);
break;
case BxPrefixSSE:
/* For SSE opcodes look into another 4 entries table
with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3) */

19
bochs/cpu/ia_opcodes.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ia_opcodes.h,v 1.15 2008-08-10 21:16:12 sshwarts Exp $
// $Id: ia_opcodes.h,v 1.16 2008-08-11 18:53:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008 Stanislav Shwartsman
@ -1255,13 +1255,28 @@ bx_define_opcode(BX_IA_MOVNTDQA_VdqMdq, &BX_CPU_C::MOVNTDQA_VdqMdq, NULL, 0)
// SSE4.2
bx_define_opcode(BX_IA_CRC32_GdEb, &BX_CPU_C::CRC32_GdEb, NULL, 0)
bx_define_opcode(BX_IA_CRC32_GdEv, &BX_CPU_C::CRC32_GdEv, NULL, 0)
bx_define_opcode(BX_IA_CRC32_GdEw, &BX_CPU_C::CRC32_GdEw, NULL, 0)
bx_define_opcode(BX_IA_CRC32_GdEd, &BX_CPU_C::CRC32_GdEd, NULL, 0)
#if BX_SUPPORT_X86_64
bx_define_opcode(BX_IA_CRC32_GdEq, &BX_CPU_C::CRC32_GdEq, NULL, 0)
#endif
bx_define_opcode(BX_IA_PCMPGTQ_VdqWdq, &BX_CPU_C::PCMPGTQ_VdqWdq, NULL, 0)
bx_define_opcode(BX_IA_PCMPESTRM_VdqWdqIb, &BX_CPU_C::PCMPESTRM_VdqWdqIb, NULL, 0)
bx_define_opcode(BX_IA_PCMPESTRI_VdqWdqIb, &BX_CPU_C::PCMPESTRI_VdqWdqIb, NULL, 0)
bx_define_opcode(BX_IA_PCMPISTRM_VdqWdqIb, &BX_CPU_C::PCMPISTRM_VdqWdqIb, NULL, 0)
bx_define_opcode(BX_IA_PCMPISTRI_VdqWdqIb, &BX_CPU_C::PCMPISTRI_VdqWdqIb, NULL, 0)
// SSE4.2
// MOVBE instruction
bx_define_opcode(BX_IA_MOVBE_GwEw, &BX_CPU_C::MOVBE_GwEw, NULL, 0)
bx_define_opcode(BX_IA_MOVBE_GdEd, &BX_CPU_C::MOVBE_GdEd, NULL, 0)
bx_define_opcode(BX_IA_MOVBE_EwGw, &BX_CPU_C::MOVBE_EwGw, NULL, 0)
bx_define_opcode(BX_IA_MOVBE_EdGd, &BX_CPU_C::MOVBE_EdGd, NULL, 0)
#if BX_SUPPORT_X86_64
bx_define_opcode(BX_IA_MOVBE_GqEq, &BX_CPU_C::MOVBE_GqEq, NULL, 0)
bx_define_opcode(BX_IA_MOVBE_EqGq, &BX_CPU_C::MOVBE_EqGq, NULL, 0)
#endif
// MOVBE instruction
#endif
// XSAVE extensions

4
bochs/cpu/sse.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse.cc,v 1.61 2008-08-08 09:22:48 sshwarts Exp $
// $Id: sse.cc,v 1.62 2008-08-11 18:53:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003 Stanislav Shwartsman
@ -758,7 +758,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKUSDW_VdqWdq(bxInstruction_c *i)
/* 66 0F 38 37 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTQ_VdqWdq(bxInstruction_c *i)
{
#if (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
#if (BX_SUPPORT_SSE > 4) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
BX_CPU_THIS_PTR prepareSSE();
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;

14
bochs/cpu/sse_string.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse_string.cc,v 1.9 2008-08-08 09:22:49 sshwarts Exp $
// $Id: sse_string.cc,v 1.10 2008-08-11 18:53:24 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007 Stanislav Shwartsman
@ -31,7 +31,7 @@
#define RCX ECX
#endif
#if (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
#if (BX_SUPPORT_SSE > 4) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
// Compare all pairs of Ai, Bj according to imm8 control
static void compare_strings(bx_bool BoolRes[16][16], BxPackedXmmRegister op1, BxPackedXmmRegister op2, Bit8u imm)
@ -286,7 +286,7 @@ static Bit16u aggregate(bx_bool BoolRes[16][16], unsigned len1, unsigned len2, B
return result;
}
#endif // (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
#endif // (BX_SUPPORT_SSE > 4) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
// for 3-byte opcodes
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
@ -294,7 +294,7 @@ static Bit16u aggregate(bx_bool BoolRes[16][16], unsigned len1, unsigned len2, B
/* 66 0F 3A 60 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRM_VdqWdqIb(bxInstruction_c *i)
{
#if (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
#if (BX_SUPPORT_SSE > 4) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
BX_CPU_THIS_PTR prepareSSE();
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
@ -364,7 +364,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRM_VdqWdqIb(bxInstruction_c *i)
/* 66 0F 3A 61 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRI_VdqWdqIb(bxInstruction_c *i)
{
#if (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
#if (BX_SUPPORT_SSE > 4) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
BX_CPU_THIS_PTR prepareSSE();
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
@ -431,7 +431,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRI_VdqWdqIb(bxInstruction_c *i)
/* 66 0F 3A 62 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRM_VdqWdqIb(bxInstruction_c *i)
{
#if (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
#if (BX_SUPPORT_SSE > 4) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
BX_CPU_THIS_PTR prepareSSE();
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
@ -492,7 +492,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRM_VdqWdqIb(bxInstruction_c *i)
/* 66 0F 3A 63 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRI_VdqWdqIb(bxInstruction_c *i)
{
#if (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
#if (BX_SUPPORT_SSE > 4) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
BX_CPU_THIS_PTR prepareSSE();
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;