some simple SSE code optimizations
This commit is contained in:
Stanislav Shwartsman
parent
bb734a906c
commit
8cfd17202a
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.183 2007-11-24 14:22:32 sshwarts Exp $
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// $Id: cpu.cc,v 1.184 2007-11-27 22:12:44 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -200,9 +200,7 @@ void BX_CPU_C::cpu_loop(Bit32u max_instr_count)
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#endif
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CHECK_MAX_INSTRUCTIONS(max_instr_count);
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#if BX_GDBSTUB
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if (bx_dbg.gdbstub_enabled) {
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return;
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}
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if (bx_dbg.gdbstub_enabled) return;
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#endif
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.376 2007-11-25 20:22:06 sshwarts Exp $
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// $Id: cpu.h,v 1.377 2007-11-27 22:12:44 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1531,13 +1531,9 @@ public: // for now...
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BX_SMF void MOV_EwIwR(bxInstruction_c *);
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BX_SMF void MOV_EbIbR(bxInstruction_c *);
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BX_SMF void RETnear32(bxInstruction_c *);
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BX_SMF void RETnear16(bxInstruction_c *);
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BX_SMF void ENTER16_IwIb(bxInstruction_c *);
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BX_SMF void ENTER32_IwIb(bxInstruction_c *);
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BX_SMF void LEAVE(bxInstruction_c *);
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BX_SMF void RETfar32(bxInstruction_c *);
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BX_SMF void RETfar16(bxInstruction_c *);
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BX_SMF void INT1(bxInstruction_c *);
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BX_SMF void INT3(bxInstruction_c *);
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@ -2593,9 +2589,13 @@ public: // for now...
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BX_SMF void CMPXCHG_IBTS(bxInstruction_c *);
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BX_SMF void CMPXCHG8B(bxInstruction_c *);
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BX_SMF void RETnear32_Iw(bxInstruction_c *);
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BX_SMF void RETnear32(bxInstruction_c *);
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BX_SMF void RETnear16_Iw(bxInstruction_c *);
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BX_SMF void RETnear16(bxInstruction_c *);
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BX_SMF void RETfar32_Iw(bxInstruction_c *);
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BX_SMF void RETfar32(bxInstruction_c *);
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BX_SMF void RETfar16_Iw(bxInstruction_c *);
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BX_SMF void RETfar16(bxInstruction_c *);
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BX_SMF void XADD_EbGbM(bxInstruction_c *);
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BX_SMF void XADD_EwGwM(bxInstruction_c *);
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@ -2868,10 +2868,10 @@ public: // for now...
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BX_SMF void CQO(bxInstruction_c *);
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BX_SMF void XADD_EqGqR(bxInstruction_c *);
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BX_SMF void XADD_EqGqM(bxInstruction_c *);
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BX_SMF void RETnear64(bxInstruction_c *);
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BX_SMF void RETnear64_Iw(bxInstruction_c *);
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BX_SMF void RETfar64(bxInstruction_c *);
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BX_SMF void RETnear64(bxInstruction_c *);
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BX_SMF void RETfar64_Iw(bxInstruction_c *);
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BX_SMF void RETfar64(bxInstruction_c *);
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BX_SMF void CMOV_GqEq(bxInstruction_c *);
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@ -2897,21 +2897,23 @@ public: // for now...
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BX_SMF void LGDT64_Ms(bxInstruction_c *);
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BX_SMF void LIDT64_Ms(bxInstruction_c *);
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BX_SMF void SYSCALL(bxInstruction_c *i);
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BX_SMF void SYSRET(bxInstruction_c *i);
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BX_SMF void SWAPGS(bxInstruction_c *i);
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BX_SMF void SYSCALL(bxInstruction_c *);
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BX_SMF void SYSRET(bxInstruction_c *);
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BX_SMF void SWAPGS(bxInstruction_c *);
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BX_SMF void RDTSCP(bxInstruction_c *);
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BX_SMF void CMPXCHG16B(bxInstruction_c *);
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BX_SMF void LOOPNE64_Jb(bxInstruction_c *);
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BX_SMF void LOOPE64_Jb(bxInstruction_c *);
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BX_SMF void LOOP64_Jb(bxInstruction_c *);
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BX_SMF void JCXZ64_Jb(bxInstruction_c *);
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BX_SMF void RDTSCP(bxInstruction_c *);
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BX_SMF void CMPXCHG16B(bxInstruction_c *);
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BX_SMF void MOVQ_EqPq(bxInstruction_c *);
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BX_SMF void MOVQ_EqVq(bxInstruction_c *);
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BX_SMF void MOVQ_PqEq(bxInstruction_c *);
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BX_SMF void MOVQ_VdqEq(bxInstruction_c *);
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BX_SMF void MOVNTI_MqGq(bxInstruction_c *);
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BX_SMF void POPCNT_GqEq(bxInstruction_c *);
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BX_SMF void MOVNTI_MqGq(bxInstruction_c *i);
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#endif // #if BX_SUPPORT_X86_64
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BX_SMF void INVLPG(bxInstruction_c *);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.141 2007-11-25 20:22:06 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.142 2007-11-27 22:12:44 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -387,7 +387,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* C8 /wr */ { BxImmediate_IwIb, &BX_CPU_C::ENTER16_IwIb },
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/* C9 /wr */ { 0, &BX_CPU_C::LEAVE },
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/* CA /wr */ { BxImmediate_Iw, &BX_CPU_C::RETfar16_Iw },
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/* CB /wr */ { 0, &BX_CPU_C::RETfar16 },
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/* CB /wr */ { 0, &BX_CPU_C::RETfar16 },
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/* CC /wr */ { 0, &BX_CPU_C::INT3 },
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/* CD /wr */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
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/* CE /wr */ { 0, &BX_CPU_C::INTO },
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@ -491,11 +491,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* 0F 10 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f10 },
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/* 0F 11 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f11 },
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/* 0F 12 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f12 },
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/* 0F 13 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13 },
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/* 0F 13 /wr */ { 0, &BX_CPU_C::BxError }, // MOVLPS/PD SSE group
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/* 0F 14 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f14 },
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/* 0F 15 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f15 },
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/* 0F 16 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f16 },
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/* 0F 17 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17 },
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/* 0F 17 /wr */ { 0, &BX_CPU_C::BxError }, // MOHLPS/PD SSE group
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/* 0F 18 /wr */ { 0, &BX_CPU_C::PREFETCH }, // opcode group G16, PREFETCH hints
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#if BX_CPU_LEVEL < 6
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/* 0F 19 /wr */ { 0, &BX_CPU_C::BxError },
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@ -951,7 +951,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* C8 /dr */ { BxImmediate_IwIb, &BX_CPU_C::ENTER32_IwIb },
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/* C9 /dr */ { 0, &BX_CPU_C::LEAVE },
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/* CA /dr */ { BxImmediate_Iw, &BX_CPU_C::RETfar32_Iw },
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/* CB /dr */ { 0, &BX_CPU_C::RETfar32 },
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/* CB /dr */ { 0, &BX_CPU_C::RETfar32 },
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/* CC /dr */ { 0, &BX_CPU_C::INT3 },
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/* CD /dr */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
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/* CE /dr */ { 0, &BX_CPU_C::INTO },
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@ -1055,11 +1055,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* 0F 10 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f10 },
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/* 0F 11 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f11 },
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/* 0F 12 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f12 },
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/* 0F 13 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13 },
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/* 0F 13 /dr */ { 0, &BX_CPU_C::BxError }, // MOVLPS/PD SSE group
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/* 0F 14 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f14 },
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/* 0F 15 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f15 },
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/* 0F 16 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f16 },
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/* 0F 17 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17 },
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/* 0F 17 /dr */ { 0, &BX_CPU_C::BxError }, // MOHLPS/PD SSE group
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/* 0F 18 /dr */ { 0, &BX_CPU_C::PREFETCH }, // opcode group G16, PREFETCH hints
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#if BX_CPU_LEVEL < 6
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/* 0F 19 /dr */ { 0, &BX_CPU_C::BxError },
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@ -1522,7 +1522,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* C8 /wm */ { BxImmediate_IwIb, &BX_CPU_C::ENTER16_IwIb },
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/* C9 /wm */ { 0, &BX_CPU_C::LEAVE },
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/* CA /wm */ { BxImmediate_Iw, &BX_CPU_C::RETfar16_Iw },
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/* CB /wm */ { 0, &BX_CPU_C::RETfar16 },
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/* CB /wm */ { 0, &BX_CPU_C::RETfar16 },
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/* CC /wm */ { 0, &BX_CPU_C::INT3 },
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/* CD /wm */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
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/* CE /wm */ { 0, &BX_CPU_C::INTO },
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@ -1626,11 +1626,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* 0F 10 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f10 },
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/* 0F 11 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f11 },
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/* 0F 12 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f12 },
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/* 0F 13 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13 },
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/* 0F 13 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13M },
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/* 0F 14 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f14 },
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/* 0F 15 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f15 },
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/* 0F 16 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f16 },
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/* 0F 17 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17 },
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/* 0F 17 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17M },
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/* 0F 18 /wm */ { 0, &BX_CPU_C::PREFETCH }, // opcode group G16, PREFETCH hints
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#if BX_CPU_LEVEL < 6
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/* 0F 19 /wm */ { 0, &BX_CPU_C::BxError },
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@ -2086,7 +2086,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* C8 /dm */ { BxImmediate_IwIb, &BX_CPU_C::ENTER32_IwIb },
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/* C9 /dm */ { 0, &BX_CPU_C::LEAVE },
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/* CA /dm */ { BxImmediate_Iw, &BX_CPU_C::RETfar32_Iw },
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/* CB /dm */ { 0, &BX_CPU_C::RETfar32 },
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/* CB /dm */ { 0, &BX_CPU_C::RETfar32 },
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/* CC /dm */ { 0, &BX_CPU_C::INT3 },
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/* CD /dm */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
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/* CE /dm */ { 0, &BX_CPU_C::INTO },
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@ -2190,11 +2190,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* 0F 10 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f10 },
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/* 0F 11 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f11 },
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/* 0F 12 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f12 },
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/* 0F 13 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13 },
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/* 0F 13 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13M },
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/* 0F 14 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f14 },
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/* 0F 15 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f15 },
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/* 0F 16 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f16 },
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/* 0F 17 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17 },
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/* 0F 17 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17M },
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/* 0F 18 /dm */ { 0, &BX_CPU_C::PREFETCH }, // opcode group G16, PREFETCH hints
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#if BX_CPU_LEVEL < 6
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/* 0F 19 /dm */ { 0, &BX_CPU_C::BxError },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.h,v 1.42 2007-11-25 20:22:10 sshwarts Exp $
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// $Id: fetchdecode.h,v 1.43 2007-11-27 22:12:45 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005 Stanislav Shwartsman
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@ -998,7 +998,7 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f12[4] = {
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/* F3 */ { 0, &BX_CPU_C::MOVSLDUP_VpsWps } // SSE3
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f13[4] = {
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f13M[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVLPS_MqVps },
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/* 66 */ { 0, &BX_CPU_C::MOVLPD_MqVsd },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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@ -1026,7 +1026,7 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f16[4] = {
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/* F3 */ { 0, &BX_CPU_C::MOVSHDUP_VpsWps } // SSE3
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f17[4] = {
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f17M[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVHPS_MqVps },
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/* 66 */ { 0, &BX_CPU_C::MOVHPD_MqVsd },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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@ -1306,6 +1306,13 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f6e[4] = {
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f6eQ[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVQ_PqEq },
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/* 66 */ { 0, &BX_CPU_C::MOVQ_VdqEq },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f6f[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVQ_PqQq },
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/* 66 */ { 0, &BX_CPU_C::MOVDQA_VdqWdq },
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@ -1362,6 +1369,13 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f7e[4] = {
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/* F3 */ { 0, &BX_CPU_C::MOVQ_VqWq }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f7eQ[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVQ_EqPq },
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/* 66 */ { 0, &BX_CPU_C::MOVQ_EqVq },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::MOVQ_VqWq }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f7f[4] = {
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/* -- */ { 0, &BX_CPU_C::MOVQ_QqPq },
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/* 66 */ { 0, &BX_CPU_C::MOVDQA_WdqVdq },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode64.cc,v 1.149 2007-11-25 20:22:10 sshwarts Exp $
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// $Id: fetchdecode64.cc,v 1.150 2007-11-27 22:12:45 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -376,7 +376,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
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/* C8 /wr */ { BxImmediate_IwIb, &BX_CPU_C::ENTER64_IwIb },
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/* C9 /wr */ { 0, &BX_CPU_C::LEAVE64 },
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/* CA /wr */ { BxImmediate_Iw, &BX_CPU_C::RETfar16_Iw },
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/* CB /wr */ { 0, &BX_CPU_C::RETfar16 },
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/* CB /wr */ { 0, &BX_CPU_C::RETfar16 },
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/* CC /wr */ { 0, &BX_CPU_C::INT3 },
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/* CD /wr */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
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/* CE /wr */ { 0, &BX_CPU_C::BxError },
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@ -455,11 +455,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
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/* 0F 10 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f10 },
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/* 0F 11 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f11 },
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/* 0F 12 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f12 },
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/* 0F 13 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13 },
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/* 0F 13 /wr */ { 0, &BX_CPU_C::BxError }, // MOVLPS/PD SSE group
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/* 0F 14 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f14 },
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/* 0F 15 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f15 },
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/* 0F 16 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f16 },
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/* 0F 17 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17 },
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/* 0F 17 /wr */ { 0, &BX_CPU_C::BxError }, // MOHLPS/PD SSE group
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/* 0F 18 /wr */ { 0, &BX_CPU_C::PREFETCH }, // opcode group G16, PREFETCH hints
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/* 0F 19 /wr */ { 0, &BX_CPU_C::NOP }, // multi-byte NOP
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/* 0F 1A /wr */ { 0, &BX_CPU_C::NOP }, // multi-byte NOP
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@ -905,7 +905,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
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||||
/* C8 /dr */ { BxImmediate_IwIb, &BX_CPU_C::ENTER64_IwIb },
|
||||
/* C9 /dr */ { 0, &BX_CPU_C::LEAVE64 },
|
||||
/* CA /dr */ { BxImmediate_Iw, &BX_CPU_C::RETfar32_Iw },
|
||||
/* CB /dr */ { 0, &BX_CPU_C::RETfar32 },
|
||||
/* CB /dr */ { 0, &BX_CPU_C::RETfar32 },
|
||||
/* CC /dr */ { 0, &BX_CPU_C::INT3 },
|
||||
/* CD /dr */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
|
||||
/* CE /dr */ { 0, &BX_CPU_C::BxError },
|
||||
@ -984,11 +984,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F 10 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f10 },
|
||||
/* 0F 11 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f11 },
|
||||
/* 0F 12 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f12 },
|
||||
/* 0F 13 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13 },
|
||||
/* 0F 13 /dr */ { 0, &BX_CPU_C::BxError }, // MOVLPS/PD SSE group
|
||||
/* 0F 14 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f14 },
|
||||
/* 0F 15 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f15 },
|
||||
/* 0F 16 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f16 },
|
||||
/* 0F 17 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17 },
|
||||
/* 0F 17 /dr */ { 0, &BX_CPU_C::BxError }, // MOHLPS/PD SSE group
|
||||
/* 0F 18 /dr */ { 0, &BX_CPU_C::PREFETCH }, // opcode group G16, PREFETCH hints
|
||||
/* 0F 19 /dr */ { 0, &BX_CPU_C::NOP }, // multi-byte NOP
|
||||
/* 0F 1A /dr */ { 0, &BX_CPU_C::NOP }, // multi-byte NOP
|
||||
@ -1434,7 +1434,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* C8 /qr */ { BxImmediate_IwIb, &BX_CPU_C::ENTER64_IwIb },
|
||||
/* C9 /qr */ { 0, &BX_CPU_C::LEAVE64 },
|
||||
/* CA /qr */ { BxImmediate_Iw, &BX_CPU_C::RETfar64_Iw },
|
||||
/* CB /qr */ { 0, &BX_CPU_C::RETfar64 },
|
||||
/* CB /qr */ { 0, &BX_CPU_C::RETfar64 },
|
||||
/* CC /qr */ { 0, &BX_CPU_C::INT3 },
|
||||
/* CD /qr */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
|
||||
/* CE /qr */ { 0, &BX_CPU_C::BxError },
|
||||
@ -1513,11 +1513,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F 10 /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f10 },
|
||||
/* 0F 11 /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f11 },
|
||||
/* 0F 12 /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f12 },
|
||||
/* 0F 13 /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13 },
|
||||
/* 0F 13 /qr */ { 0, &BX_CPU_C::BxError }, // MOVLPS/PD SSE group
|
||||
/* 0F 14 /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f14 },
|
||||
/* 0F 15 /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f15 },
|
||||
/* 0F 16 /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f16 },
|
||||
/* 0F 17 /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17 },
|
||||
/* 0F 17 /qr */ { 0, &BX_CPU_C::BxError }, // MOHLPS/PD SSE group
|
||||
/* 0F 18 /qr */ { 0, &BX_CPU_C::PREFETCH }, // opcode group G16, PREFETCH hints
|
||||
/* 0F 19 /qr */ { 0, &BX_CPU_C::NOP }, // multi-byte NOP
|
||||
/* 0F 1A /qr */ { 0, &BX_CPU_C::NOP }, // multi-byte NOP
|
||||
@ -1612,7 +1612,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F 6B /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6b },
|
||||
/* 0F 6C /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6c },
|
||||
/* 0F 6D /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6d },
|
||||
/* 0F 6E /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6e },
|
||||
/* 0F 6E /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6eQ },
|
||||
/* 0F 6F /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6f },
|
||||
/* 0F 70 /qr */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f70 },
|
||||
/* 0F 71 /qr */ { BxGroup12, NULL, BxOpcodeInfoG12 },
|
||||
@ -1628,7 +1628,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F 7B /qr */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F 7C /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7c },
|
||||
/* 0F 7D /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7d },
|
||||
/* 0F 7E /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7e },
|
||||
/* 0F 7E /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7eQ },
|
||||
/* 0F 7F /qr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7f },
|
||||
/* 0F 80 /qr */ { BxImmediate_BrOff32, &BX_CPU_C::JO_Jq },
|
||||
/* 0F 81 /qr */ { BxImmediate_BrOff32, &BX_CPU_C::JNO_Jq },
|
||||
@ -1969,7 +1969,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* C8 /wm */ { BxImmediate_IwIb, &BX_CPU_C::ENTER16_IwIb },
|
||||
/* C9 /wm */ { 0, &BX_CPU_C::LEAVE },
|
||||
/* CA /wm */ { BxImmediate_Iw, &BX_CPU_C::RETfar16_Iw },
|
||||
/* CB /wm */ { 0, &BX_CPU_C::RETfar16 },
|
||||
/* CB /wm */ { 0, &BX_CPU_C::RETfar16 },
|
||||
/* CC /wm */ { 0, &BX_CPU_C::INT3 },
|
||||
/* CD /wm */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
|
||||
/* CE /wm */ { 0, &BX_CPU_C::BxError },
|
||||
@ -2048,11 +2048,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F 10 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f10 },
|
||||
/* 0F 11 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f11 },
|
||||
/* 0F 12 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f12 },
|
||||
/* 0F 13 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13 },
|
||||
/* 0F 13 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13M },
|
||||
/* 0F 14 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f14 },
|
||||
/* 0F 15 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f15 },
|
||||
/* 0F 16 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f16 },
|
||||
/* 0F 17 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17 },
|
||||
/* 0F 17 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17M },
|
||||
/* 0F 18 /wm */ { 0, &BX_CPU_C::PREFETCH }, // opcode group G16, PREFETCH hints
|
||||
/* 0F 19 /wm */ { 0, &BX_CPU_C::NOP }, // multi-byte NOP
|
||||
/* 0F 1A /wm */ { 0, &BX_CPU_C::NOP }, // multi-byte NOP
|
||||
@ -2498,7 +2498,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* C8 /dm */ { BxImmediate_IwIb, &BX_CPU_C::ENTER64_IwIb },
|
||||
/* C9 /dm */ { 0, &BX_CPU_C::LEAVE64 },
|
||||
/* CA /dm */ { BxImmediate_Iw, &BX_CPU_C::RETfar32_Iw },
|
||||
/* CB /dm */ { 0, &BX_CPU_C::RETfar32 },
|
||||
/* CB /dm */ { 0, &BX_CPU_C::RETfar32 },
|
||||
/* CC /dm */ { 0, &BX_CPU_C::INT3 },
|
||||
/* CD /dm */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
|
||||
/* CE /dm */ { 0, &BX_CPU_C::BxError },
|
||||
@ -2577,11 +2577,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F 10 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f10 },
|
||||
/* 0F 11 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f11 },
|
||||
/* 0F 12 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f12 },
|
||||
/* 0F 13 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13 },
|
||||
/* 0F 13 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13M },
|
||||
/* 0F 14 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f14 },
|
||||
/* 0F 15 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f15 },
|
||||
/* 0F 16 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f16 },
|
||||
/* 0F 17 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17 },
|
||||
/* 0F 17 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17M },
|
||||
/* 0F 18 /dm */ { 0, &BX_CPU_C::PREFETCH }, // opcode group G16, PREFETCH hints
|
||||
/* 0F 19 /dm */ { 0, &BX_CPU_C::NOP }, // multi-byte NOP
|
||||
/* 0F 1A /dm */ { 0, &BX_CPU_C::NOP }, // multi-byte NOP
|
||||
@ -3027,7 +3027,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* C8 /qm */ { BxImmediate_IwIb, &BX_CPU_C::ENTER64_IwIb },
|
||||
/* C9 /qm */ { 0, &BX_CPU_C::LEAVE64 },
|
||||
/* CA /qm */ { BxImmediate_Iw, &BX_CPU_C::RETfar64_Iw },
|
||||
/* CB /qm */ { 0, &BX_CPU_C::RETfar64 },
|
||||
/* CB /qm */ { 0, &BX_CPU_C::RETfar64 },
|
||||
/* CC /qm */ { 0, &BX_CPU_C::INT3 },
|
||||
/* CD /qm */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
|
||||
/* CE /qm */ { 0, &BX_CPU_C::BxError },
|
||||
@ -3106,11 +3106,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F 10 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f10 },
|
||||
/* 0F 11 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f11 },
|
||||
/* 0F 12 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f12 },
|
||||
/* 0F 13 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13 },
|
||||
/* 0F 13 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f13M },
|
||||
/* 0F 14 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f14 },
|
||||
/* 0F 15 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f15 },
|
||||
/* 0F 16 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f16 },
|
||||
/* 0F 17 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17 },
|
||||
/* 0F 17 /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f17M },
|
||||
/* 0F 18 /qm */ { 0, &BX_CPU_C::PREFETCH }, // opcode group G16, PREFETCH hints
|
||||
/* 0F 19 /qm */ { 0, &BX_CPU_C::NOP }, // multi-byte NOP
|
||||
/* 0F 1A /qm */ { 0, &BX_CPU_C::NOP }, // multi-byte NOP
|
||||
@ -3205,7 +3205,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F 6B /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6b },
|
||||
/* 0F 6C /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6c },
|
||||
/* 0F 6D /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6d },
|
||||
/* 0F 6E /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6e },
|
||||
/* 0F 6E /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6eQ },
|
||||
/* 0F 6F /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f6f },
|
||||
/* 0F 70 /qm */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f70 },
|
||||
/* 0F 71 /qm */ { BxGroup12, NULL, BxOpcodeInfoG12 },
|
||||
@ -3221,7 +3221,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F 7B /qm */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F 7C /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7c },
|
||||
/* 0F 7D /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7d },
|
||||
/* 0F 7E /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7e },
|
||||
/* 0F 7E /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7eQ },
|
||||
/* 0F 7F /qm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7f },
|
||||
/* 0F 80 /qm */ { BxImmediate_BrOff32, &BX_CPU_C::JO_Jq },
|
||||
/* 0F 81 /qm */ { BxImmediate_BrOff32, &BX_CPU_C::JNO_Jq },
|
||||
|
||||
103
bochs/cpu/mmx.cc
103
bochs/cpu/mmx.cc
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: mmx.cc,v 1.63 2007-11-17 12:44:10 sshwarts Exp $
|
||||
// $Id: mmx.cc,v 1.64 2007-11-27 22:12:45 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2002 Stanislav Shwartsman
|
||||
@ -987,31 +987,15 @@ void BX_CPU_C::MOVD_PqEd(bxInstruction_c *i)
|
||||
|
||||
BxPackedMmxRegister op;
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->os64L()) /* 64 bit operand size mode */
|
||||
{
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
MMXUQ(op) = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_qword(i->seg(), RMAddr(i), &(MMXUQ(op)));
|
||||
}
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
MMXUD1(op) = 0;
|
||||
MMXUD1(op) = 0;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
MMXUD0(op) = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_dword(i->seg(), RMAddr(i), &(MMXUD0(op)));
|
||||
}
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
MMXUD0(op) = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_dword(i->seg(), RMAddr(i), &(MMXUD0(op)));
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
@ -1022,6 +1006,30 @@ void BX_CPU_C::MOVD_PqEd(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 0F 6E */
|
||||
#if BX_SUPPORT_X86_64
|
||||
|
||||
void BX_CPU_C::MOVQ_PqEq(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
MMXUQ(op) = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_qword(i->seg(), RMAddr(i), &(MMXUQ(op)));
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_MMX_REG(i->nnn(), op);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* 0F 6F */
|
||||
void BX_CPU_C::MOVQ_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
@ -1190,27 +1198,12 @@ void BX_CPU_C::MOVD_EdPd(bxInstruction_c *i)
|
||||
|
||||
BxPackedMmxRegister op = BX_READ_MMX_REG(i->nnn());
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->os64L()) /* 64 bit operand size mode */
|
||||
{
|
||||
/* destination is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), MMXUQ(op));
|
||||
}
|
||||
else {
|
||||
write_virtual_qword(i->seg(), RMAddr(i), &(MMXUQ(op)));
|
||||
}
|
||||
/* destination is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), MMXUD0(op));
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
/* destination is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), MMXUD0(op));
|
||||
}
|
||||
else {
|
||||
write_virtual_dword(i->seg(), RMAddr(i), &(MMXUD0(op)));
|
||||
}
|
||||
else {
|
||||
write_virtual_dword(i->seg(), RMAddr(i), &(MMXUD0(op)));
|
||||
}
|
||||
|
||||
#else
|
||||
@ -1219,6 +1212,26 @@ void BX_CPU_C::MOVD_EdPd(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
|
||||
/* 0F 7E */
|
||||
void BX_CPU_C::MOVQ_EqPq(bxInstruction_c *i)
|
||||
{
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op = BX_READ_MMX_REG(i->nnn());
|
||||
|
||||
/* destination is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), MMXUQ(op));
|
||||
}
|
||||
else {
|
||||
write_virtual_qword(i->seg(), RMAddr(i), &(MMXUQ(op)));
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* 0F 7F */
|
||||
void BX_CPU_C::MOVQ_QqPq(bxInstruction_c *i)
|
||||
{
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: proc_ctrl.cc,v 1.182 2007-11-20 21:22:03 sshwarts Exp $
|
||||
// $Id: proc_ctrl.cc,v 1.183 2007-11-27 22:12:45 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -34,7 +34,6 @@
|
||||
#if BX_SUPPORT_X86_64==0
|
||||
// Make life easier for merging code.
|
||||
#define RAX EAX
|
||||
#define RBX EBX
|
||||
#define RCX ECX
|
||||
#define RDX EDX
|
||||
#endif
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: sse_move.cc,v 1.66 2007-11-25 20:52:40 sshwarts Exp $
|
||||
// $Id: sse_move.cc,v 1.67 2007-11-27 22:12:45 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2003 Stanislav Shwartsman
|
||||
@ -491,17 +491,15 @@ void BX_CPU_C::MOVSS_VssWss(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
|
||||
Bit32u val32;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0())
|
||||
{
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
|
||||
/* If the source operand is an XMM register, the high-order
|
||||
96 bits of the destination XMM register are not modified. */
|
||||
op1.xmm32u(0) = op2.xmm32u(0);
|
||||
op.xmm32u(0) = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
@ -509,13 +507,13 @@ void BX_CPU_C::MOVSS_VssWss(bxInstruction_c *i)
|
||||
|
||||
/* If the source operand is a memory location, the high-order
|
||||
96 bits of the destination XMM register are cleared to 0s */
|
||||
op1.xmm32u(0) = val32;
|
||||
op1.xmm32u(1) = 0;
|
||||
op1.xmm64u(1) = 0;
|
||||
op.xmm32u(0) = val32;
|
||||
op.xmm32u(1) = 0;
|
||||
op.xmm64u(1) = 0;
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("MOVSS_VssWss: required SSE, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
@ -553,17 +551,15 @@ void BX_CPU_C::MOVSD_VsdWsd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
|
||||
Bit64u val64;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0())
|
||||
{
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
|
||||
/* If the source operand is an XMM register, the high-order
|
||||
64 bits of the destination XMM register are not modified. */
|
||||
op1.xmm64u(0) = op2.xmm64u(0);
|
||||
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
@ -571,12 +567,12 @@ void BX_CPU_C::MOVSD_VsdWsd(bxInstruction_c *i)
|
||||
|
||||
/* If the source operand is a memory location, the high-order
|
||||
64 bits of the destination XMM register are cleared to 0s */
|
||||
op1.xmm64u(0) = val64;
|
||||
op1.xmm64u(1) = 0;
|
||||
op.xmm64u(0) = val64;
|
||||
op.xmm64u(1) = 0;
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("MOVSD_VsdWsd: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
@ -724,16 +720,8 @@ void BX_CPU_C::MOVSHDUP_VpsWps(bxInstruction_c *i)
|
||||
void BX_CPU_C::MOVLPS_MqVps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
if (i->modC0())
|
||||
{
|
||||
BX_INFO(("MOVLPS_MqVps: must be memory reference"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
write_virtual_qword(i->seg(), RMAddr(i), &BX_XMM_REG_LO_QWORD(i->nnn()));
|
||||
|
||||
#else
|
||||
BX_INFO(("MOVLPS_MqVps: required SSE, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
@ -770,16 +758,8 @@ void BX_CPU_C::MOVHPS_VpsMq(bxInstruction_c *i)
|
||||
void BX_CPU_C::MOVHPS_MqVps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
if (i->modC0())
|
||||
{
|
||||
BX_INFO(("MOVHPS_MqVps: must be memory reference"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
write_virtual_qword(i->seg(), RMAddr(i), &BX_XMM_REG_HI_QWORD(i->nnn()));
|
||||
|
||||
#else
|
||||
BX_INFO(("MOVHPS_MqVps: required SSE, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
@ -892,41 +872,20 @@ void BX_CPU_C::MOVD_VdqEd(bxInstruction_c *i)
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1;
|
||||
Bit32u op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_dword(i->seg(), RMAddr(i), &op2);
|
||||
}
|
||||
|
||||
op1.xmm64u(0) = (Bit64u)(op2);
|
||||
op1.xmm64u(1) = 0;
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->os64L()) /* 64 bit operand size mode */
|
||||
{
|
||||
Bit64u op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_qword(i->seg(), RMAddr(i), &op2);
|
||||
}
|
||||
|
||||
op1.xmm64u(0) = op2;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
Bit32u op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_dword(i->seg(), RMAddr(i), &op2);
|
||||
}
|
||||
|
||||
op1.xmm64u(0) = (Bit64u)(op2);
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
@ -935,41 +894,54 @@ void BX_CPU_C::MOVD_VdqEd(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
|
||||
/* 66 0F 6E */
|
||||
void BX_CPU_C::MOVQ_VdqEq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1;
|
||||
Bit64u op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_qword(i->seg(), RMAddr(i), &op2);
|
||||
}
|
||||
|
||||
op1.xmm64u(0) = op2;
|
||||
op1.xmm64u(1) = 0;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("MOVQ_VdqEq: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* 66 0F 7E */
|
||||
void BX_CPU_C::MOVD_EdVd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn());
|
||||
Bit32u op2 = BX_READ_XMM_REG_LO_DWORD(i->nnn());
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->os64L()) /* 64 bit operand size mode */
|
||||
{
|
||||
Bit64u op2 = op1.xmm64u(0);
|
||||
|
||||
/* destination is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), op2);
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
write_virtual_qword(i->seg(), RMAddr(i), &op2);
|
||||
}
|
||||
/* destination is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), op2);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
Bit32u op2 = op1.xmm32u(0);
|
||||
|
||||
/* destination is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), op2);
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
write_virtual_dword(i->seg(), RMAddr(i), &op2);
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
write_virtual_dword(i->seg(), RMAddr(i), &op2);
|
||||
}
|
||||
#else
|
||||
BX_INFO(("MOVD_EdVd: required SSE2, use --enable-sse option"));
|
||||
@ -977,6 +949,32 @@ void BX_CPU_C::MOVD_EdVd(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
|
||||
/* 66 0F 7E */
|
||||
void BX_CPU_C::MOVQ_EqVq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Bit64u op2 = BX_READ_XMM_REG_LO_QWORD(i->nnn());
|
||||
|
||||
/* destination is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), op2);
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
write_virtual_qword(i->seg(), RMAddr(i), &op2);
|
||||
}
|
||||
#else
|
||||
BX_INFO(("MOVQ_EqVq: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* F3 0F 7E */
|
||||
void BX_CPU_C::MOVQ_VqWq(bxInstruction_c *i)
|
||||
{
|
||||
@ -987,7 +985,7 @@ void BX_CPU_C::MOVQ_VqWq(bxInstruction_c *i)
|
||||
Bit64u val64;
|
||||
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user