Some code cleanups and warning fixes
This commit is contained in:
Stanislav Shwartsman
parent
55d2446fe4
commit
b8787fd5a7
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.313 2007-03-06 17:47:18 sshwarts Exp $
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// $Id: cpu.h,v 1.314 2007-03-14 21:15:14 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -2147,7 +2147,7 @@ public: // for now...
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// Although in implementation, these instructions are aliased to the
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// another function, it's nice to have them call a seperate function when
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// the decoder is being tested in stand-alone mode.
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#ifdef StandAloneDecoder
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#ifdef STAND_ALONE_DECODER
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BX_SMF void MOVUPD_VpdWpd(bxInstruction_c *);
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BX_SMF void MOVUPD_WpdVpd(bxInstruction_c *);
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BX_SMF void MOVAPD_VpdWpd(bxInstruction_c *);
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@ -2175,14 +2175,21 @@ public: // for now...
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BX_SMF void MOVNTPD_MdqVpd(bxInstruction_c *);
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BX_SMF void MOVNTDQ_MdqVdq(bxInstruction_c *);
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#else
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#define MOVUPD_VpdWpd /* 66 0f 10 */ MOVUPS_VpsWps /* 0f 10 */
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#define MOVUPD_WpdVpd /* 66 0f 11 */ MOVUPS_WpsVps /* 0f 11 */
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#define MOVAPD_VpdWpd /* 66 0f 28 */ MOVAPS_VpsWps /* 0f 28 */
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#define MOVAPD_WpdVpd /* 66 0f 29 */ MOVAPS_WpsVps /* 0f 29 */
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#define MOVDQU_VdqWdq /* f3 0f 6f */ MOVUPS_VpsWps /* 0f 10 */
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#define MOVDQU_WdqVdq /* f3 0f 7f */ MOVUPS_WpsVps /* 0f 11 */
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#define MOVDQA_VdqWdq /* 66 0f 6f */ MOVAPS_VpsWps /* 0f 28 */
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#define MOVDQA_WdqVdq /* 66 0f 7f */ MOVAPS_WpsVps /* 0f 29 */
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#if BX_SUPPORT_SSE >= 2
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#define SSE2_ALIAS(i) i
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#else
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#define SSE2_ALIAS(i) BxError
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#endif
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#define MOVUPD_VpdWpd /* 66 0f 10 */ SSE2_ALIAS(MOVUPS_VpsWps) /* 0f 10 */
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#define MOVUPD_WpdVpd /* 66 0f 11 */ SSE2_ALIAS(MOVUPS_WpsVps) /* 0f 11 */
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#define MOVAPD_VpdWpd /* 66 0f 28 */ SSE2_ALIAS(MOVAPS_VpsWps) /* 0f 28 */
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#define MOVAPD_WpdVpd /* 66 0f 29 */ SSE2_ALIAS(MOVAPS_WpsVps) /* 0f 29 */
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#define MOVDQU_VdqWdq /* f3 0f 6f */ SSE2_ALIAS(MOVUPS_VpsWps) /* 0f 10 */
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#define MOVDQU_WdqVdq /* f3 0f 7f */ SSE2_ALIAS(MOVUPS_WpsVps) /* 0f 11 */
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#define MOVDQA_VdqWdq /* 66 0f 6f */ SSE2_ALIAS(MOVAPS_VpsWps) /* 0f 28 */
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#define MOVDQA_WdqVdq /* 66 0f 7f */ SSE2_ALIAS(MOVAPS_WpsVps) /* 0f 29 */
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#define UNPCKHPS_VpsWq /* 0f 15 */ PUNPCKHDQ_VdqWq /* 66 0f 6a */
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#define UNPCKLPS_VpsWq /* 0f 14 */ PUNPCKLDQ_VdqWq /* 66 0f 62 */
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@ -2199,14 +2206,15 @@ public: // for now...
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#define UNPCKHPD_VpdWq /* 66 0f 15 */ PUNPCKHQDQ_VdqWq /* 66 0f 6d */
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#define UNPCKLPD_VpdWq /* 66 0f 14 */ PUNPCKLQDQ_VdqWq /* 66 0f 6c */
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#define MOVLPD_VsdMq /* 66 0f 12 */ MOVLPS_VpsMq /* 0f 12 */
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#define MOVLPD_MqVsd /* 66 0f 13 */ MOVLPS_MqVps /* 0f 13 */
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#define MOVHPD_VsdMq /* 66 0f 16 */ MOVHPS_VpsMq /* 0f 16 */
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#define MOVHPD_MqVsd /* 66 0f 17 */ MOVHPS_MqVps /* 0f 17 */
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#define MOVLPD_VsdMq /* 66 0f 12 */ SSE2_ALIAS(MOVLPS_VpsMq) /* 0f 12 */
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#define MOVLPD_MqVsd /* 66 0f 13 */ SSE2_ALIAS(MOVLPS_MqVps) /* 0f 13 */
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#define MOVHPD_VsdMq /* 66 0f 16 */ SSE2_ALIAS(MOVHPS_VpsMq) /* 0f 16 */
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#define MOVHPD_MqVsd /* 66 0f 17 */ SSE2_ALIAS(MOVHPS_MqVps) /* 0f 17 */
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#define MOVNTPD_MdqVpd /* 66 0f 2b */ MOVNTPS_MdqVps /* 0f 2b */
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#define MOVNTDQ_MdqVdq /* 66 0f e7 */ MOVNTPD_MdqVpd /* 66 0f 2b */
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#endif // #ifdef StandAloneDecoder
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#define MOVNTPD_MdqVpd /* 66 0f 2b */ SSE2_ALIAS(MOVNTPS_MdqVps) /* 0f 2b */
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#define MOVNTDQ_MdqVdq /* 66 0f e7 */ SSE2_ALIAS(MOVNTPS_MdqVps) /* 66 0f 2b */
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#endif // #ifdef STAND_ALONE_DECODER
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/* SSE3 */
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BX_SMF void MOVDDUP_VpdWq(bxInstruction_c *i);
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@ -2222,6 +2230,7 @@ public: // for now...
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/* SSE3 */
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#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
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/* SSE3E */
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BX_SMF void PSHUFB_PqQq(bxInstruction_c *i);
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BX_SMF void PHADDW_PqQq(bxInstruction_c *i);
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BX_SMF void PHADDD_PqQq(bxInstruction_c *i);
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@ -2255,6 +2264,7 @@ public: // for now...
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BX_SMF void PABSW_VdqWdq(bxInstruction_c *i);
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BX_SMF void PABSD_VdqWdq(bxInstruction_c *i);
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BX_SMF void PALIGNR_VdqWdqIb(bxInstruction_c *i);
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/* SSE3E */
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#endif
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BX_SMF void CMPXCHG_XBTS(bxInstruction_c *);
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@ -2511,7 +2521,6 @@ public: // for now...
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BX_SMF void CMPXCHG16B(bxInstruction_c *);
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#endif // #if BX_SUPPORT_X86_64
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// mch added
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BX_SMF void INVLPG(bxInstruction_c *);
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BX_SMF void RSM(bxInstruction_c *);
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@ -2874,8 +2883,7 @@ public: // for now...
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#if BX_SUPPORT_X86_64
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BX_SMF void fetch_raw_descriptor64(const bx_selector_t *selector,
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Bit32u *dword1, Bit32u *dword2, Bit32u *dword3, unsigned exception_no);
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BX_SMF void loadSRegLMNominal(unsigned seg, unsigned selector,
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bx_address base, unsigned dpl);
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BX_SMF void loadSRegLMNominal(unsigned seg, unsigned selector, unsigned dpl);
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#endif
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BX_SMF void push_16(Bit16u value16) BX_CPP_AttrRegparmN(1);
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BX_SMF void push_32(Bit32u value32);
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@ -3313,9 +3321,6 @@ IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
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// For decoding...
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//
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#define BX_REPE_PREFIX 10
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#define BX_REPNE_PREFIX 11
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#define BX_TASK_FROM_JUMP 10
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#define BX_TASK_FROM_CALL_OR_INT 11
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#define BX_TASK_FROM_IRET 12
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@ -1,5 +1,5 @@
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////////////////////////////////////////////////////////////////////////
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// $Id: ctrl_xfer_pro.cc,v 1.55 2006-06-12 16:58:26 sshwarts Exp $
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// $Id: ctrl_xfer_pro.cc,v 1.56 2007-03-14 21:15:15 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -108,7 +108,7 @@ BX_CPU_C::load_cs(bx_selector_t *selector, bx_descriptor_t *descriptor, Bit8u cp
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if (descriptor->u.segment.l) {
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BX_CPU_THIS_PTR cpu_mode = BX_MODE_LONG_64;
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BX_DEBUG(("Long Mode Activated"));
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loadSRegLMNominal(BX_SEG_REG_CS, selector->value, 0, cpl);
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loadSRegLMNominal(BX_SEG_REG_CS, selector->value, cpl);
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}
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else {
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BX_DEBUG(("Compatibility Mode Activated"));
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@ -1,5 +1,5 @@
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////////////////////////////////////////////////////////////////////////
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// $Id: iret.cc,v 1.17 2007-02-03 21:36:40 sshwarts Exp $
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// $Id: iret.cc,v 1.18 2007-03-14 21:15:15 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -45,8 +45,6 @@ BX_CPU_C::iret_protected(bxInstruction_c *i)
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Bit32u dword1, dword2;
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bx_descriptor_t cs_descriptor, ss_descriptor;
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BX_DEBUG(("IRET PROTECTED"));
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR msr.lma)
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{
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@ -603,7 +601,7 @@ BX_CPU_C::long_iret(bxInstruction_c *i)
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}
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else {
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// we are in 64-bit mode !
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loadSRegLMNominal(BX_SEG_REG_SS, raw_ss_selector, 0, cs_selector.rpl);
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loadSRegLMNominal(BX_SEG_REG_SS, raw_ss_selector, cs_selector.rpl);
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}
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if (StackAddrSize64()) RSP = new_rsp;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: protect_ctrl.cc,v 1.56 2007-01-28 21:27:31 sshwarts Exp $
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// $Id: protect_ctrl.cc,v 1.57 2007-03-14 21:15:15 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -438,7 +438,7 @@ void BX_CPU_C::LTR_Ew(bxInstruction_c *i)
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Bit32u dword3;
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access_linear(BX_CPU_THIS_PTR gdtr.base + selector.index*8 + 8, 4, 0, BX_READ, &dword3);
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descriptor.u.system.base |= ((Bit64u)dword3 << 32);
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BX_INFO(("64 bit TSS base = 0x%08x%08x",
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BX_DEBUG(("64 bit TSS base = 0x%08x%08x",
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GET32H(descriptor.u.system.base), GET32L(descriptor.u.system.base)));
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}
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#endif
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: segment_ctrl_pro.cc,v 1.68 2006-08-31 18:18:17 sshwarts Exp $
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// $Id: segment_ctrl_pro.cc,v 1.69 2007-03-14 21:15:15 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -246,14 +246,13 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
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}
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#if BX_SUPPORT_X86_64
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void BX_CPU_C::loadSRegLMNominal(unsigned segI, unsigned selector, bx_address base,
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unsigned dpl)
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void BX_CPU_C::loadSRegLMNominal(unsigned segI, unsigned selector, unsigned dpl)
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{
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bx_segment_reg_t *seg = & BX_CPU_THIS_PTR sregs[segI];
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// Load a segment register in long-mode with nominal values,
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// so descriptor cache values are compatible with existing checks.
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seg->cache.u.segment.base = base;
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seg->cache.u.segment.base = 0;
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// I doubt we need limit_scaled. If we do, it should be
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// of type bx_addr and be maxed to 64bits, not 32.
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seg->cache.u.segment.limit_scaled = 0xffffffff;
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@ -645,7 +644,7 @@ BX_CPU_C::load_ss(bx_selector_t *selector, bx_descriptor_t *descriptor, Bit8u cp
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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loadSRegLMNominal(BX_SEG_REG_SS, selector->value, 0, cpl);
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loadSRegLMNominal(BX_SEG_REG_SS, selector->value, cpl);
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return;
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}
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#endif
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: instrument.cc,v 1.15 2005-11-14 18:25:41 sshwarts Exp $
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// $Id: instrument.cc,v 1.16 2007-03-14 21:15:15 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -25,9 +25,10 @@
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include "bochs.h"
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#if BX_INSTRUMENTATION
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void bx_instr_init(unsigned cpu) {}
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void bx_instr_shutdown(unsigned cpu) {}
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void bx_instr_reset(unsigned cpu) {}
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@ -76,3 +77,5 @@ void bx_instr_phy_write(unsigned cpu, bx_address addr, unsigned len) {}
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void bx_instr_phy_read(unsigned cpu, bx_address addr, unsigned len) {}
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void bx_instr_wrmsr(unsigned cpu, unsigned addr, Bit64u value) {}
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#endif
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