Changes method of resolving opcode/attributes from group table
New method more flexible and easy to understanding. Reorganizing fetchdecode code and make it more easy and understandable
This commit is contained in:
Stanislav Shwartsman
parent
9c9b054ef9
commit
254ad17328
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: bochs.h,v 1.126 2003-08-25 16:46:18 vruppert Exp $
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// $Id: bochs.h,v 1.127 2003-08-28 19:25:23 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -232,16 +232,8 @@ int bx_begin_simulation (int argc, char *argv[]);
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# define BX_DBG_UCMEM_REPORT(addr, size, op, val)
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#endif // #if BX_DEBUGGER
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extern Bit8u DTPageDirty[];
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#if BX_DYNAMIC_TRANSLATION
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# define BX_DYN_DIRTY_PAGE(page) DTPageDirty[page] = 1;
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#else
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# define BX_DYN_DIRTY_PAGE(page)
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#endif
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#define MAGIC_LOGNUM 0x12345678
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typedef class BOCHSAPI logfunctions {
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char *prefix;
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int type;
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@ -429,12 +421,6 @@ int bx_gdbstub_check(unsigned int eip);
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# include "disasm/disasm.h"
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#endif
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#if BX_DYNAMIC_TRANSLATION
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# include "dynamic/dynamic.h"
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#endif
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typedef struct {
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bx_bool floppy;
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bx_bool keyboard;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.143 2003-08-17 18:55:16 sshwarts Exp $
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// $Id: cpu.h,v 1.144 2003-08-28 19:25:23 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1182,10 +1182,6 @@ class BX_MEM_C;
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#include "cpu/xmm.h"
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#endif
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#if BX_DYNAMIC_TRANSLATION
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typedef void (*BxDTShim_t)(void);
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#endif
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class BOCHSAPI BX_CPU_C : public logfunctions {
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public: // for now...
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@ -1236,30 +1232,8 @@ union {
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// each fetch/execute cycle.
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bx_address prev_eip;
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#endif
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// A few pointer to functions for use by the dynamic translation
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// code. Keep them close to the gen_reg declaration, so I can
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// use an 8bit offset to access them.
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#if BX_DYNAMIC_TRANSLATION
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BxDTShim_t DTWrite8vShim;
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BxDTShim_t DTWrite16vShim;
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BxDTShim_t DTWrite32vShim;
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BxDTShim_t DTRead8vShim;
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BxDTShim_t DTRead16vShim;
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BxDTShim_t DTRead32vShim;
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BxDTShim_t DTReadRMW8vShim;
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BxDTShim_t DTReadRMW16vShim;
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BxDTShim_t DTReadRMW32vShim;
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BxDTShim_t DTWriteRMW8vShim;
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BxDTShim_t DTWriteRMW16vShim;
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BxDTShim_t DTWriteRMW32vShim;
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BxDTShim_t DTSetFlagsOSZAPCPtr;
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BxDTShim_t DTIndBrHandler;
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BxDTShim_t DTDirBrHandler;
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#endif
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// status and control flags register set
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Bit32u lf_flags_status;
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Bit32u lf_flags_status;
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bx_flags_reg_t eflags;
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bx_lf_flags_entry oszapc;
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@ -3130,14 +3104,20 @@ IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
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#define BxImmediate_Iq 0x000A // 64 bit override
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#endif
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#define BxPrefix 0x0010 // bit 4
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#define BxAnother 0x0020 // bit 5
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#define BxSplitMod11b 0x0040 // bit 6
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#define BxPrefixSSE 0x0080 // bit 7
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#define BxLockable 0x0200 // bit 9
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#define BxRepeatable 0x0800 // bit 11 (pass through to metaInfo field)
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#define BxRepeatableZF 0x1000 // bit 12 (pass through to metaInfo field)
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#define BxGroupN 0x0100 // bits 8
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// Lookup for opcode and attributes in another opcode tables
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// Totally 7 opcode groups supported
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#define BxGroupX 0x0070 // bits 6..4: opcode groups definition
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#define BxGroupN 0x0010 // Group encoding: 001
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#define BxPrefixSSE 0x0020 // Group encoding: 010
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#define BxSplitMod11b 0x0030 // Group encoding: 011
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#define BxPrefix 0x0080 // bit 7
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#define BxAnother 0x0100 // bit 8
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#define BxLockable 0x0200 // bit 9
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#define BxRepeatable 0x0800 // bit 11 (pass through to metaInfo field)
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#define BxRepeatableZF 0x1000 // bit 12 (pass through to metaInfo field)
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#define BxGroup1 BxGroupN
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#define BxGroup2 BxGroupN
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#define BxGroup3 BxGroupN
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@ -3156,10 +3136,10 @@ IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
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#if BX_DEBUGGER
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typedef enum _show_flags {
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Flag_call = 0x1,
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Flag_ret = 0x2,
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Flag_int = 0x4,
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Flag_iret = 0x8,
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Flag_call = 0x1,
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Flag_ret = 0x2,
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Flag_int = 0x4,
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Flag_iret = 0x8,
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Flag_intsig = 0x10
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} show_flags_t;
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#endif
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.56 2003-08-15 13:08:23 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.57 2003-08-28 19:25:23 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -39,7 +39,6 @@
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///////////////////////////
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// sign extended to osize:
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// 6a push ib
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// 6b imul gvevib
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@ -64,7 +63,6 @@
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// maybe move 16bit only i's like MOV_EwSw, MOV_SwEw
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// to 32 bit modules.
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// use 0F as a prefix too?
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/* *********** */
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// LOCK PREFIX //
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@ -85,22 +83,6 @@
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void BxResolveError(bxInstruction_c *);
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#if BX_DYNAMIC_TRANSLATION
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// For 16-bit address mode, this matrix describes the registers
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// used to formulate the offset, indexed by the RM field.
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// This info is needed by the dynamic translation code for dataflow.
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static unsigned BxMemRegsUsed16[8] = {
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(1<<3) | (1<<6), // BX + SI
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(1<<3) | (1<<7), // BX + DI
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(1<<5) | (1<<6), // BP + SI
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(1<<5) | (1<<7), // BP + DI
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(1<<6), // SI
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(1<<7), // DI
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(1<<5), // BP
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(1<<3) // BX
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};
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#endif
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static BxExecutePtr_tR BxResolve16Mod0[8] = {
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&BX_CPU_C::Resolve16Mod0Rm0,
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&BX_CPU_C::Resolve16Mod0Rm1,
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@ -189,43 +171,43 @@ static BxOpcodeInfo_t opcodesADD_EdId[2] = {
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};
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static BxOpcodeInfo_t opcodesADD_GwEw[2] = {
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{ 0, &BX_CPU_C::ADD_GwEEw },
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{ 0, &BX_CPU_C::ADD_GwEGw }
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{ 0, &BX_CPU_C::ADD_GwEEw },
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{ 0, &BX_CPU_C::ADD_GwEGw }
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};
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static BxOpcodeInfo_t opcodesADD_GdEd[2] = {
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{ 0, &BX_CPU_C::ADD_GdEEd },
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{ 0, &BX_CPU_C::ADD_GdEGd }
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{ 0, &BX_CPU_C::ADD_GdEEd },
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{ 0, &BX_CPU_C::ADD_GdEGd }
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};
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static BxOpcodeInfo_t opcodesMOV_GbEb[2] = {
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{ 0, &BX_CPU_C::MOV_GbEEb },
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{ 0, &BX_CPU_C::MOV_GbEGb }
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{ 0, &BX_CPU_C::MOV_GbEEb },
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{ 0, &BX_CPU_C::MOV_GbEGb }
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};
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static BxOpcodeInfo_t opcodesMOV_GwEw[2] = {
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{ 0, &BX_CPU_C::MOV_GwEEw },
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{ 0, &BX_CPU_C::MOV_GwEGw }
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{ 0, &BX_CPU_C::MOV_GwEEw },
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{ 0, &BX_CPU_C::MOV_GwEGw }
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};
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static BxOpcodeInfo_t opcodesMOV_GdEd[2] = {
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{ 0, &BX_CPU_C::MOV_GdEEd },
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{ 0, &BX_CPU_C::MOV_GdEGd }
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{ 0, &BX_CPU_C::MOV_GdEEd },
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{ 0, &BX_CPU_C::MOV_GdEGd }
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};
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static BxOpcodeInfo_t opcodesMOV_EbGb[2] = {
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{ 0, &BX_CPU_C::MOV_EEbGb },
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{ 0, &BX_CPU_C::MOV_EGbGb }
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{ 0, &BX_CPU_C::MOV_EEbGb },
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{ 0, &BX_CPU_C::MOV_EGbGb }
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};
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static BxOpcodeInfo_t opcodesMOV_EwGw[2] = {
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{ 0, &BX_CPU_C::MOV_EEwGw },
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{ 0, &BX_CPU_C::MOV_EGwGw }
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{ 0, &BX_CPU_C::MOV_EEwGw },
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{ 0, &BX_CPU_C::MOV_EGwGw }
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};
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static BxOpcodeInfo_t opcodesMOV_EdGd[2] = {
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{ 0, &BX_CPU_C::MOV_EEdGd },
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{ 0, &BX_CPU_C::MOV_EGdGd }
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{ 0, &BX_CPU_C::MOV_EEdGd },
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{ 0, &BX_CPU_C::MOV_EGdGd }
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};
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@ -1549,9 +1531,6 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 0F FF */ { 0, &BX_CPU_C::BxError }
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};
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unsigned
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BX_CPU_C::fetchDecode(Bit8u *iptr, bxInstruction_c *instruction,
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unsigned remain)
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@ -1563,6 +1542,7 @@ BX_CPU_C::fetchDecode(Bit8u *iptr, bxInstruction_c *instruction,
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unsigned imm_mode, offset;
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unsigned rm, mod=0, nnn=0;
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unsigned sse_prefix;
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#define SSE_PREFIX_NONE 0
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#define SSE_PREFIX_66 1
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#define SSE_PREFIX_F2 2
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@ -1589,29 +1569,7 @@ another_byte:
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attr = BxOpcodeInfo[b1+offset].Attr;
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instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
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if ( !(attr & BxAnother) ) {
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// Opcode does not require a MODRM byte.
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// Note that a 2-byte opcode (0F XX) will jump to before
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// the if() above after fetching the 2nd byte, so this path is
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// taken in all cases if a modrm byte is NOT required.
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instruction->execute = BxOpcodeInfo[b1+offset].ExecutePtr;
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instruction->IxForm.opcodeReg = b1 & 7;
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#if BX_DYNAMIC_TRANSLATION
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instruction->DTAttr = BxDTOpcodeInfo[b1+offset].DTAttr;
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instruction->DTFPtr = BxDTOpcodeInfo[b1+offset].DTASFPtr;
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#endif
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// Simple instruction, nothing left to do.
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if (attr == 0) {
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if (lock) {
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BX_INFO(("LOCK prefix unallowed (op1=0x%x, attr=0x%x, mod=0x%x, nnn=%u)", b1, attr, mod, nnn));
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UndefinedOpcode(instruction);
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}
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instruction->setB1(b1);
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instruction->setILen(ilen);
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return(1);
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}
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}
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else {
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if (attr & BxAnother) {
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if (attr & BxPrefix) {
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switch (b1) {
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case 0x66: // OpSize
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@ -1713,10 +1671,11 @@ another_byte:
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return(0);
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default:
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BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1));
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BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1));
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return(0);
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}
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}
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// opcode requires another byte
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if (ilen < remain) {
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ilen++;
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@ -1747,14 +1706,8 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1));
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if (instruction->as32L()) {
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// 32-bit addressing modes; note that mod==11b handled above
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if (rm != 4) { // no s-i-b byte
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#if BX_DYNAMIC_TRANSLATION
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instruction->DTMemRegsUsed = 1<<rm; // except for mod=00b rm=100b
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#endif
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if (mod == 0x00) { // mod == 00b
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instruction->ResolveModrm = BxResolve32Mod0[rm];
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#if BX_DYNAMIC_TRANSLATION
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instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0[rm];
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#endif
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_SEG_REG_DS);
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if (rm == 5) {
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@ -1762,9 +1715,6 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1));
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instruction->modRMForm.displ32u = FetchDWORD(iptr);
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iptr += 4;
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ilen += 4;
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#if BX_DYNAMIC_TRANSLATION
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instruction->DTMemRegsUsed = 0;
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#endif
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goto modrm_done;
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}
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else return(0);
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@ -1774,9 +1724,6 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1));
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}
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if (mod == 0x40) { // mod == 01b
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instruction->ResolveModrm = BxResolve32Mod1or2[rm];
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#if BX_DYNAMIC_TRANSLATION
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instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm];
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#endif
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01_rm32[rm]);
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get_8bit_displ:
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@ -1790,9 +1737,6 @@ get_8bit_displ:
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}
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// (mod == 0x80) mod == 10b
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instruction->ResolveModrm = BxResolve32Mod1or2[rm];
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#if BX_DYNAMIC_TRANSLATION
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instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm];
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#endif
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod10_rm32[rm]);
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get_32bit_displ:
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@ -1819,46 +1763,23 @@ get_32bit_displ:
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instruction->modRMForm.modRMData |= (base<<12);
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instruction->modRMForm.modRMData |= (index<<16);
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instruction->modRMForm.modRMData |= (scale<<4);
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#if BX_DYNAMIC_TRANSLATION
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if (index == 0x04) // 100b
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instruction->DTMemRegsUsed = 0;
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else
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instruction->DTMemRegsUsed = 1<<index;
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#endif
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if (mod == 0x00) { // mod==00b, rm==4
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instruction->ResolveModrm = BxResolve32Mod0Base[base];
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#if BX_DYNAMIC_TRANSLATION
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instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0Base[base];
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#endif
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod0_base32[base]);
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if (base == 0x05) {
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if (base == 0x05)
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goto get_32bit_displ;
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}
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// mod==00b, rm==4, base!=5
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#if BX_DYNAMIC_TRANSLATION
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instruction->DTMemRegsUsed |= 1<<base;
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#endif
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goto modrm_done;
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}
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#if BX_DYNAMIC_TRANSLATION
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// for remaining 32bit cases
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instruction->DTMemRegsUsed |= 1<<base;
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#endif
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if (mod == 0x40) { // mod==01b, rm==4
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instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
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#if BX_DYNAMIC_TRANSLATION
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instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base];
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#endif
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
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goto get_8bit_displ;
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}
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// (mod == 0x80), mod==10b, rm==4
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instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
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#if BX_DYNAMIC_TRANSLATION
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instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base];
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#endif
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
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goto get_32bit_displ;
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@ -1868,14 +1789,8 @@ get_32bit_displ:
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// 16-bit addressing modes, mod==11b handled above
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if (mod == 0x40) { // mod == 01b
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instruction->ResolveModrm = BxResolve16Mod1or2[rm];
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#if BX_DYNAMIC_TRANSLATION
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instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve16Mod1or2[rm];
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#endif
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if (BX_NULL_SEG_REG(instruction->seg()))
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instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01_rm16[rm]);
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#if BX_DYNAMIC_TRANSLATION
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instruction->DTMemRegsUsed = BxMemRegsUsed16[rm];
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#endif
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if (ilen < remain) {
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// 8 sign extended to 16
|
||||
instruction->modRMForm.displ16u = (Bit8s) *iptr++;
|
||||
@ -1886,14 +1801,8 @@ get_32bit_displ:
|
||||
}
|
||||
if (mod == 0x80) { // mod == 10b
|
||||
instruction->ResolveModrm = BxResolve16Mod1or2[rm];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve16Mod1or2[rm];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod10_rm16[rm]);
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTMemRegsUsed = BxMemRegsUsed16[rm];
|
||||
#endif
|
||||
if ((ilen+1) < remain) {
|
||||
instruction->modRMForm.displ16u = FetchWORD(iptr);
|
||||
iptr += 2;
|
||||
@ -1904,9 +1813,6 @@ get_32bit_displ:
|
||||
}
|
||||
// mod must be 00b at this point
|
||||
instruction->ResolveModrm = BxResolve16Mod0[rm];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve16Mod0[rm];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod00_rm16[rm]);
|
||||
if (rm == 0x06) {
|
||||
@ -1919,76 +1825,59 @@ get_32bit_displ:
|
||||
else return(0);
|
||||
}
|
||||
// mod=00b rm!=6
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTMemRegsUsed = BxMemRegsUsed16[rm];
|
||||
#endif
|
||||
}
|
||||
|
||||
modrm_done:
|
||||
if (attr & BxGroupN) {
|
||||
BxOpcodeInfo_t *OpcodeInfoPtr = BxOpcodeInfo[b1+offset].AnotherArray;
|
||||
// get additional attributes from group table
|
||||
attr |= OpcodeInfoPtr[nnn].Attr;
|
||||
instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTAttr = 0; // for now
|
||||
#endif
|
||||
/* For SSE opcodes, look into another 4 entries table
|
||||
with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3 */
|
||||
if (attr & BxPrefixSSE) {
|
||||
int op = sse_prefix_index[sse_prefix];
|
||||
if(op < 0) BX_PANIC(("fetchdecode: SSE opcode with two or more prefixes"));
|
||||
else {
|
||||
OpcodeInfoPtr = OpcodeInfoPtr[nnn].AnotherArray;
|
||||
instruction->execute = OpcodeInfoPtr[op].ExecutePtr;
|
||||
attr |= OpcodeInfoPtr[op].Attr;
|
||||
}
|
||||
}
|
||||
// For high frequency opcodes, two variants of the instruction are
|
||||
// implemented; one for the mod=11b case (Reg-Reg), and one for
|
||||
// the other cases (Reg-Mem). If this is one of those cases,
|
||||
// we need to dereference to get to the execute pointer.
|
||||
else { // ! BxPrefixSSE
|
||||
if (attr & BxSplitMod11b) {
|
||||
OpcodeInfoPtr = OpcodeInfoPtr[nnn].AnotherArray;
|
||||
instruction->execute = OpcodeInfoPtr[mod==0xc0].ExecutePtr;
|
||||
attr |= OpcodeInfoPtr[mod==0xc0].Attr;
|
||||
}
|
||||
else {
|
||||
instruction->execute = OpcodeInfoPtr[nnn].ExecutePtr;
|
||||
attr |= OpcodeInfoPtr[nnn].Attr;
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTAttr = BxDTOpcodeInfo[b1+offset].DTAttr;
|
||||
instruction->DTFPtr = BxDTOpcodeInfo[b1+offset].DTASFPtr;
|
||||
#endif
|
||||
/* For SSE opcodes, look into another 4 entries table
|
||||
with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3 */
|
||||
if (attr & BxPrefixSSE) {
|
||||
int op = sse_prefix_index[sse_prefix];
|
||||
if(op < 0) BX_PANIC(("fetchdecode: SSE opcode with two or more prefixes"));
|
||||
else {
|
||||
BxOpcodeInfo_t *OpcodeInfoPtr = BxOpcodeInfo[b1+offset].AnotherArray;
|
||||
instruction->execute = OpcodeInfoPtr[op].ExecutePtr;
|
||||
attr |= OpcodeInfoPtr[op].Attr;
|
||||
}
|
||||
}
|
||||
// (See note immediately above for comment)
|
||||
else {
|
||||
if (attr & BxSplitMod11b) {
|
||||
BxOpcodeInfo_t *OpcodeInfoPtr = BxOpcodeInfo[b1+offset].AnotherArray;
|
||||
instruction->execute = OpcodeInfoPtr[mod==0xc0].ExecutePtr;
|
||||
attr |= OpcodeInfoPtr[mod==0xc0].Attr;
|
||||
}
|
||||
else {
|
||||
instruction->execute = BxOpcodeInfo[b1+offset].ExecutePtr;
|
||||
attr |= BxOpcodeInfo[b1+offset].Attr;
|
||||
}
|
||||
}
|
||||
|
||||
// Resolve ExecutePtr and additional opcode Attr
|
||||
BxOpcodeInfo_t *OpcodeInfoPtr = &(BxOpcodeInfo[b1+offset]);
|
||||
while(attr & BxGroupX)
|
||||
{
|
||||
Bit32u Group = attr & BxGroupX;
|
||||
attr &= ~BxGroupX;
|
||||
|
||||
switch(Group) {
|
||||
case BxGroupN:
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn]);
|
||||
break;
|
||||
case BxPrefixSSE:
|
||||
{
|
||||
/* For SSE opcodes, look into another 4 entries table
|
||||
with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3) */
|
||||
int op = sse_prefix_index[sse_prefix];
|
||||
if (op < 0) {
|
||||
BX_INFO(("fetchdecode: SSE opcode with two or more prefixes"));
|
||||
UndefinedOpcode(instruction);
|
||||
}
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[op]);
|
||||
break;
|
||||
}
|
||||
case BxSplitMod11b:
|
||||
/* For high frequency opcodes, two variants of the instruction are
|
||||
* implemented; one for the mod=11b case (Reg-Reg), and one for
|
||||
* the other cases (Reg-Mem). If this is one of those cases,
|
||||
* we need to dereference to get to the execute pointer.
|
||||
*/
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[mod==0xc0]);
|
||||
break;
|
||||
default:
|
||||
BX_PANIC(("fetchdecode: Unknown opcode group"));
|
||||
}
|
||||
|
||||
/* get additional attributes from group table */
|
||||
attr |= OpcodeInfoPtr->Attr;
|
||||
}
|
||||
|
||||
instruction->execute = OpcodeInfoPtr->ExecutePtr;
|
||||
instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
|
||||
}
|
||||
else {
|
||||
// Opcode does not require a MODRM byte.
|
||||
// Note that a 2-byte opcode (0F XX) will jump to before
|
||||
// the if() above after fetching the 2nd byte, so this path is
|
||||
// taken in all cases if a modrm byte is NOT required.
|
||||
instruction->execute = BxOpcodeInfo[b1+offset].ExecutePtr;
|
||||
instruction->IxForm.opcodeReg = b1 & 7;
|
||||
}
|
||||
|
||||
if (lock) { // lock prefix invalid opcode
|
||||
@ -2000,7 +1889,6 @@ modrm_done:
|
||||
}
|
||||
|
||||
imm_mode = attr & BxImmediate;
|
||||
|
||||
if (imm_mode) {
|
||||
switch (imm_mode) {
|
||||
case BxImmediate_Ib:
|
||||
@ -2113,7 +2001,7 @@ modrm_done:
|
||||
}
|
||||
break;
|
||||
default:
|
||||
BX_INFO(("b1 was %x", b1));
|
||||
BX_INFO(("b1 was %x", b1));
|
||||
BX_PANIC(("fetchdecode: imm_mode = %u", imm_mode));
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: fetchdecode64.cc,v 1.54 2003-08-15 13:17:16 sshwarts Exp $
|
||||
// $Id: fetchdecode64.cc,v 1.55 2003-08-28 19:25:23 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -85,22 +85,6 @@
|
||||
|
||||
void BxResolveError(bxInstruction_c *);
|
||||
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
// For 16-bit address mode, this matrix describes the registers
|
||||
// used to formulate the offset, indexed by the RM field.
|
||||
// This info is needed by the dynamic translation code for dataflow.
|
||||
static unsigned BxMemRegsUsed16[8] = {
|
||||
(1<<3) | (1<<6), // BX + SI
|
||||
(1<<3) | (1<<7), // BX + DI
|
||||
(1<<5) | (1<<6), // BP + SI
|
||||
(1<<5) | (1<<7), // BP + DI
|
||||
(1<<6), // SI
|
||||
(1<<7), // DI
|
||||
(1<<5), // BP
|
||||
(1<<3) // BX
|
||||
};
|
||||
#endif
|
||||
|
||||
static BxExecutePtr_tR BxResolve32Mod0[8] = {
|
||||
&BX_CPU_C::Resolve32Mod0Rm0,
|
||||
&BX_CPU_C::Resolve32Mod0Rm1,
|
||||
@ -243,43 +227,43 @@ static BxOpcodeInfo_t opcodesADD_EdId[2] = {
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t opcodesADD_GwEw[2] = {
|
||||
{ 0, &BX_CPU_C::ADD_GwEEw },
|
||||
{ 0, &BX_CPU_C::ADD_GwEGw }
|
||||
{ 0, &BX_CPU_C::ADD_GwEEw },
|
||||
{ 0, &BX_CPU_C::ADD_GwEGw }
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t opcodesADD_GdEd[2] = {
|
||||
{ 0, &BX_CPU_C::ADD_GdEEd },
|
||||
{ 0, &BX_CPU_C::ADD_GdEGd }
|
||||
{ 0, &BX_CPU_C::ADD_GdEEd },
|
||||
{ 0, &BX_CPU_C::ADD_GdEGd }
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t opcodesMOV_GbEb[2] = {
|
||||
{ 0, &BX_CPU_C::MOV_GbEEb },
|
||||
{ 0, &BX_CPU_C::MOV_GbEGb }
|
||||
{ 0, &BX_CPU_C::MOV_GbEEb },
|
||||
{ 0, &BX_CPU_C::MOV_GbEGb }
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t opcodesMOV_GwEw[2] = {
|
||||
{ 0, &BX_CPU_C::MOV_GwEEw },
|
||||
{ 0, &BX_CPU_C::MOV_GwEGw }
|
||||
{ 0, &BX_CPU_C::MOV_GwEEw },
|
||||
{ 0, &BX_CPU_C::MOV_GwEGw }
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t opcodesMOV_GdEd[2] = {
|
||||
{ 0, &BX_CPU_C::MOV_GdEEd },
|
||||
{ 0, &BX_CPU_C::MOV_GdEGd }
|
||||
{ 0, &BX_CPU_C::MOV_GdEEd },
|
||||
{ 0, &BX_CPU_C::MOV_GdEGd }
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t opcodesMOV_EbGb[2] = {
|
||||
{ 0, &BX_CPU_C::MOV_EEbGb },
|
||||
{ 0, &BX_CPU_C::MOV_EGbGb }
|
||||
{ 0, &BX_CPU_C::MOV_EEbGb },
|
||||
{ 0, &BX_CPU_C::MOV_EGbGb }
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t opcodesMOV_EwGw[2] = {
|
||||
{ 0, &BX_CPU_C::MOV_EEwGw },
|
||||
{ 0, &BX_CPU_C::MOV_EGwGw }
|
||||
{ 0, &BX_CPU_C::MOV_EEwGw },
|
||||
{ 0, &BX_CPU_C::MOV_EGwGw }
|
||||
};
|
||||
|
||||
static BxOpcodeInfo_t opcodesMOV_EdGd[2] = {
|
||||
{ 0, &BX_CPU_C::MOV_EEdGd },
|
||||
{ 0, &BX_CPU_C::MOV_EGdGd }
|
||||
{ 0, &BX_CPU_C::MOV_EEdGd },
|
||||
{ 0, &BX_CPU_C::MOV_EGdGd }
|
||||
};
|
||||
|
||||
|
||||
@ -2379,14 +2363,8 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1));
|
||||
if (instruction->as64L()) {
|
||||
// 64-bit addressing modes; note that mod==11b handled above
|
||||
if (rm != 4) { // no s-i-b byte
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTMemRegsUsed = 1<<rm; // except for mod=00b rm=100b
|
||||
#endif
|
||||
if (mod == 0x00) { // mod == 00b
|
||||
instruction->ResolveModrm = BxResolve64Mod0[rm];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0[rm];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_SEG_REG_DS);
|
||||
ExtendedFieldCheck((rm&8) && ((rm&7)==5)); // KPL
|
||||
@ -2395,9 +2373,6 @@ ExtendedFieldCheck((rm&8) && ((rm&7)==5)); // KPL
|
||||
instruction->modRMForm.displ32u = FetchDWORD(iptr);
|
||||
iptr += 4;
|
||||
ilen += 4;
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTMemRegsUsed = 0;
|
||||
#endif
|
||||
goto modrm_done;
|
||||
}
|
||||
else return(0);
|
||||
@ -2407,9 +2382,6 @@ ExtendedFieldCheck((rm&8) && ((rm&7)==5)); // KPL
|
||||
}
|
||||
if (mod == 0x40) { // mod == 01b
|
||||
instruction->ResolveModrm = BxResolve64Mod1or2[rm];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01_rm32[rm]);
|
||||
get_8bit_displ_1:
|
||||
@ -2423,9 +2395,6 @@ get_8bit_displ_1:
|
||||
}
|
||||
// (mod == 0x80) mod == 10b
|
||||
instruction->ResolveModrm = BxResolve64Mod1or2[rm];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod10_rm32[rm]);
|
||||
get_32bit_displ_1:
|
||||
@ -2452,47 +2421,24 @@ get_32bit_displ_1:
|
||||
instruction->modRMForm.modRMData |= (base<<12);
|
||||
instruction->modRMForm.modRMData |= (index<<16);
|
||||
instruction->modRMForm.modRMData |= (scale<<4);
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
if (instruction->modRMForm.index == 0x04) // 100b
|
||||
instruction->DTMemRegsUsed = 0;
|
||||
else
|
||||
instruction->DTMemRegsUsed = 1<<instruction->modRMForm.index;
|
||||
#endif
|
||||
if (mod == 0x00) { // mod==00b, rm==4
|
||||
instruction->ResolveModrm = BxResolve64Mod0Base[base];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0Base[base];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod0_base32[base]);
|
||||
ExtendedFieldCheck((base&8) && ((base&7)==5)); // KPL
|
||||
if (base == 0x05) {
|
||||
if (base == 0x05)
|
||||
goto get_32bit_displ_1;
|
||||
}
|
||||
// mod==00b, rm==4, base!=5
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTMemRegsUsed |= 1<<base;
|
||||
#endif
|
||||
goto modrm_done;
|
||||
}
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
// for remaining 32bit cases
|
||||
instruction->DTMemRegsUsed |= 1<<base;
|
||||
#endif
|
||||
if (mod == 0x40) { // mod==01b, rm==4
|
||||
instruction->ResolveModrm = BxResolve64Mod1or2Base[base];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
|
||||
goto get_8bit_displ_1;
|
||||
}
|
||||
// (mod == 0x80), mod==10b, rm==4
|
||||
instruction->ResolveModrm = BxResolve64Mod1or2Base[base];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
|
||||
goto get_32bit_displ_1;
|
||||
@ -2501,15 +2447,9 @@ ExtendedFieldCheck((base&8) && ((base&7)==5)); // KPL
|
||||
else {
|
||||
// 32-bit addressing modes; note that mod==11b handled above
|
||||
if (rm != 4) { // no s-i-b byte
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTMemRegsUsed = 1<<rm; // except for mod=00b rm=100b
|
||||
#endif
|
||||
if (mod == 0x00) { // mod == 00b
|
||||
ExtendedFieldCheck(rm&8); // KPL
|
||||
instruction->ResolveModrm = BxResolve32Mod0[rm];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0[rm];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_SEG_REG_DS);
|
||||
ExtendedFieldCheck((rm&8) && ((rm&7)==5)); // KPL
|
||||
@ -2518,9 +2458,6 @@ ExtendedFieldCheck((rm&8) && ((rm&7)==5)); // KPL
|
||||
instruction->modRMForm.displ32u = FetchDWORD(iptr);
|
||||
iptr += 4;
|
||||
ilen += 4;
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTMemRegsUsed = 0;
|
||||
#endif
|
||||
goto modrm_done;
|
||||
}
|
||||
else return(0);
|
||||
@ -2531,9 +2468,6 @@ ExtendedFieldCheck((rm&8) && ((rm&7)==5)); // KPL
|
||||
if (mod == 0x40) { // mod == 01b
|
||||
ExtendedFieldCheck(rm&8); // KPL
|
||||
instruction->ResolveModrm = BxResolve32Mod1or2[rm];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01_rm32[rm]);
|
||||
get_8bit_displ:
|
||||
@ -2548,9 +2482,6 @@ get_8bit_displ:
|
||||
// (mod == 0x80) mod == 10b
|
||||
ExtendedFieldCheck(rm&8); // KPL
|
||||
instruction->ResolveModrm = BxResolve32Mod1or2[rm];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod10_rm32[rm]);
|
||||
get_32bit_displ:
|
||||
@ -2577,40 +2508,20 @@ get_32bit_displ:
|
||||
instruction->modRMForm.modRMData |= (base<<12);
|
||||
instruction->modRMForm.modRMData |= (index<<16);
|
||||
instruction->modRMForm.modRMData |= (scale<<4);
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
if (instruction->modRMForm.index == 0x04) // 100b
|
||||
instruction->DTMemRegsUsed = 0;
|
||||
else
|
||||
instruction->DTMemRegsUsed = 1<<instruction->modRMForm.index;
|
||||
#endif
|
||||
if (mod == 0x00) { // mod==00b, rm==4
|
||||
ExtendedFieldCheck(base&8); // KPL
|
||||
instruction->ResolveModrm = BxResolve32Mod0Base[base];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0Base[base];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod0_base32[base]);
|
||||
ExtendedFieldCheck((base&8) && ((base&7)==5)); // KPL
|
||||
if (base == 0x05) {
|
||||
if (base == 0x05)
|
||||
goto get_32bit_displ;
|
||||
}
|
||||
// mod==00b, rm==4, base!=5
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTMemRegsUsed |= 1<<base;
|
||||
#endif
|
||||
goto modrm_done;
|
||||
}
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
// for remaining 32bit cases
|
||||
instruction->DTMemRegsUsed |= 1<<base;
|
||||
#endif
|
||||
if (mod == 0x40) { // mod==01b, rm==4
|
||||
ExtendedFieldCheck(base&8); // KPL
|
||||
instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
|
||||
goto get_8bit_displ;
|
||||
@ -2618,9 +2529,6 @@ ExtendedFieldCheck(base&8); // KPL
|
||||
// (mod == 0x80), mod==10b, rm==4
|
||||
ExtendedFieldCheck(base&8); // KPL
|
||||
instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base];
|
||||
#endif
|
||||
if (BX_NULL_SEG_REG(instruction->seg()))
|
||||
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
|
||||
goto get_32bit_displ;
|
||||
@ -2628,6 +2536,7 @@ ExtendedFieldCheck(base&8); // KPL
|
||||
}
|
||||
|
||||
modrm_done:
|
||||
|
||||
/*
|
||||
BX_DEBUG (("as_64=%d os_64=%d as_32=%d os_32=%d b1=%04x b2=%04x ofs=%4d rm=%d mod=%d nnn=%d",
|
||||
instruction->as64L(),
|
||||
@ -2640,69 +2549,48 @@ modrm_done:
|
||||
nnn
|
||||
));
|
||||
*/
|
||||
if (attr & BxGroupN) {
|
||||
BxOpcodeInfo_t *OpcodeInfoPtr = BxOpcodeInfo64[b1+offset].AnotherArray;
|
||||
ExtendedFieldCheck(nnn&8); // KPL
|
||||
// get additional attributes from group table
|
||||
attr |= OpcodeInfoPtr[nnn].Attr;
|
||||
instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTAttr = 0; // for now
|
||||
#endif
|
||||
/* For SSE opcodes, look into another 4 entries table
|
||||
with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3 */
|
||||
if (attr & BxPrefixSSE) {
|
||||
int op = sse_prefix_index[sse_prefix];
|
||||
if(op < 0) BX_PANIC(("fetchdecode: SSE opcode with two or more prefixes"));
|
||||
else {
|
||||
OpcodeInfoPtr = OpcodeInfoPtr[nnn].AnotherArray;
|
||||
instruction->execute = OpcodeInfoPtr[op].ExecutePtr;
|
||||
attr |= OpcodeInfoPtr[op].Attr;
|
||||
}
|
||||
}
|
||||
// For high frequency opcodes, two variants of the instruction are
|
||||
// implemented; one for the mod=11b case (Reg-Reg), and one for
|
||||
// the other cases (Reg-Mem). If this is one of those cases,
|
||||
// we need to dereference to get to the execute pointer.
|
||||
else {
|
||||
if (attr & BxSplitMod11b) {
|
||||
OpcodeInfoPtr = OpcodeInfoPtr[nnn].AnotherArray;
|
||||
instruction->execute = OpcodeInfoPtr[mod==0xc0].ExecutePtr;
|
||||
attr |= OpcodeInfoPtr[mod==0xc0].Attr;
|
||||
}
|
||||
else {
|
||||
instruction->execute = OpcodeInfoPtr[nnn].ExecutePtr;
|
||||
attr |= OpcodeInfoPtr[nnn].Attr;
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTAttr = BxDTOpcodeInfo[b1+offset].DTAttr;
|
||||
instruction->DTFPtr = BxDTOpcodeInfo[b1+offset].DTASFPtr;
|
||||
#endif
|
||||
if (attr & BxPrefixSSE) {
|
||||
int op = sse_prefix_index[sse_prefix];
|
||||
if(op < 0) BX_PANIC(("fetchdecode: SSE opcode with two or more prefixes"));
|
||||
else {
|
||||
BxOpcodeInfo_t *OpcodeInfoPtr = BxOpcodeInfo64[b1+offset].AnotherArray;
|
||||
instruction->execute = OpcodeInfoPtr[op].ExecutePtr;
|
||||
attr |= OpcodeInfoPtr[op].Attr;
|
||||
}
|
||||
}
|
||||
// (See note immediately above for comment)
|
||||
else {
|
||||
if (attr & BxSplitMod11b) {
|
||||
BxOpcodeInfo_t *OpcodeInfoPtr = BxOpcodeInfo64[b1+offset].AnotherArray;
|
||||
instruction->execute = OpcodeInfoPtr[mod==0xc0].ExecutePtr;
|
||||
attr |= OpcodeInfoPtr[mod==0xc0].Attr;
|
||||
}
|
||||
else {
|
||||
instruction->execute = BxOpcodeInfo64[b1+offset].ExecutePtr;
|
||||
attr |= BxOpcodeInfo64[b1+offset].Attr;
|
||||
}
|
||||
}
|
||||
|
||||
// Resolve ExecutePtr and additional opcode Attr
|
||||
BxOpcodeInfo_t *OpcodeInfoPtr = &(BxOpcodeInfo64[b1+offset]);
|
||||
while(attr & BxGroupX)
|
||||
{
|
||||
Bit32u Group = attr & BxGroupX;
|
||||
attr &= ~BxGroupX;
|
||||
|
||||
switch(Group) {
|
||||
case BxGroupN:
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn]);
|
||||
break;
|
||||
case BxPrefixSSE:
|
||||
{
|
||||
/* For SSE opcodes, look into another 4 entries table
|
||||
with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3) */
|
||||
int op = sse_prefix_index[sse_prefix];
|
||||
if (op < 0) {
|
||||
BX_INFO(("fetchdecode: SSE opcode with two or more prefixes"));
|
||||
UndefinedOpcode(instruction);
|
||||
}
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[op]);
|
||||
break;
|
||||
}
|
||||
case BxSplitMod11b:
|
||||
/* For high frequency opcodes, two variants of the instruction are
|
||||
* implemented; one for the mod=11b case (Reg-Reg), and one for
|
||||
* the other cases (Reg-Mem). If this is one of those cases,
|
||||
* we need to dereference to get to the execute pointer.
|
||||
*/
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[mod==0xc0]);
|
||||
break;
|
||||
default:
|
||||
BX_PANIC(("fetchdecode: Unknown opcode group"));
|
||||
}
|
||||
|
||||
/* get additional attributes from group table */
|
||||
attr |= OpcodeInfoPtr->Attr;
|
||||
}
|
||||
|
||||
instruction->execute = OpcodeInfoPtr->ExecutePtr;
|
||||
instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
|
||||
}
|
||||
else {
|
||||
// Opcode does not require a MODRM byte.
|
||||
@ -2711,10 +2599,6 @@ ExtendedFieldCheck(nnn&8); // KPL
|
||||
// taken in all cases if a modrm byte is NOT required.
|
||||
instruction->execute = BxOpcodeInfo64[b1+offset].ExecutePtr;
|
||||
instruction->IxForm.opcodeReg = (b1 & 7) | rex_b;
|
||||
#if BX_DYNAMIC_TRANSLATION
|
||||
instruction->DTAttr = BxDTOpcodeInfo[b1+offset].DTAttr;
|
||||
instruction->DTFPtr = BxDTOpcodeInfo[b1+offset].DTASFPtr;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (lock) { // lock prefix invalid opcode
|
||||
@ -2726,7 +2610,6 @@ ExtendedFieldCheck(nnn&8); // KPL
|
||||
}
|
||||
|
||||
imm_mode = attr & BxImmediate;
|
||||
|
||||
if (imm_mode) {
|
||||
switch (imm_mode) {
|
||||
case BxImmediate_Ib:
|
||||
@ -2851,7 +2734,7 @@ ExtendedFieldCheck(nnn&8); // KPL
|
||||
}
|
||||
break;
|
||||
default:
|
||||
BX_INFO(("b1 was %x", b1));
|
||||
BX_INFO(("b1 was %x", b1));
|
||||
BX_PANIC(("fetchdecode: imm_mode = %u", imm_mode));
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*---------------------------------------------------------------------------+
|
||||
| errors.c |
|
||||
| $Id: errors.c,v 1.10 2003-08-07 18:54:03 sshwarts Exp $
|
||||
| $Id: errors.c,v 1.11 2003-08-28 19:25:23 sshwarts Exp $
|
||||
| |
|
||||
| The error handling functions for wm-FPU-emu |
|
||||
| |
|
||||
@ -29,6 +29,8 @@
|
||||
#include "reg_constant.h"
|
||||
#include "version.h"
|
||||
|
||||
int printk(const char * fmt, ...);
|
||||
|
||||
/* */
|
||||
#undef PRINT_MESSAGES
|
||||
/* */
|
||||
@ -42,7 +44,6 @@ void FPU_illegal(void)
|
||||
math_abort(NULL, SIGILL);
|
||||
}
|
||||
|
||||
|
||||
#ifndef USE_WITH_CPU_SIM
|
||||
void FPU_printall(void)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user