SSE4 support
This commit is contained in:
Stanislav Shwartsman
parent
f6af99dead
commit
5189cfbf10
@ -20,6 +20,7 @@
|
||||
--enable-mmx \
|
||||
--enable-fpu \
|
||||
--enable-sse=4 \
|
||||
--enable-sse-extension \
|
||||
--enable-vme \
|
||||
--enable-sep \
|
||||
--enable-3dnow \
|
||||
|
||||
@ -2,6 +2,7 @@ Changes in 2.3.5 release (coming soon):
|
||||
|
||||
- CPU
|
||||
- Fixed critical bug with 0x90 opcode (NOP) handling in x86-64 mode
|
||||
- added emulation of SSE4 instructions (Stanislav)
|
||||
- Do not save and restore XMM8-XMM15 registers when not in x86-64 mode
|
||||
- Fixed zero upper 32-bit part of GPR in x86-64 mode
|
||||
- CMOV_GdEd should zero upper 32-bit part of GPR register even if the
|
||||
@ -17,8 +18,11 @@ Changes in 2.3.5 release (coming soon):
|
||||
- Configure and compile
|
||||
- several fixes for MacOSX, OpenBSD and Solaris 10
|
||||
- enable save/restore feature by default for all configurations
|
||||
- rename SSE4 option to match Intel(R) Programming Reference Manual,
|
||||
to enable Intel Core Duo 2 new instructions use --enable-sse3e
|
||||
- reorganized SSE configure options to match Intel(R) Programming
|
||||
Reference Manual, new option introduced for SSE extensions enabling.
|
||||
To enable Intel Core Duo 2 new instructions use
|
||||
--enable-sse=3 --enable-sse-extension
|
||||
enabling of SSE4 (--enable-sse=4) will enable SSE3 exensions as well
|
||||
- removed old PIT, always use new PIT written by Greg Alexander,
|
||||
removed configure option --enable-new-pit
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: bochs.h,v 1.206 2007-03-06 21:12:19 sshwarts Exp $
|
||||
// $Id: bochs.h,v 1.207 2007-04-19 16:12:12 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2002 MandrakeSoft S.A.
|
||||
@ -77,11 +77,7 @@ extern "C" {
|
||||
#endif
|
||||
#include <time.h>
|
||||
#if BX_WITH_MACOS
|
||||
#define Float32 KLUDGE_Float32
|
||||
#define Float64 KLUDGE_Float64
|
||||
# include <types.h>
|
||||
#undef Float32
|
||||
#undef Float64
|
||||
# include <stat.h>
|
||||
# include <cstdio>
|
||||
# include <unistd.h>
|
||||
|
||||
@ -734,7 +734,7 @@ typedef
|
||||
#define BX_SUPPORT_MMX 0
|
||||
#define BX_SUPPORT_3DNOW 0
|
||||
#define BX_SUPPORT_SSE 0
|
||||
#define BX_SUPPORT_SSE3E 0
|
||||
#define BX_SUPPORT_SSE_EXTENSION 0
|
||||
#define BX_SUPPORT_DAZ 0
|
||||
#define BX_SUPPORT_SEP 0
|
||||
#define BX_SUPPORT_VME 0
|
||||
@ -833,14 +833,6 @@ typedef
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (BX_SUPPORT_SSE3E && BX_SUPPORT_SSE < 3)
|
||||
#error "SSE3E requires SSE3 support !"
|
||||
#endif
|
||||
|
||||
#if (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE3E == 0)
|
||||
#error "SSE4 requires SSE3E support !"
|
||||
#endif
|
||||
|
||||
#define BX_HAVE_GETENV 0
|
||||
#define BX_HAVE_SETENV 0
|
||||
#define BX_HAVE_SELECT 0
|
||||
|
||||
43
bochs/configure
vendored
43
bochs/configure
vendored
@ -1577,7 +1577,7 @@ Optional Features:
|
||||
--enable-mmx MMX support
|
||||
--enable-3dnow 3DNow! support
|
||||
--enable-sse SSE support (--enable-sse=no|1|2|3|4)
|
||||
--enable-sse3e extended SSE3 (Intel Core Duo 2 new instructions) support
|
||||
--enable-sse-extension support for SSE extensions
|
||||
--enable-daz denormals-are-zeroes support
|
||||
--enable-sep SYSENTER/SYSEXIT support
|
||||
--enable-x86-debugger x86 debugger support
|
||||
@ -23110,7 +23110,7 @@ if test "$ac_x_libraries" = no; then
|
||||
# See if we find them without any special options.
|
||||
# Don't add to $LIBS permanently.
|
||||
ac_save_LIBS=$LIBS
|
||||
LIBS="-lXt $LIBS"
|
||||
LIBS="-lX11 $LIBS"
|
||||
cat >conftest.$ac_ext <<_ACEOF
|
||||
/* confdefs.h. */
|
||||
_ACEOF
|
||||
@ -39141,53 +39141,34 @@ _ACEOF
|
||||
|
||||
fi
|
||||
|
||||
{ echo "$as_me:$LINENO: checking for SSE3E support" >&5
|
||||
echo $ECHO_N "checking for SSE3E support... $ECHO_C" >&6; }
|
||||
# Check whether --enable-sse3e was given.
|
||||
if test "${enable_sse3e+set}" = set; then
|
||||
enableval=$enable_sse3e; if test "$enableval" = yes; then
|
||||
{ echo "$as_me:$LINENO: checking for SSE extensions support" >&5
|
||||
echo $ECHO_N "checking for SSE extensions support... $ECHO_C" >&6; }
|
||||
# Check whether --enable-sse-extension was given.
|
||||
if test "${enable_sse_extension+set}" = set; then
|
||||
enableval=$enable_sse_extension; if test "$enableval" = yes; then
|
||||
{ echo "$as_me:$LINENO: result: yes" >&5
|
||||
echo "${ECHO_T}yes" >&6; }
|
||||
cat >>confdefs.h <<\_ACEOF
|
||||
#define BX_SUPPORT_SSE3E 1
|
||||
#define BX_SUPPORT_SSE_EXTENSION 1
|
||||
_ACEOF
|
||||
|
||||
if test "$support_sse" -lt 3; then
|
||||
{ { echo "$as_me:$LINENO: error: SSE3E needs SSE3 support" >&5
|
||||
echo "$as_me: error: SSE3E needs SSE3 support" >&2;}
|
||||
{ (exit 1); exit 1; }; }
|
||||
fi
|
||||
elif test "$enableval" = no; then
|
||||
if test "$support_sse" -ge 4; then
|
||||
{ { echo "$as_me:$LINENO: error: SSE4 and greater requires SSE3E support" >&5
|
||||
echo "$as_me: error: SSE4 and greater requires SSE3E support" >&2;}
|
||||
{ (exit 1); exit 1; }; }
|
||||
fi
|
||||
{ echo "$as_me:$LINENO: result: no" >&5
|
||||
echo "${ECHO_T}no" >&6; }
|
||||
cat >>confdefs.h <<\_ACEOF
|
||||
#define BX_SUPPORT_SSE3E 0
|
||||
#define BX_SUPPORT_SSE_EXTENSION 0
|
||||
_ACEOF
|
||||
|
||||
fi
|
||||
|
||||
else
|
||||
|
||||
if test "$support_sse" -ge 4; then
|
||||
{ echo "$as_me:$LINENO: result: yes" >&5
|
||||
echo "${ECHO_T}yes" >&6; }
|
||||
cat >>confdefs.h <<\_ACEOF
|
||||
#define BX_SUPPORT_SSE3E 1
|
||||
_ACEOF
|
||||
|
||||
else
|
||||
{ echo "$as_me:$LINENO: result: no" >&5
|
||||
{ echo "$as_me:$LINENO: result: no" >&5
|
||||
echo "${ECHO_T}no" >&6; }
|
||||
cat >>confdefs.h <<\_ACEOF
|
||||
#define BX_SUPPORT_SSE3E 0
|
||||
cat >>confdefs.h <<\_ACEOF
|
||||
#define BX_SUPPORT_SSE_EXTENSION 0
|
||||
_ACEOF
|
||||
|
||||
fi
|
||||
|
||||
|
||||
fi
|
||||
|
||||
@ -2,7 +2,7 @@ dnl // Process this file with autoconf to produce a configure script.
|
||||
|
||||
AC_PREREQ(2.50)
|
||||
AC_INIT(bochs.h)
|
||||
AC_REVISION([[$Id: configure.in,v 1.336 2007-04-09 08:46:24 vruppert Exp $]])
|
||||
AC_REVISION([[$Id: configure.in,v 1.337 2007-04-19 16:12:18 sshwarts Exp $]])
|
||||
AC_CONFIG_HEADER(config.h)
|
||||
AC_CONFIG_HEADER(ltdlconf.h)
|
||||
|
||||
@ -1606,32 +1606,21 @@ else
|
||||
AC_DEFINE(BX_SUPPORT_SSE, 0)
|
||||
fi
|
||||
|
||||
AC_MSG_CHECKING(for SSE3E support)
|
||||
AC_ARG_ENABLE(sse3e,
|
||||
[ --enable-sse3e extended SSE3 (Intel Core Duo 2 new instructions) support],
|
||||
AC_MSG_CHECKING(for SSE extensions support)
|
||||
AC_ARG_ENABLE(sse-extension,
|
||||
[ --enable-sse-extension support for SSE extensions],
|
||||
[if test "$enableval" = yes; then
|
||||
AC_MSG_RESULT(yes)
|
||||
AC_DEFINE(BX_SUPPORT_SSE3E, 1)
|
||||
if test "$support_sse" -lt 3; then
|
||||
AC_MSG_ERROR([SSE3E needs SSE3 support])
|
||||
fi
|
||||
AC_DEFINE(BX_SUPPORT_SSE_EXTENSION, 1)
|
||||
elif test "$enableval" = no; then
|
||||
if test "$support_sse" -ge 4; then
|
||||
AC_MSG_ERROR([SSE4 and greater requires SSE3E support])
|
||||
fi
|
||||
AC_MSG_RESULT(no)
|
||||
AC_DEFINE(BX_SUPPORT_SSE3E, 0)
|
||||
AC_DEFINE(BX_SUPPORT_SSE_EXTENSION, 0)
|
||||
fi
|
||||
],
|
||||
[
|
||||
if test "$support_sse" -ge 4; then
|
||||
AC_MSG_RESULT(yes)
|
||||
AC_DEFINE(BX_SUPPORT_SSE3E, 1)
|
||||
else
|
||||
AC_MSG_RESULT(no)
|
||||
AC_DEFINE(BX_SUPPORT_SSE3E, 0)
|
||||
fi
|
||||
]
|
||||
AC_MSG_RESULT(no)
|
||||
AC_DEFINE(BX_SUPPORT_SSE_EXTENSION, 0)
|
||||
]
|
||||
)
|
||||
|
||||
AC_MSG_CHECKING(for DAZ support)
|
||||
|
||||
126
bochs/cpu/cpu.h
126
bochs/cpu/cpu.h
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: cpu.h,v 1.318 2007-04-14 10:05:30 sshwarts Exp $
|
||||
// $Id: cpu.h,v 1.319 2007-04-19 16:12:18 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -2006,7 +2006,7 @@ public: // for now...
|
||||
BX_SMF void PSHUFLW_VqWqIb(bxInstruction_c *i);
|
||||
BX_SMF void CMPPS_VpsWpsIb(bxInstruction_c *i);
|
||||
BX_SMF void CMPSS_VssWssIb(bxInstruction_c *i);
|
||||
BX_SMF void PINSRW_PqEdIb(bxInstruction_c *i);
|
||||
BX_SMF void PINSRW_PqEwIb(bxInstruction_c *i);
|
||||
BX_SMF void PEXTRW_GdPqIb(bxInstruction_c *i);
|
||||
BX_SMF void SHUFPS_VpsWpsIb(bxInstruction_c *i);
|
||||
BX_SMF void PMOVMSKB_GdPRq(bxInstruction_c *i);
|
||||
@ -2080,8 +2080,8 @@ public: // for now...
|
||||
BX_SMF void CMPPD_VpdWpdIb(bxInstruction_c *i);
|
||||
BX_SMF void CMPSD_VsdWsdIb(bxInstruction_c *i);
|
||||
BX_SMF void MOVNTI_MdGd(bxInstruction_c *i);
|
||||
BX_SMF void PINSRW_VdqEdIb(bxInstruction_c *i);
|
||||
BX_SMF void PEXTRW_GdVRdqIb(bxInstruction_c *i);
|
||||
BX_SMF void PINSRW_VdqEwIb(bxInstruction_c *i);
|
||||
BX_SMF void PEXTRW_GdUdqIb(bxInstruction_c *i);
|
||||
BX_SMF void SHUFPD_VpdWpdIb(bxInstruction_c *i);
|
||||
BX_SMF void PSRLW_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PSRLD_VdqWdq(bxInstruction_c *i);
|
||||
@ -2092,7 +2092,7 @@ public: // for now...
|
||||
BX_SMF void MOVQ_WqVq(bxInstruction_c *i);
|
||||
BX_SMF void MOVDQ2Q_PqVRq(bxInstruction_c *i);
|
||||
BX_SMF void MOVQ2DQ_VdqQq(bxInstruction_c *i);
|
||||
BX_SMF void PMOVMSKB_GdVRdq(bxInstruction_c *i);
|
||||
BX_SMF void PMOVMSKB_GdUdq(bxInstruction_c *i);
|
||||
BX_SMF void PSUBUSB_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PSUBUSW_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PMINUB_VdqWdq(bxInstruction_c *i);
|
||||
@ -2125,7 +2125,7 @@ public: // for now...
|
||||
BX_SMF void PMULUDQ_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PMADDWD_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PSADBW_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void MASKMOVDQU_VdqVRdq(bxInstruction_c *i);
|
||||
BX_SMF void MASKMOVDQU_VdqUdq(bxInstruction_c *i);
|
||||
BX_SMF void PSUBB_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PSUBW_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PSUBD_VdqWdq(bxInstruction_c *i);
|
||||
@ -2146,7 +2146,7 @@ public: // for now...
|
||||
BX_SMF void PSLLDQ_UdqIb(bxInstruction_c *i);
|
||||
/* SSE2 */
|
||||
|
||||
/*** Duplicate SSE/SSE2 instructions ***/
|
||||
/*** Duplicate SSE instructions ***/
|
||||
// Although in implementation, these instructions are aliased to the
|
||||
// another function, it's nice to have them call a separate function when
|
||||
// the decoder is being tested in stand-alone mode.
|
||||
@ -2177,6 +2177,7 @@ public: // for now...
|
||||
BX_SMF void MOVHPD_MqVsd(bxInstruction_c *);
|
||||
BX_SMF void MOVNTPD_MdqVpd(bxInstruction_c *);
|
||||
BX_SMF void MOVNTDQ_MdqVdq(bxInstruction_c *);
|
||||
BX_SMF void MOVNTDQA_VdqMdq(bxInstruction_c *i);
|
||||
#else
|
||||
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
@ -2185,38 +2186,46 @@ public: // for now...
|
||||
#define SSE2_ALIAS(i) BxError
|
||||
#endif
|
||||
|
||||
#define MOVUPD_VpdWpd /* 66 0f 10 */ SSE2_ALIAS(MOVUPS_VpsWps) /* 0f 10 */
|
||||
#define MOVUPD_WpdVpd /* 66 0f 11 */ SSE2_ALIAS(MOVUPS_WpsVps) /* 0f 11 */
|
||||
#define MOVAPD_VpdWpd /* 66 0f 28 */ SSE2_ALIAS(MOVAPS_VpsWps) /* 0f 28 */
|
||||
#define MOVAPD_WpdVpd /* 66 0f 29 */ SSE2_ALIAS(MOVAPS_WpsVps) /* 0f 29 */
|
||||
#define MOVDQU_VdqWdq /* f3 0f 6f */ SSE2_ALIAS(MOVUPS_VpsWps) /* 0f 10 */
|
||||
#define MOVDQU_WdqVdq /* f3 0f 7f */ SSE2_ALIAS(MOVUPS_WpsVps) /* 0f 11 */
|
||||
#define MOVDQA_VdqWdq /* 66 0f 6f */ SSE2_ALIAS(MOVAPS_VpsWps) /* 0f 28 */
|
||||
#define MOVDQA_WdqVdq /* 66 0f 7f */ SSE2_ALIAS(MOVAPS_WpsVps) /* 0f 29 */
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
#define SSE4_ALIAS(i) i
|
||||
#else
|
||||
#define SSE4_ALIAS(i) BxError
|
||||
#endif
|
||||
|
||||
#define PUNPCKLDQ_VdqWq /* 66 0f 62 */ SSE2_ALIAS(UNPCKLPS_VpsWq) /* 0f 14 */
|
||||
#define PUNPCKHDQ_VdqWq /* 66 0f 6a */ SSE2_ALIAS(UNPCKHPS_VpsWq) /* 0f 15 */
|
||||
#define MOVUPD_VpdWpd /* 66 0f 10 */ SSE2_ALIAS(MOVUPS_VpsWps) /* 0f 10 */
|
||||
#define MOVUPD_WpdVpd /* 66 0f 11 */ SSE2_ALIAS(MOVUPS_WpsVps) /* 0f 11 */
|
||||
#define MOVAPD_VpdWpd /* 66 0f 28 */ SSE2_ALIAS(MOVAPS_VpsWps) /* 0f 28 */
|
||||
#define MOVAPD_WpdVpd /* 66 0f 29 */ SSE2_ALIAS(MOVAPS_WpsVps) /* 0f 29 */
|
||||
#define MOVDQU_VdqWdq /* f3 0f 6f */ SSE2_ALIAS(MOVUPS_VpsWps) /* 0f 10 */
|
||||
#define MOVDQU_WdqVdq /* f3 0f 7f */ SSE2_ALIAS(MOVUPS_WpsVps) /* 0f 11 */
|
||||
#define MOVDQA_VdqWdq /* 66 0f 6f */ SSE2_ALIAS(MOVAPS_VpsWps) /* 0f 28 */
|
||||
#define MOVDQA_WdqVdq /* 66 0f 7f */ SSE2_ALIAS(MOVAPS_WpsVps) /* 0f 29 */
|
||||
|
||||
#define PAND_VdqWdq /* 66 0f db */ SSE2_ALIAS(ANDPS_VpsWps) /* 0f 54 */
|
||||
#define PANDN_VdqWdq /* 66 0f df */ SSE2_ALIAS(ANDNPS_VpsWps) /* 0f 55 */
|
||||
#define POR_VdqWdq /* 66 0f eb */ SSE2_ALIAS(ORPS_VpsWps) /* 0f 56 */
|
||||
#define PXOR_VdqWdq /* 66 0f ef */ SSE2_ALIAS(XORPS_VpsWps) /* 0f 57 */
|
||||
#define PUNPCKLDQ_VdqWq /* 66 0f 62 */ SSE2_ALIAS(UNPCKLPS_VpsWq) /* 0f 14 */
|
||||
#define PUNPCKHDQ_VdqWq /* 66 0f 6a */ SSE2_ALIAS(UNPCKHPS_VpsWq) /* 0f 15 */
|
||||
|
||||
#define ANDPD_VpdWpd /* 66 0f 54 */ SSE2_ALIAS(ANDPS_VpsWps) /* 0f 54 */
|
||||
#define ANDNPD_VpdWpd /* 66 0f 55 */ SSE2_ALIAS(ANDNPS_VpsWps) /* 0f 55 */
|
||||
#define ORPD_VpdWpd /* 66 0f 56 */ SSE2_ALIAS(ORPS_VpsWps) /* 0f 56 */
|
||||
#define XORPD_VpdWpd /* 66 0f 57 */ SSE2_ALIAS(XORPS_VpsWps) /* 0f 57 */
|
||||
#define PAND_VdqWdq /* 66 0f db */ SSE2_ALIAS(ANDPS_VpsWps) /* 0f 54 */
|
||||
#define PANDN_VdqWdq /* 66 0f df */ SSE2_ALIAS(ANDNPS_VpsWps) /* 0f 55 */
|
||||
#define POR_VdqWdq /* 66 0f eb */ SSE2_ALIAS(ORPS_VpsWps) /* 0f 56 */
|
||||
#define PXOR_VdqWdq /* 66 0f ef */ SSE2_ALIAS(XORPS_VpsWps) /* 0f 57 */
|
||||
|
||||
#define MOVLPD_VsdMq /* 66 0f 12 */ SSE2_ALIAS(MOVLPS_VpsMq) /* 0f 12 */
|
||||
#define MOVLPD_MqVsd /* 66 0f 13 */ SSE2_ALIAS(MOVLPS_MqVps) /* 0f 13 */
|
||||
#define MOVHPD_VsdMq /* 66 0f 16 */ SSE2_ALIAS(MOVHPS_VpsMq) /* 0f 16 */
|
||||
#define MOVHPD_MqVsd /* 66 0f 17 */ SSE2_ALIAS(MOVHPS_MqVps) /* 0f 17 */
|
||||
#define ANDPD_VpdWpd /* 66 0f 54 */ SSE2_ALIAS(ANDPS_VpsWps) /* 0f 54 */
|
||||
#define ANDNPD_VpdWpd /* 66 0f 55 */ SSE2_ALIAS(ANDNPS_VpsWps) /* 0f 55 */
|
||||
#define ORPD_VpdWpd /* 66 0f 56 */ SSE2_ALIAS(ORPS_VpsWps) /* 0f 56 */
|
||||
#define XORPD_VpdWpd /* 66 0f 57 */ SSE2_ALIAS(XORPS_VpsWps) /* 0f 57 */
|
||||
|
||||
#define MOVNTPD_MdqVpd /* 66 0f 2b */ SSE2_ALIAS(MOVNTPS_MdqVps) /* 0f 2b */
|
||||
#define MOVNTDQ_MdqVdq /* 66 0f e7 */ SSE2_ALIAS(MOVNTPS_MdqVps) /* 0f 2b */
|
||||
#define MOVLPD_VsdMq /* 66 0f 12 */ SSE2_ALIAS(MOVLPS_VpsMq) /* 0f 12 */
|
||||
#define MOVLPD_MqVsd /* 66 0f 13 */ SSE2_ALIAS(MOVLPS_MqVps) /* 0f 13 */
|
||||
#define MOVHPD_VsdMq /* 66 0f 16 */ SSE2_ALIAS(MOVHPS_VpsMq) /* 0f 16 */
|
||||
#define MOVHPD_MqVsd /* 66 0f 17 */ SSE2_ALIAS(MOVHPS_MqVps) /* 0f 17 */
|
||||
|
||||
#define UNPCKLPD_VpdWq /* 66 0f 14 */ PUNPCKLQDQ_VdqWq /* 66 0f 6c */
|
||||
#define UNPCKHPD_VpdWq /* 66 0f 15 */ PUNPCKHQDQ_VdqWq /* 66 0f 6d */
|
||||
#define MOVNTPD_MdqVpd /* 66 0f 2b */ SSE2_ALIAS(MOVNTPS_MdqVps) /* 0f 2b */
|
||||
#define MOVNTDQ_MdqVdq /* 66 0f e7 */ SSE2_ALIAS(MOVNTPS_MdqVps) /* 0f 2b */
|
||||
|
||||
#define UNPCKLPD_VpdWq /* 66 0f 14 */ PUNPCKLQDQ_VdqWq /* 66 0f 6c */
|
||||
#define UNPCKHPD_VpdWq /* 66 0f 15 */ PUNPCKHQDQ_VdqWq /* 66 0f 6d */
|
||||
|
||||
#define MOVNTDQA_VdqMdq /* 66 0f 38 2a */ SSE4_ALIAS(LDDQU_VdqMdq) /* f2 0f f0 */
|
||||
|
||||
#endif // #ifdef STAND_ALONE_DECODER
|
||||
|
||||
@ -2233,7 +2242,7 @@ public: // for now...
|
||||
BX_SMF void LDDQU_VdqMdq(bxInstruction_c *i);
|
||||
/* SSE3 */
|
||||
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
/* SSE3E */
|
||||
BX_SMF void PSHUFB_PqQq(bxInstruction_c *i);
|
||||
BX_SMF void PHADDW_PqQq(bxInstruction_c *i);
|
||||
@ -2271,6 +2280,55 @@ public: // for now...
|
||||
/* SSE3E */
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_SMF void PBLENDVB_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void BLENDVPS_VpsWps(bxInstruction_c *i);
|
||||
BX_SMF void BLENDVPD_VpdWpd(bxInstruction_c *i);
|
||||
BX_SMF void PTEST_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PMULDQ_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PCMPEQQ_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PACKUSDW_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PMOVSXBW_VdqWq(bxInstruction_c *i);
|
||||
BX_SMF void PMOVSXBD_VdqWd(bxInstruction_c *i);
|
||||
BX_SMF void PMOVSXBQ_VdqWw(bxInstruction_c *i);
|
||||
BX_SMF void PMOVSXWD_VdqWq(bxInstruction_c *i);
|
||||
BX_SMF void PMOVSXWQ_VdqWd(bxInstruction_c *i);
|
||||
BX_SMF void PMOVSXDQ_VdqWq(bxInstruction_c *i);
|
||||
BX_SMF void PMOVZXBW_VdqWq(bxInstruction_c *i);
|
||||
BX_SMF void PMOVZXBD_VdqWd(bxInstruction_c *i);
|
||||
BX_SMF void PMOVZXBQ_VdqWw(bxInstruction_c *i);
|
||||
BX_SMF void PMOVZXWD_VdqWq(bxInstruction_c *i);
|
||||
BX_SMF void PMOVZXWQ_VdqWd(bxInstruction_c *i);
|
||||
BX_SMF void PMOVZXDQ_VdqWq(bxInstruction_c *i);
|
||||
BX_SMF void PMINSB_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PMINSD_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PMINUW_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PMINUD_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PMAXSB_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PMAXSD_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PMAXUW_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PMAXUD_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PMULLD_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void PHMINPOSUW_VdqWdq(bxInstruction_c *i);
|
||||
BX_SMF void ROUNDPS_VpsWpsIb(bxInstruction_c *i);
|
||||
BX_SMF void ROUNDPD_VpdWpdIb(bxInstruction_c *i);
|
||||
BX_SMF void ROUNDSS_VssWssIb(bxInstruction_c *i);
|
||||
BX_SMF void ROUNDSD_VsdWsdIb(bxInstruction_c *i);
|
||||
BX_SMF void BLENDPS_VpsWpsIb(bxInstruction_c *i);
|
||||
BX_SMF void BLENDPD_VpdWpdIb(bxInstruction_c *i);
|
||||
BX_SMF void PBLENDW_VdqWdqIb(bxInstruction_c *i);
|
||||
BX_SMF void PEXTRB_HbdUdqIb(bxInstruction_c *i);
|
||||
BX_SMF void PEXTRW_HwdUdqIb(bxInstruction_c *i);
|
||||
BX_SMF void PEXTRD_HdUdqIb(bxInstruction_c *i);
|
||||
BX_SMF void EXTRACTPS_HdUpsIb(bxInstruction_c *i);
|
||||
BX_SMF void PINSRB_VdqEbIb(bxInstruction_c *i);
|
||||
BX_SMF void INSERTPS_VpsWssIb(bxInstruction_c *i);
|
||||
BX_SMF void PINSRD_VdqEdIb(bxInstruction_c *i);
|
||||
BX_SMF void DPPS_VpsWpsIb(bxInstruction_c *i);
|
||||
BX_SMF void DPPD_VpdWpdIb(bxInstruction_c *i);
|
||||
BX_SMF void MPSADBW_VdqWdqIb(bxInstruction_c *i);
|
||||
#endif
|
||||
|
||||
BX_SMF void CMPXCHG_XBTS(bxInstruction_c *);
|
||||
BX_SMF void CMPXCHG_IBTS(bxInstruction_c *);
|
||||
BX_SMF void CMPXCHG_EbGb(bxInstruction_c *);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: cpuid.cc,v 1.42 2007-04-14 10:05:30 sshwarts Exp $
|
||||
// $Id: cpuid.cc,v 1.43 2007-04-19 16:12:18 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -123,18 +123,40 @@ Bit32u BX_CPU_C::get_cpu_version_information()
|
||||
/* Get CPU extended feature flags. */
|
||||
Bit32u BX_CPU_C::get_extended_cpuid_features()
|
||||
{
|
||||
// [0:0] SSE3: SSE3 Instructions
|
||||
// [2:1] reserved
|
||||
// [3:3] MONITOR/MWAIT support
|
||||
// [4:4] DS-CPL: CPL qualified debug store
|
||||
// [5:5] VMX: Virtual Machine Technology
|
||||
// [6:6] reserved
|
||||
// [7:7] EST: Enhanced Intel SpeedStep Technology
|
||||
// [8:8] TM2: Thermal Monitor 2
|
||||
// [9:9] SSE3E: SSE3E Instructions (Intel Core Duo 2 new instructions)
|
||||
// [10:10] CNXT-ID: L1 context ID
|
||||
// [12:11] reserved
|
||||
// [13:13] CMPXCHG16B: CMPXCHG16B instruction support
|
||||
// [14:14] xTPR update control
|
||||
// [18:15] reserved
|
||||
// [19:19] SSE4: SSE4 Instructions
|
||||
// [20:20] SSE4E: SSE4E Instructions
|
||||
// [31:21] reserved
|
||||
|
||||
Bit32u features = 0;
|
||||
|
||||
#if BX_SUPPORT_SSE >= 3
|
||||
features |= 0x1; // report SSE3
|
||||
features |= 0x1; // support SSE3
|
||||
#endif
|
||||
#if BX_SUPPORT_SSE3E
|
||||
features |= (1<<9); // report SSE3E (Intel Core Duo 2 new instructions)
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
features |= (1<<9); // support SSE3E
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
features |= (1<<13); // support CMPXCHG16B
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
features |= (1<<19); // support SSE4
|
||||
#endif
|
||||
|
||||
return features;
|
||||
}
|
||||
@ -256,16 +278,23 @@ void BX_CPU_C::CPUID(bxInstruction_c *i)
|
||||
// [23:16] Number of logical processors in one physical processor
|
||||
// [31:24] Local Apic ID
|
||||
// ECX: Feature Flags::Extended
|
||||
// [0:0] SSE3
|
||||
// [2:1] Reserved
|
||||
// [3:3] MONITOR/MWAIT
|
||||
// [4:4] CPL qualified debug store available
|
||||
// [6:5] Reserved
|
||||
// [7:7] Enchanced Intel Speedstep Technology
|
||||
// [0:0] SSE3: SSE3 Instructions
|
||||
// [2:1] reserved
|
||||
// [3:3] MONITOR/MWAIT support
|
||||
// [4:4] DS-CPL: CPL qualified debug store
|
||||
// [5:5] VMX: Virtual Machine Technology
|
||||
// [6:6] reserved
|
||||
// [7:7] EST: Enhanced Intel SpeedStep Technology
|
||||
// [8:8] TM2: Thermal Monitor 2
|
||||
// [12:9] Reserved
|
||||
// [13:13] CMPXCHG16B
|
||||
// [31:14] Reserved
|
||||
// [9:9] SSE3E: SSE3E Instructions (Intel Core Duo 2 new instructions)
|
||||
// [10:10] CNXT-ID: L1 context ID
|
||||
// [12:11] reserved
|
||||
// [13:13] CMPXCHG16B: CMPXCHG16B instruction support
|
||||
// [14:14] xTPR update control
|
||||
// [18:15] reserved
|
||||
// [19:19] SSE4: SSE4 Instructions
|
||||
// [20:20] SSE4E: SSE4E Instructions
|
||||
// [31:21] reserved
|
||||
// EDX: Feature Flags
|
||||
// [0:0] FPU on chip
|
||||
// [1:1] VME: Virtual-8086 Mode enhancements
|
||||
@ -291,13 +320,14 @@ void BX_CPU_C::CPUID(bxInstruction_c *i)
|
||||
// [21:21] DS: Debug Store
|
||||
// [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
|
||||
// [23:23] MMX Technology
|
||||
// [24;24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
|
||||
// [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
|
||||
// [25:25] SSE: SSE Extensions
|
||||
// [26:26] SSE2: SSE2 Extensions
|
||||
// [27:27] Reserved
|
||||
// [28:28] Hyper Threading Technology
|
||||
// [29:29] TM: Thermal Monitor
|
||||
// [31:30] Reserved
|
||||
// [30:30] Reserved
|
||||
// [31:31] PBE: Pending Break Enable
|
||||
RAX = get_cpu_version_information();
|
||||
RBX = 0;
|
||||
#if BX_SUPPORT_APIC
|
||||
@ -365,7 +395,7 @@ void BX_CPU_C::CPUID(bxInstruction_c *i)
|
||||
// [21:21] Reserved
|
||||
// [22:22] AMD MMX Extensions
|
||||
// [*] [23:23] MMX Technology
|
||||
// [*] [24;24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
|
||||
// [*] [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
|
||||
// [25:25] Fast FXSAVE/FXRSTOR mode support
|
||||
// [26:26] Reserved
|
||||
// [27:27] Support RDTSCP Instruction
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: fetchdecode.cc,v 1.105 2007-04-09 20:28:14 sshwarts Exp $
|
||||
// $Id: fetchdecode.cc,v 1.106 2007-04-19 16:12:19 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -767,13 +767,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
|
||||
/* 0F 35 */ { 0, &BX_CPU_C::SYSEXIT },
|
||||
/* 0F 36 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F 37 */ { 0, &BX_CPU_C::BxError },
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
/* 0F 38 */ { BxAnother | Bx3ByteOpcode | Bx3ByteOpTable, NULL, BxOpcode3ByteTableA4 }, // 3-byte escape
|
||||
#else
|
||||
/* 0F 38 */ { 0, &BX_CPU_C::BxError },
|
||||
#endif
|
||||
/* 0F 39 */ { 0, &BX_CPU_C::BxError },
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
/* 0F 3A */ { BxAnother | Bx3ByteOpcode | Bx3ByteOpTable, NULL, BxOpcode3ByteTableA5 }, // 3-byte escape
|
||||
#else
|
||||
/* 0F 3A */ { 0, &BX_CPU_C::BxError },
|
||||
@ -1325,13 +1325,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
|
||||
/* 0F 35 */ { 0, &BX_CPU_C::SYSEXIT },
|
||||
/* 0F 36 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F 37 */ { 0, &BX_CPU_C::BxError },
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
/* 0F 38 */ { BxAnother | Bx3ByteOpcode | Bx3ByteOpTable, NULL, BxOpcode3ByteTableA4 }, // 3-byte escape
|
||||
#else
|
||||
/* 0F 38 */ { 0, &BX_CPU_C::BxError },
|
||||
#endif
|
||||
/* 0F 39 */ { 0, &BX_CPU_C::BxError },
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
/* 0F 3A */ { BxAnother | Bx3ByteOpcode | Bx3ByteOpTable, NULL, BxOpcode3ByteTableA5 }, // 3-byte escape
|
||||
#else
|
||||
/* 0F 3A */ { 0, &BX_CPU_C::BxError },
|
||||
@ -1544,7 +1544,7 @@ BX_CPU_C::fetchDecode32(Bit8u *iptr, bxInstruction_c *instruction, unsigned rema
|
||||
unsigned b1, b2, ilen=0, attr, os_32;
|
||||
unsigned imm_mode, offset;
|
||||
unsigned rm = 0, mod=0, nnn=0;
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
unsigned b3 = 0;
|
||||
#endif
|
||||
|
||||
@ -1661,7 +1661,7 @@ fetch_b1:
|
||||
|
||||
attr = BxOpcodeInfo[b1+offset].Attr;
|
||||
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
// handle 3-byte escape
|
||||
if (attr & Bx3ByteOpcode) {
|
||||
if (ilen < remain) {
|
||||
@ -1840,7 +1840,7 @@ modrm_done:
|
||||
case BxRMGroup:
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[rm]);
|
||||
break;
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
case Bx3ByteOpTable:
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[b3 >> 4]);
|
||||
break;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: fetchdecode.h,v 1.28 2007-03-23 21:27:12 sshwarts Exp $
|
||||
// $Id: fetchdecode.h,v 1.29 2007-04-19 16:12:19 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2005 Stanislav Shwartsman
|
||||
@ -1427,15 +1427,15 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fc3[4] = {
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fc4[4] = {
|
||||
/* -- */ { BxImmediate_Ib, &BX_CPU_C::PINSRW_PqEdIb },
|
||||
/* 66 */ { BxImmediate_Ib, &BX_CPU_C::PINSRW_VdqEdIb },
|
||||
/* -- */ { BxImmediate_Ib, &BX_CPU_C::PINSRW_PqEwIb },
|
||||
/* 66 */ { BxImmediate_Ib, &BX_CPU_C::PINSRW_VdqEwIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fc5[4] = {
|
||||
/* -- */ { BxImmediate_Ib, &BX_CPU_C::PEXTRW_GdPqIb },
|
||||
/* 66 */ { BxImmediate_Ib, &BX_CPU_C::PEXTRW_GdVRdqIb },
|
||||
/* 66 */ { BxImmediate_Ib, &BX_CPU_C::PEXTRW_GdUdqIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
@ -1498,7 +1498,7 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fd6[4] = {
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fd7[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::PMOVMSKB_GdPRq },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVMSKB_GdVRdq },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVMSKB_GdUdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
@ -1722,7 +1722,7 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0ff6[4] = {
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0ff7[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::MASKMOVQ_PqPRq },
|
||||
/* 66 */ { 0, &BX_CPU_C::MASKMOVDQU_VdqVRdq },
|
||||
/* 66 */ { 0, &BX_CPU_C::MASKMOVDQU_VdqUdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
@ -1846,7 +1846,7 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_G1407[4] = {
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3800[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::PSHUFB_PqQq },
|
||||
@ -1918,6 +1918,104 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3809[4] = {
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3810[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PBLENDVB_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3814[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::BLENDVPS_VpsWps },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3815[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::BLENDVPD_VpdWpd },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3817[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PTEST_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3820[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVSXBW_VdqWq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3821[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVSXBD_VdqWd },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3822[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVSXBQ_VdqWw },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3823[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVSXWD_VdqWq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3824[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVSXWQ_VdqWd },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3825[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVSXDQ_VdqWq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3828[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMULDQ_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3829[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PCMPEQQ_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f382a[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::MOVNTDQA_VdqMdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f382b[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PACKUSDW_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f380a[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::PSIGND_PqQq },
|
||||
/* 66 */ { 0, &BX_CPU_C::PSIGND_VdqWdq },
|
||||
@ -1953,6 +2051,167 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f381e[4] = {
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3830[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVZXBW_VdqWq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3831[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVZXBD_VdqWd },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3832[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVZXBQ_VdqWw },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3833[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVZXWD_VdqWq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3834[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVZXWQ_VdqWd },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3835[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMOVZXDQ_VdqWq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3838[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMINSB_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3839[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMINSD_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f383a[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMINUW_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f383b[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMINUD_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f383c[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMAXSB_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f383d[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMAXSD_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f383e[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMAXUW_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f383f[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMAXUD_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3840[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PMULLD_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3841[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PHMINPOSUW_VdqWdq },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a08[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::ROUNDPS_VpsWpsIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a09[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::ROUNDPD_VpdWpdIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a0a[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::ROUNDSS_VssWssIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a0b[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::ROUNDSD_VsdWsdIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a0c[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::BLENDPS_VpsWpsIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a0d[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::BLENDPD_VpdWpdIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a0e[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PBLENDW_VdqWdqIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a0f[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::PALIGNR_PqQqIb },
|
||||
/* 66 */ { 0, &BX_CPU_C::PALIGNR_VdqWdqIb },
|
||||
@ -1960,6 +2219,76 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a0f[4] = {
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a14[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PEXTRB_HbdUdqIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a15[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PEXTRW_HwdUdqIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a16[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PEXTRD_HdUdqIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a17[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::EXTRACTPS_HdUpsIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a20[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PINSRB_VdqEbIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a21[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::INSERTPS_VpsWssIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a22[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::PINSRD_VdqEdIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a40[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::DPPS_VpsWpsIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a41[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::DPPD_VpdWpdIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f3a42[4] = {
|
||||
/* -- */ { 0, &BX_CPU_C::BxError },
|
||||
/* 66 */ { 0, &BX_CPU_C::MPSADBW_VdqWdqIb },
|
||||
/* F2 */ { 0, &BX_CPU_C::BxError },
|
||||
/* F3 */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
/* ************************************************************************ */
|
||||
/* 3-byte opcode table (Table A-4, 0F 38) */
|
||||
|
||||
@ -1983,14 +2312,14 @@ static const BxOpcodeInfo_t BxOpcode3ByteOp0f380x[16] = {
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcode3ByteOp0f381x[16] = {
|
||||
/* 00 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 00 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3810 },
|
||||
/* 01 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 02 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 03 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 04 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 05 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 04 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3814 },
|
||||
/* 05 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3815 },
|
||||
/* 06 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 07 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 07 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3817 },
|
||||
/* 08 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 09 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0A */ { 0, &BX_CPU_C::BxError },
|
||||
@ -2001,9 +2330,47 @@ static const BxOpcodeInfo_t BxOpcode3ByteOp0f381x[16] = {
|
||||
/* 0F */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcode3ByteTableA4[16] = {
|
||||
/* 00 */ { Bx3ByteOpIndex, NULL, BxOpcode3ByteOp0f380x },
|
||||
/* 00 */ { Bx3ByteOpIndex, NULL, BxOpcode3ByteOp0f381x },
|
||||
static const BxOpcodeInfo_t BxOpcode3ByteOp0f382x[16] = {
|
||||
/* 00 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3820 },
|
||||
/* 01 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3821 },
|
||||
/* 02 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3822 },
|
||||
/* 03 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3823 },
|
||||
/* 04 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3824 },
|
||||
/* 05 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3825 },
|
||||
/* 06 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 07 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 08 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3828 },
|
||||
/* 09 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3829 },
|
||||
/* 0A */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f382a },
|
||||
/* 0B */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f382b },
|
||||
/* 0C */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0D */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0E */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcode3ByteOp0f383x[16] = {
|
||||
/* 00 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3830 },
|
||||
/* 01 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3831 },
|
||||
/* 02 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3832 },
|
||||
/* 03 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3833 },
|
||||
/* 04 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3834 },
|
||||
/* 05 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3835 },
|
||||
/* 06 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 07 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 08 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3838 },
|
||||
/* 09 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3839 },
|
||||
/* 0A */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f383a },
|
||||
/* 0B */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f383b },
|
||||
/* 0C */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f383c },
|
||||
/* 0D */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f383d },
|
||||
/* 0E */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f383e },
|
||||
/* 0F */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f383f }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcode3ByteOp0f384x[16] = {
|
||||
/* 00 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3840 },
|
||||
/* 01 */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3841 },
|
||||
/* 02 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 03 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 04 */ { 0, &BX_CPU_C::BxError },
|
||||
@ -2018,6 +2385,25 @@ static const BxOpcodeInfo_t BxOpcode3ByteTableA4[16] = {
|
||||
/* 0D */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0E */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcode3ByteTableA4[16] = {
|
||||
/* 00 */ { Bx3ByteOpIndex, NULL, BxOpcode3ByteOp0f380x },
|
||||
/* 01 */ { Bx3ByteOpIndex, NULL, BxOpcode3ByteOp0f381x },
|
||||
/* 02 */ { Bx3ByteOpIndex, NULL, BxOpcode3ByteOp0f382x },
|
||||
/* 03 */ { Bx3ByteOpIndex, NULL, BxOpcode3ByteOp0f383x },
|
||||
/* 04 */ { Bx3ByteOpIndex, NULL, BxOpcode3ByteOp0f384x },
|
||||
/* 05 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 06 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 07 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 08 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 09 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0A */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0B */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0C */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0D */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0E */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
/* ************************************************************************ */
|
||||
@ -2032,6 +2418,25 @@ static const BxOpcodeInfo_t BxOpcode3ByteOp0f3a0x[16] = {
|
||||
/* 05 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 06 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 07 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 08 */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a08 },
|
||||
/* 09 */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a09 },
|
||||
/* 0A */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a0a },
|
||||
/* 0B */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a0b },
|
||||
/* 0C */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a0c },
|
||||
/* 0D */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a0d },
|
||||
/* 0E */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a0e },
|
||||
/* 0F */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a0f }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcode3ByteOp0f3a1x[16] = {
|
||||
/* 00 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 01 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 02 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 03 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 04 */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a14 },
|
||||
/* 05 */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a15 },
|
||||
/* 06 */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a16 },
|
||||
/* 07 */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a17 },
|
||||
/* 08 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 09 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0A */ { 0, &BX_CPU_C::BxError },
|
||||
@ -2039,13 +2444,13 @@ static const BxOpcodeInfo_t BxOpcode3ByteOp0f3a0x[16] = {
|
||||
/* 0C */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0D */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0E */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a0f }
|
||||
/* 0F */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcode3ByteTableA5[16] = {
|
||||
/* 00 */ { Bx3ByteOpIndex, NULL, BxOpcode3ByteOp0f3a0x },
|
||||
/* 01 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 02 */ { 0, &BX_CPU_C::BxError },
|
||||
static const BxOpcodeInfo_t BxOpcode3ByteOp0f3a2x[16] = {
|
||||
/* 00 */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a20 },
|
||||
/* 01 */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a21 },
|
||||
/* 02 */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a22 },
|
||||
/* 03 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 04 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 05 */ { 0, &BX_CPU_C::BxError },
|
||||
@ -2061,6 +2466,44 @@ static const BxOpcodeInfo_t BxOpcode3ByteTableA5[16] = {
|
||||
/* 0F */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
#endif /* BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4 */
|
||||
static const BxOpcodeInfo_t BxOpcode3ByteOp0f3a4x[16] = {
|
||||
/* 00 */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a40 },
|
||||
/* 01 */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a41 },
|
||||
/* 02 */ { BxImmediate_Ib | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f3a42 },
|
||||
/* 03 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 04 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 05 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 06 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 07 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 08 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 09 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0A */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0B */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0C */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0D */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0E */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcode3ByteTableA5[16] = {
|
||||
/* 00 */ { Bx3ByteOpIndex, NULL, BxOpcode3ByteOp0f3a0x },
|
||||
/* 01 */ { Bx3ByteOpIndex, NULL, BxOpcode3ByteOp0f3a1x },
|
||||
/* 02 */ { Bx3ByteOpIndex, NULL, BxOpcode3ByteOp0f3a2x },
|
||||
/* 03 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 04 */ { Bx3ByteOpIndex, NULL, BxOpcode3ByteOp0f3a4x },
|
||||
/* 05 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 06 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 07 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 08 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 09 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0A */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0B */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0C */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0D */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0E */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F */ { 0, &BX_CPU_C::BxError }
|
||||
};
|
||||
|
||||
#endif // BX_SUPPORT_SSE >= 4 || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: fetchdecode64.cc,v 1.110 2007-04-09 21:14:59 sshwarts Exp $
|
||||
// $Id: fetchdecode64.cc,v 1.111 2007-04-19 16:12:19 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -886,13 +886,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* 0F 35 */ { 0, &BX_CPU_C::BxError }, // SYSENTER/SYSEXIT not recognized in long mode
|
||||
/* 0F 36 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F 37 */ { 0, &BX_CPU_C::BxError },
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
/* 0F 38 */ { BxAnother | Bx3ByteOpcode | Bx3ByteOpTable, NULL, BxOpcode3ByteTableA4 }, // 3-byte escape
|
||||
#else
|
||||
/* 0F 38 */ { 0, &BX_CPU_C::BxError },
|
||||
#endif
|
||||
/* 0F 39 */ { 0, &BX_CPU_C::BxError },
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
/* 0F 3A */ { BxAnother | Bx3ByteOpcode | Bx3ByteOpTable, NULL, BxOpcode3ByteTableA5 }, // 3-byte escape
|
||||
#else
|
||||
/* 0F 3A */ { 0, &BX_CPU_C::BxError },
|
||||
@ -1415,13 +1415,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* 0F 35 */ { 0, &BX_CPU_C::BxError }, // SYSENTER/SYSEXIT not recognized in long mode
|
||||
/* 0F 36 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F 37 */ { 0, &BX_CPU_C::BxError },
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
/* 0F 38 */ { BxAnother | Bx3ByteOpcode | Bx3ByteOpTable, NULL, BxOpcode3ByteTableA4 }, // 3-byte escape
|
||||
#else
|
||||
/* 0F 38 */ { 0, &BX_CPU_C::BxError },
|
||||
#endif
|
||||
/* 0F 39 */ { 0, &BX_CPU_C::BxError },
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
/* 0F 3A */ { BxAnother | Bx3ByteOpcode | Bx3ByteOpTable, NULL, BxOpcode3ByteTableA5 }, // 3-byte escape
|
||||
#else
|
||||
/* 0F 3A */ { 0, &BX_CPU_C::BxError },
|
||||
@ -1944,13 +1944,13 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* 0F 35 */ { 0, &BX_CPU_C::BxError }, // SYSENTER/SYSEXIT not recognized in long mode
|
||||
/* 0F 36 */ { 0, &BX_CPU_C::BxError },
|
||||
/* 0F 37 */ { 0, &BX_CPU_C::BxError },
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
/* 0F 38 */ { BxAnother | Bx3ByteOpcode | Bx3ByteOpTable, NULL, BxOpcode3ByteTableA4 }, // 3-byte escape
|
||||
#else
|
||||
/* 0F 38 */ { 0, &BX_CPU_C::BxError },
|
||||
#endif
|
||||
/* 0F 39 */ { 0, &BX_CPU_C::BxError },
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
/* 0F 3A */ { BxAnother | Bx3ByteOpcode | Bx3ByteOpTable, NULL, BxOpcode3ByteTableA5 }, // 3-byte escape
|
||||
#else
|
||||
/* 0F 3A */ { 0, &BX_CPU_C::BxError },
|
||||
@ -2163,7 +2163,7 @@ BX_CPU_C::fetchDecode64(Bit8u *iptr, bxInstruction_c *instruction, unsigned rema
|
||||
unsigned b1, b2, ilen=0, attr, lock=0;
|
||||
unsigned imm_mode, offset, rex_r = 0, rex_x = 0, rex_b = 0;
|
||||
unsigned rm = 0, mod = 0, nnn = 0;
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
unsigned b3 = 0;
|
||||
#endif
|
||||
#define SSE_PREFIX_NONE 0
|
||||
@ -2298,7 +2298,7 @@ fetch_b1:
|
||||
|
||||
attr = BxOpcodeInfo64[b1+offset].Attr;
|
||||
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
// handle 3-byte escape
|
||||
if (attr & Bx3ByteOpcode) {
|
||||
if (ilen < remain) {
|
||||
@ -2533,7 +2533,7 @@ modrm_done:
|
||||
case BxRMGroup:
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[rm & 0x7]);
|
||||
break;
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
case Bx3ByteOpTable:
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[b3 >> 4]);
|
||||
break;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: mmx.cc,v 1.59 2007-03-23 21:27:12 sshwarts Exp $
|
||||
// $Id: mmx.cc,v 1.60 2007-04-19 16:12:19 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2002 Stanislav Shwartsman
|
||||
@ -115,12 +115,12 @@ void BX_CPU_C::prepareFPU2MMX(void)
|
||||
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
|
||||
/* 0F 38 00 */
|
||||
void BX_CPU_C::PSHUFB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -145,7 +145,7 @@ void BX_CPU_C::PSHUFB_PqQq(bxInstruction_c *i)
|
||||
|
||||
BX_WRITE_MMX_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PSHUFB_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PSHUFB_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -153,7 +153,7 @@ void BX_CPU_C::PSHUFB_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 01 */
|
||||
void BX_CPU_C::PHADDW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -174,7 +174,7 @@ void BX_CPU_C::PHADDW_PqQq(bxInstruction_c *i)
|
||||
|
||||
BX_WRITE_MMX_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PHADDW_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PHADDW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -182,7 +182,7 @@ void BX_CPU_C::PHADDW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 02 */
|
||||
void BX_CPU_C::PHADDD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -201,7 +201,7 @@ void BX_CPU_C::PHADDD_PqQq(bxInstruction_c *i)
|
||||
|
||||
BX_WRITE_MMX_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PHADDD_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PHADDD_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -209,7 +209,7 @@ void BX_CPU_C::PHADDD_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 03 */
|
||||
void BX_CPU_C::PHADDSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -231,7 +231,7 @@ void BX_CPU_C::PHADDSW_PqQq(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_MMX_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PHADDSW_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PHADDSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -239,7 +239,7 @@ void BX_CPU_C::PHADDSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 04 */
|
||||
void BX_CPU_C::PMADDUBSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -264,7 +264,7 @@ void BX_CPU_C::PMADDUBSW_PqQq(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_MMX_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMADDUBSW_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PMADDUBSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -272,7 +272,7 @@ void BX_CPU_C::PMADDUBSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 05 */
|
||||
void BX_CPU_C::PHSUBSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -294,7 +294,7 @@ void BX_CPU_C::PHSUBSW_PqQq(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_MMX_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PHSUBSW_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PHSUBSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -302,7 +302,7 @@ void BX_CPU_C::PHSUBSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 05 */
|
||||
void BX_CPU_C::PHSUBW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -323,7 +323,7 @@ void BX_CPU_C::PHSUBW_PqQq(bxInstruction_c *i)
|
||||
|
||||
BX_WRITE_MMX_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PHSUBW_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PHSUBW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -331,7 +331,7 @@ void BX_CPU_C::PHSUBW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 06 */
|
||||
void BX_CPU_C::PHSUBD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -350,7 +350,7 @@ void BX_CPU_C::PHSUBD_PqQq(bxInstruction_c *i)
|
||||
|
||||
BX_WRITE_MMX_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PHSUBD_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PHSUBD_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -358,7 +358,7 @@ void BX_CPU_C::PHSUBD_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 08 */
|
||||
void BX_CPU_C::PSIGNB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -379,7 +379,7 @@ void BX_CPU_C::PSIGNB_PqQq(bxInstruction_c *i)
|
||||
|
||||
BX_WRITE_MMX_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("PSIGNB_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PSIGNB_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -387,7 +387,7 @@ void BX_CPU_C::PSIGNB_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 09 */
|
||||
void BX_CPU_C::PSIGNW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -408,7 +408,7 @@ void BX_CPU_C::PSIGNW_PqQq(bxInstruction_c *i)
|
||||
|
||||
BX_WRITE_MMX_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("PSIGNW_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PSIGNW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -416,7 +416,7 @@ void BX_CPU_C::PSIGNW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 0A */
|
||||
void BX_CPU_C::PSIGND_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -439,7 +439,7 @@ void BX_CPU_C::PSIGND_PqQq(bxInstruction_c *i)
|
||||
|
||||
BX_WRITE_MMX_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("PSIGND_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PSIGND_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -447,7 +447,7 @@ void BX_CPU_C::PSIGND_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 0B */
|
||||
void BX_CPU_C::PMULHRSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -474,7 +474,7 @@ void BX_CPU_C::PMULHRSW_PqQq(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_MMX_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMULHRSW_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PMULHRSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -482,7 +482,7 @@ void BX_CPU_C::PMULHRSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 1C */
|
||||
void BX_CPU_C::PABSB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op;
|
||||
@ -507,7 +507,7 @@ void BX_CPU_C::PABSB_PqQq(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_MMX_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("PABSB_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PABSB_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -515,7 +515,7 @@ void BX_CPU_C::PABSB_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 1D */
|
||||
void BX_CPU_C::PABSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op;
|
||||
@ -536,7 +536,7 @@ void BX_CPU_C::PABSW_PqQq(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_MMX_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("PABSW_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PABSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -544,7 +544,7 @@ void BX_CPU_C::PABSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 1E */
|
||||
void BX_CPU_C::PABSD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op;
|
||||
@ -563,7 +563,7 @@ void BX_CPU_C::PABSD_PqQq(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_MMX_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("PABSD_PqQq: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PABSD_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -571,7 +571,7 @@ void BX_CPU_C::PABSD_PqQq(bxInstruction_c *i)
|
||||
/* 0F 3A 0F */
|
||||
void BX_CPU_C::PALIGNR_PqQqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE3E
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -599,12 +599,12 @@ void BX_CPU_C::PALIGNR_PqQqIb(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_MMX_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PALIGNR_PqQqIb: required SSE3E, use --enable-sse3e option"));
|
||||
BX_INFO(("PALIGNR_PqQqIb: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* BX_SUPPORT_SSE3E || BX_SUPPORT_SSE >= 4 */
|
||||
#endif // BX_SUPPORT_SSE >= 4 || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
|
||||
/* 0F 60 */
|
||||
void BX_CPU_C::PUNPCKLBW_PqQd(bxInstruction_c *i)
|
||||
@ -1241,7 +1241,7 @@ void BX_CPU_C::MOVQ_QqPq(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* 0F C4 */
|
||||
void BX_CPU_C::PINSRW_PqEdIb(bxInstruction_c *i)
|
||||
void BX_CPU_C::PINSRW_PqEwIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
1446
bochs/cpu/sse.cc
1446
bochs/cpu/sse.cc
File diff suppressed because it is too large
Load Diff
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: sse_move.cc,v 1.57 2007-03-23 21:27:12 sshwarts Exp $
|
||||
// $Id: sse_move.cc,v 1.58 2007-04-19 16:12:20 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2003 Stanislav Shwartsman
|
||||
@ -665,7 +665,7 @@ void BX_CPU_C::MOVDDUP_VpdWq(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("MOVDDUP_VpdWq: required PNI, use --enable-pni option"));
|
||||
BX_INFO(("MOVDDUP_VpdWq: required SSE3, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -694,7 +694,7 @@ void BX_CPU_C::MOVSLDUP_VpsWps(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("MOVSLDUP_VpsWps: required PNI, use --enable-pni option"));
|
||||
BX_INFO(("MOVSLDUP_VpsWps: required SSE3, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -723,7 +723,7 @@ void BX_CPU_C::MOVSHDUP_VpsWps(bxInstruction_c *i)
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("MOVHLDUP_VpsWps: required PNI, use --enable-pni option"));
|
||||
BX_INFO(("MOVHLDUP_VpsWps: required SSE3, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -814,19 +814,19 @@ void BX_CPU_C::LDDQU_VdqMdq(bxInstruction_c *i)
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
|
||||
#else
|
||||
BX_INFO(("LDDQU_VdqMdq: required PNI, use --enable-pni option"));
|
||||
BX_INFO(("LDDQU_VdqMdq: required SSE3, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F F7 */
|
||||
void BX_CPU_C::MASKMOVDQU_VdqVRdq(bxInstruction_c *i)
|
||||
void BX_CPU_C::MASKMOVDQU_VdqUdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
if (! i->modC0()) {
|
||||
BX_INFO(("MASKMOVDQU_VdqVRdq: unexpected memory reference"));
|
||||
BX_INFO(("MASKMOVDQU_VdqUdq: unexpected memory reference"));
|
||||
UndefinedOpcode(i);
|
||||
}
|
||||
|
||||
@ -855,7 +855,7 @@ void BX_CPU_C::MASKMOVDQU_VdqVRdq(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
#else
|
||||
BX_INFO(("MASKMOVDQU_VdqVRdq: required SSE2, use --enable-sse option"));
|
||||
BX_INFO(("MASKMOVDQU_VdqUdq: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -1080,436 +1080,37 @@ void BX_CPU_C::MOVQ2DQ_VdqQq(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ****************************** */
|
||||
/* SSE: MEMORY SHUFFLE OPERATIONS */
|
||||
/* ****************************** */
|
||||
|
||||
/* 0F C6 */
|
||||
void BX_CPU_C::SHUFPS_VpsWpsIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
Bit8u order = i->Ib();
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm32u(0) = op1.xmm32u((order >> 0) & 0x3);
|
||||
result.xmm32u(1) = op1.xmm32u((order >> 2) & 0x3);
|
||||
result.xmm32u(2) = op2.xmm32u((order >> 4) & 0x3);
|
||||
result.xmm32u(3) = op2.xmm32u((order >> 6) & 0x3);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("SHUFPS_VpsWpsIb: required SSE, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F C6 */
|
||||
void BX_CPU_C::SHUFPD_VpdWpdIb(bxInstruction_c *i)
|
||||
/* 66 0F D7 */
|
||||
void BX_CPU_C::PMOVMSKB_GdUdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
Bit8u order = i->Ib();
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
|
||||
Bit32u result = 0;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = op1.xmm64u((order >> 0) & 0x1);
|
||||
result.xmm64u(1) = op2.xmm64u((order >> 1) & 0x1);
|
||||
if(op.xmmubyte(0x0) & 0x80) result |= 0x0001;
|
||||
if(op.xmmubyte(0x1) & 0x80) result |= 0x0002;
|
||||
if(op.xmmubyte(0x2) & 0x80) result |= 0x0004;
|
||||
if(op.xmmubyte(0x3) & 0x80) result |= 0x0008;
|
||||
if(op.xmmubyte(0x4) & 0x80) result |= 0x0010;
|
||||
if(op.xmmubyte(0x5) & 0x80) result |= 0x0020;
|
||||
if(op.xmmubyte(0x6) & 0x80) result |= 0x0040;
|
||||
if(op.xmmubyte(0x7) & 0x80) result |= 0x0080;
|
||||
if(op.xmmubyte(0x8) & 0x80) result |= 0x0100;
|
||||
if(op.xmmubyte(0x9) & 0x80) result |= 0x0200;
|
||||
if(op.xmmubyte(0xA) & 0x80) result |= 0x0400;
|
||||
if(op.xmmubyte(0xB) & 0x80) result |= 0x0800;
|
||||
if(op.xmmubyte(0xC) & 0x80) result |= 0x1000;
|
||||
if(op.xmmubyte(0xD) & 0x80) result |= 0x2000;
|
||||
if(op.xmmubyte(0xE) & 0x80) result |= 0x4000;
|
||||
if(op.xmmubyte(0xF) & 0x80) result |= 0x8000;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
BX_WRITE_32BIT_REGZ(i->nnn(), result);
|
||||
|
||||
#else
|
||||
BX_INFO(("SHUFPD_VpdWpdIb: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 60 */
|
||||
void BX_CPU_C::PUNPCKLBW_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmmubyte(0x0) = op1.xmmubyte(0);
|
||||
result.xmmubyte(0x1) = op2.xmmubyte(0);
|
||||
result.xmmubyte(0x2) = op1.xmmubyte(1);
|
||||
result.xmmubyte(0x3) = op2.xmmubyte(1);
|
||||
result.xmmubyte(0x4) = op1.xmmubyte(2);
|
||||
result.xmmubyte(0x5) = op2.xmmubyte(2);
|
||||
result.xmmubyte(0x6) = op1.xmmubyte(3);
|
||||
result.xmmubyte(0x7) = op2.xmmubyte(3);
|
||||
result.xmmubyte(0x8) = op1.xmmubyte(4);
|
||||
result.xmmubyte(0x9) = op2.xmmubyte(4);
|
||||
result.xmmubyte(0xA) = op1.xmmubyte(5);
|
||||
result.xmmubyte(0xB) = op2.xmmubyte(5);
|
||||
result.xmmubyte(0xC) = op1.xmmubyte(6);
|
||||
result.xmmubyte(0xD) = op2.xmmubyte(6);
|
||||
result.xmmubyte(0xE) = op1.xmmubyte(7);
|
||||
result.xmmubyte(0xF) = op2.xmmubyte(7);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PUNPCKLBW_VdqWq: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 61 */
|
||||
void BX_CPU_C::PUNPCKLWD_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm16u(0) = op1.xmm16u(0);
|
||||
result.xmm16u(1) = op2.xmm16u(0);
|
||||
result.xmm16u(2) = op1.xmm16u(1);
|
||||
result.xmm16u(3) = op2.xmm16u(1);
|
||||
result.xmm16u(4) = op1.xmm16u(2);
|
||||
result.xmm16u(5) = op2.xmm16u(2);
|
||||
result.xmm16u(6) = op1.xmm16u(3);
|
||||
result.xmm16u(7) = op2.xmm16u(3);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PUNPCKLWD_VdqWq: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* UNPCKLPS: 0F 14 */
|
||||
/* PUNPCKLDQ: 66 0F 62 */
|
||||
|
||||
void BX_CPU_C::UNPCKLPS_VpsWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm32u(0) = op1.xmm32u(0);
|
||||
result.xmm32u(1) = op2.xmm32u(0);
|
||||
result.xmm32u(2) = op1.xmm32u(1);
|
||||
result.xmm32u(3) = op2.xmm32u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("UNPCKLPS_VpsWq: required SSE, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 68 */
|
||||
void BX_CPU_C::PUNPCKHBW_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmmubyte(0x0) = op1.xmmubyte(0x8);
|
||||
result.xmmubyte(0x1) = op2.xmmubyte(0x8);
|
||||
result.xmmubyte(0x2) = op1.xmmubyte(0x9);
|
||||
result.xmmubyte(0x3) = op2.xmmubyte(0x9);
|
||||
result.xmmubyte(0x4) = op1.xmmubyte(0xA);
|
||||
result.xmmubyte(0x5) = op2.xmmubyte(0xA);
|
||||
result.xmmubyte(0x6) = op1.xmmubyte(0xB);
|
||||
result.xmmubyte(0x7) = op2.xmmubyte(0xB);
|
||||
result.xmmubyte(0x8) = op1.xmmubyte(0xC);
|
||||
result.xmmubyte(0x9) = op2.xmmubyte(0xC);
|
||||
result.xmmubyte(0xA) = op1.xmmubyte(0xD);
|
||||
result.xmmubyte(0xB) = op2.xmmubyte(0xD);
|
||||
result.xmmubyte(0xC) = op1.xmmubyte(0xE);
|
||||
result.xmmubyte(0xD) = op2.xmmubyte(0xE);
|
||||
result.xmmubyte(0xE) = op1.xmmubyte(0xF);
|
||||
result.xmmubyte(0xF) = op2.xmmubyte(0xF);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PUNPCKHBW_VdqWq: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 69 */
|
||||
void BX_CPU_C::PUNPCKHWD_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm16u(0) = op1.xmm16u(4);
|
||||
result.xmm16u(1) = op2.xmm16u(4);
|
||||
result.xmm16u(2) = op1.xmm16u(5);
|
||||
result.xmm16u(3) = op2.xmm16u(5);
|
||||
result.xmm16u(4) = op1.xmm16u(6);
|
||||
result.xmm16u(5) = op2.xmm16u(6);
|
||||
result.xmm16u(6) = op1.xmm16u(7);
|
||||
result.xmm16u(7) = op2.xmm16u(7);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PUNPCKHWD_VdqWq: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* UNPCKHPS: 0F 15 */
|
||||
/* PUNPCKHDQ: 66 0F 6A */
|
||||
|
||||
void BX_CPU_C::UNPCKHPS_VpsWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm32u(0) = op1.xmm32u(2);
|
||||
result.xmm32u(1) = op2.xmm32u(2);
|
||||
result.xmm32u(2) = op1.xmm32u(3);
|
||||
result.xmm32u(3) = op2.xmm32u(3);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("UNPCKHPS_VpsWq: required SSE, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* UNPCKLPD: 66 0F 14 */
|
||||
/* PUNPCKLQDQ: 66 0F 6C */
|
||||
|
||||
void BX_CPU_C::PUNPCKLQDQ_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
op1.xmm64u(1) = op2.xmm64u(0);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("PUNPCKLQDQ_VdqWq: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* UNPCKHPD: 66 0F 15 */
|
||||
/* PUNPCKHQDQ: 66 0F 6D */
|
||||
|
||||
void BX_CPU_C::PUNPCKHQDQ_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = op1.xmm64u(1);
|
||||
result.xmm64u(1) = op2.xmm64u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PUNPCKHQDQ_VdqWq: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 70 */
|
||||
void BX_CPU_C::PSHUFD_VdqWdqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op, result;
|
||||
Bit8u order = i->Ib();
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
|
||||
result.xmm32u(0) = op.xmm32u((order >> 0) & 0x3);
|
||||
result.xmm32u(1) = op.xmm32u((order >> 2) & 0x3);
|
||||
result.xmm32u(2) = op.xmm32u((order >> 4) & 0x3);
|
||||
result.xmm32u(3) = op.xmm32u((order >> 6) & 0x3);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PSHUFD_VdqWdqIb: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* F2 0F 70 */
|
||||
void BX_CPU_C::PSHUFHW_VqWqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op, result;
|
||||
Bit8u order = i->Ib();
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = op.xmm64u(0);
|
||||
result.xmm16u(4) = op.xmm16u(4 + ((order >> 0) & 0x3));
|
||||
result.xmm16u(5) = op.xmm16u(4 + ((order >> 2) & 0x3));
|
||||
result.xmm16u(6) = op.xmm16u(4 + ((order >> 4) & 0x3));
|
||||
result.xmm16u(7) = op.xmm16u(4 + ((order >> 6) & 0x3));
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PSHUFHW_VqWqIb: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* F3 0F 70 */
|
||||
void BX_CPU_C::PSHUFLW_VqWqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op, result;
|
||||
Bit8u order = i->Ib();
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
|
||||
result.xmm16u(0) = op.xmm16u((order >> 0) & 0x3);
|
||||
result.xmm16u(1) = op.xmm16u((order >> 2) & 0x3);
|
||||
result.xmm16u(2) = op.xmm16u((order >> 4) & 0x3);
|
||||
result.xmm16u(3) = op.xmm16u((order >> 6) & 0x3);
|
||||
result.xmm64u(1) = op.xmm64u(1);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PSHUFLW_VqWqIb: required SSE, use --enable-sse option"));
|
||||
BX_INFO(("PMOVMSKB_GdUdq: required SSE2, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
@ -1567,3 +1168,429 @@ void BX_CPU_C::MOVNTPS_MdqVps(bxInstruction_c *i)
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ************************** */
|
||||
/* 3-BYTE-OPCODE INSTRUCTIONS */
|
||||
/* ************************** */
|
||||
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
|
||||
/* 66 0F 38 20 */
|
||||
void BX_CPU_C::PMOVSXBW_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BxPackedXmmRegister result;
|
||||
Bit64u val64;
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
val64 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_qword(i->seg(), RMAddr(i), &val64);
|
||||
}
|
||||
|
||||
result.xmm16u(0) = (Bit8s) (val64 & 0xFF);
|
||||
result.xmm16u(1) = (Bit8s) ((val64 >> 8) & 0xFF);
|
||||
result.xmm16u(2) = (Bit8s) ((val64 >> 16) & 0xFF);
|
||||
result.xmm16u(3) = (Bit8s) ((val64 >> 24) & 0xFF);
|
||||
result.xmm16u(4) = (Bit8s) ((val64 >> 32) & 0xFF);
|
||||
result.xmm16u(5) = (Bit8s) ((val64 >> 40) & 0xFF);
|
||||
result.xmm16u(6) = (Bit8s) ((val64 >> 48) & 0xFF);
|
||||
result.xmm16u(7) = (Bit8s) (val64 >> 56);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMOVSXBW_VdqWq: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 38 21 */
|
||||
void BX_CPU_C::PMOVSXBD_VdqWd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BxPackedXmmRegister result;
|
||||
Bit32u val32;
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
val32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_dword(i->seg(), RMAddr(i), &val32);
|
||||
}
|
||||
|
||||
result.xmm32u(0) = (Bit8s) (val32 & 0xFF);
|
||||
result.xmm32u(1) = (Bit8s) ((val32 >> 8) & 0xFF);
|
||||
result.xmm32u(2) = (Bit8s) ((val32 >> 16) & 0xFF);
|
||||
result.xmm32u(3) = (Bit8s) (val32 >> 24);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMOVSXBD_VdqWd: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 38 22 */
|
||||
void BX_CPU_C::PMOVSXBQ_VdqWw(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BxPackedXmmRegister result;
|
||||
Bit16u val16;
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
val16 = BX_READ_XMM_REG_LO_WORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_word(i->seg(), RMAddr(i), &val16);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = (Bit8s) (val16 & 0xFF);
|
||||
result.xmm64u(1) = (Bit8s) (val16 >> 8);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMOVSXBQ_VdqWw: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 38 23 */
|
||||
void BX_CPU_C::PMOVSXWD_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BxPackedXmmRegister result;
|
||||
Bit64u val64;
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
val64 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_qword(i->seg(), RMAddr(i), &val64);
|
||||
}
|
||||
|
||||
result.xmm32u(0) = (Bit16s) (val64 & 0xFFFF);
|
||||
result.xmm32u(1) = (Bit16s) ((val64 >> 16) & 0xFFFF);
|
||||
result.xmm32u(2) = (Bit16s) ((val64 >> 32) & 0xFFFF);
|
||||
result.xmm32u(3) = (Bit16s) (val64 >> 48);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMOVSXWD_VdqWq: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 38 24 */
|
||||
void BX_CPU_C::PMOVSXWQ_VdqWd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BxPackedXmmRegister result;
|
||||
Bit32u val32;
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
val32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_dword(i->seg(), RMAddr(i), &val32);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = (Bit16s) (val32 & 0xFFFF);
|
||||
result.xmm64u(1) = (Bit16s) (val32 >> 16);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMOVSXWQ_VdqWd: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 38 25 */
|
||||
void BX_CPU_C::PMOVSXDQ_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BxPackedXmmRegister result;
|
||||
Bit64u val64;
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
val64 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_qword(i->seg(), RMAddr(i), &val64);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = (Bit32s) (val64 & 0xFFFFFFFF);
|
||||
result.xmm64u(1) = (Bit32s) (val64 >> 32);
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMOVSXDQ_VdqWq: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 38 30 */
|
||||
void BX_CPU_C::PMOVZXBW_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BxPackedXmmRegister result;
|
||||
Bit64u val64;
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
val64 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_qword(i->seg(), RMAddr(i), &val64);
|
||||
}
|
||||
|
||||
result.xmm16u(0) = val64 & 0xFF;
|
||||
result.xmm16u(1) = (val64 >> 8) & 0xFF;
|
||||
result.xmm16u(2) = (val64 >> 16) & 0xFF;
|
||||
result.xmm16u(3) = (val64 >> 24) & 0xFF;
|
||||
result.xmm16u(4) = (val64 >> 32) & 0xFF;
|
||||
result.xmm16u(5) = (val64 >> 40) & 0xFF;
|
||||
result.xmm16u(6) = (val64 >> 48) & 0xFF;
|
||||
result.xmm16u(7) = val64 >> 56;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMOVZXBW_VdqWq: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 38 31 */
|
||||
void BX_CPU_C::PMOVZXBD_VdqWd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BxPackedXmmRegister result;
|
||||
Bit32u val32;
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
val32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_dword(i->seg(), RMAddr(i), &val32);
|
||||
}
|
||||
|
||||
result.xmm32u(0) = val32 & 0xFF;
|
||||
result.xmm32u(1) = (val32 >> 8) & 0xFF;
|
||||
result.xmm32u(2) = (val32 >> 16) & 0xFF;
|
||||
result.xmm32u(3) = val32 >> 24;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMOVZXBD_VdqWd: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 38 32 */
|
||||
void BX_CPU_C::PMOVZXBQ_VdqWw(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BxPackedXmmRegister result;
|
||||
Bit16u val16;
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
val16 = BX_READ_XMM_REG_LO_WORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_word(i->seg(), RMAddr(i), &val16);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = val16 & 0xFF;
|
||||
result.xmm64u(1) = val16 >> 8;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMOVZXBQ_VdqWw: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 38 33 */
|
||||
void BX_CPU_C::PMOVZXWD_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BxPackedXmmRegister result;
|
||||
Bit64u val64;
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
val64 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_qword(i->seg(), RMAddr(i), &val64);
|
||||
}
|
||||
|
||||
result.xmm32u(0) = val64 & 0xFFFF;
|
||||
result.xmm32u(1) = (val64 >> 16) & 0xFFFF;
|
||||
result.xmm32u(2) = (val64 >> 32) & 0xFFFF;
|
||||
result.xmm32u(3) = val64 >> 48;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMOVZXWD_VdqWq: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 38 34 */
|
||||
void BX_CPU_C::PMOVZXWQ_VdqWd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BxPackedXmmRegister result;
|
||||
Bit32u val32;
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
val32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_dword(i->seg(), RMAddr(i), &val32);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = val32 & 0xFFFF;
|
||||
result.xmm64u(1) = val32 >> 16;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMOVZXWQ_VdqWd: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 38 35 */
|
||||
void BX_CPU_C::PMOVZXDQ_VdqWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BxPackedXmmRegister result;
|
||||
Bit64u val64;
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
val64 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_qword(i->seg(), RMAddr(i), &val64);
|
||||
}
|
||||
|
||||
result.xmm64u(0) = val64 & 0xFFFFFFFF;
|
||||
result.xmm64u(1) = val64 >> 32;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PMOVZXDQ_VdqWq: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 3A 0F */
|
||||
void BX_CPU_C::PALIGNR_VdqWdqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
unsigned shift = i->Ib() * 8;
|
||||
|
||||
if(shift == 0) {
|
||||
result.xmm64u(0) = op2.xmm64u(0);
|
||||
result.xmm64u(1) = op2.xmm64u(1);
|
||||
}
|
||||
else if(shift < 64) {
|
||||
result.xmm64u(0) = (op2.xmm64u(0) >> shift) | (op2.xmm64u(1) << (64-shift));
|
||||
result.xmm64u(1) = (op2.xmm64u(1) >> shift) | (op1.xmm64u(0) << (64-shift));
|
||||
}
|
||||
else if(shift == 64) {
|
||||
result.xmm64u(0) = op2.xmm64u(1);
|
||||
result.xmm64u(1) = op1.xmm64u(0);
|
||||
}
|
||||
else if(shift < 128) {
|
||||
shift -= 64;
|
||||
result.xmm64u(0) = (op2.xmm64u(1) >> shift) | (op1.xmm64u(0) << (64-shift));
|
||||
result.xmm64u(1) = (op1.xmm64u(0) >> shift) | (op1.xmm64u(1) << (64-shift));
|
||||
}
|
||||
else if(shift == 128) {
|
||||
result.xmm64u(0) = op1.xmm64u(0);
|
||||
result.xmm64u(1) = op1.xmm64u(1);
|
||||
}
|
||||
else if(shift < 192) {
|
||||
shift -= 128;
|
||||
result.xmm64u(0) = (op1.xmm64u(0) >> shift) | (op1.xmm64u(1) << (64-shift));
|
||||
result.xmm64u(1) = (op1.xmm64u(1) >> shift);
|
||||
}
|
||||
else if(shift < 256) {
|
||||
result.xmm64u(0) = op1.xmm64u(1) >> (shift - 192);
|
||||
result.xmm64u(1) = 0;
|
||||
}
|
||||
else {
|
||||
result.xmm64u(0) = 0;
|
||||
result.xmm64u(1) = 0;
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("PALIGNR_VdqWdqIb: required SSE3E, use --enable-sse and --enable-sse-extension options"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif // BX_SUPPORT_SSE >= 4 || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: sse_pfp.cc,v 1.29 2007-03-23 21:27:12 sshwarts Exp $
|
||||
// $Id: sse_pfp.cc,v 1.30 2007-04-19 16:12:20 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2003 Stanislav Shwartsman
|
||||
@ -27,6 +27,8 @@
|
||||
|
||||
#if BX_SUPPORT_SSE
|
||||
|
||||
#include "fpu/softfloat-specialize.h"
|
||||
|
||||
void BX_CPU_C::check_exceptionsSSE(int exceptions_flags)
|
||||
{
|
||||
int unmasked = ~(MXCSR.get_exceptions_masks()) & exceptions_flags;
|
||||
@ -73,7 +75,6 @@ static float32_compare_method compare32[4] = {
|
||||
};
|
||||
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
|
||||
/* Comparison predicate for CMPSD/CMPPD instructions */
|
||||
static float64_compare_method compare64[4] = {
|
||||
float64_eq,
|
||||
@ -81,11 +82,10 @@ static float64_compare_method compare64[4] = {
|
||||
float64_le,
|
||||
float64_unordered
|
||||
};
|
||||
|
||||
#endif /* BX_SUPPORT_SSE >= 2 */
|
||||
|
||||
#endif
|
||||
|
||||
#endif // BX_SUPPORT_SSE
|
||||
|
||||
/*
|
||||
* Opcode: 0F 2A
|
||||
* Convert two 32bit signed integers from MMX/MEM to two single precision FP
|
||||
@ -170,7 +170,7 @@ void BX_CPU_C::CVTSI2SD_VsdEd(bxInstruction_c *i)
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
Float64 result;
|
||||
float64 result;
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->os64L()) /* 64 bit operand size mode */
|
||||
@ -227,7 +227,7 @@ void BX_CPU_C::CVTSI2SS_VssEd(bxInstruction_c *i)
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
Float32 result;
|
||||
float32 result;
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->os64L()) /* 64 bit operand size mode */
|
||||
@ -297,8 +297,8 @@ void BX_CPU_C::CVTTPS2PI_PqWps(bxInstruction_c *i)
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
|
||||
Float32 r0 = (Float32)(op & 0xFFFFFFFF);
|
||||
Float32 r1 = (Float32)(op >> 32);
|
||||
float32 r0 = (float32)(op & 0xFFFFFFFF);
|
||||
float32 r1 = (float32)(op >> 32);
|
||||
|
||||
MMXUD0(result) = float32_to_int32_round_to_zero(r0, status_word);
|
||||
MMXUD1(result) = float32_to_int32_round_to_zero(r1, status_word);
|
||||
@ -360,7 +360,7 @@ void BX_CPU_C::CVTTSD2SI_GdWsd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op;
|
||||
float64 op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -406,7 +406,7 @@ void BX_CPU_C::CVTTSS2SI_GdWss(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op;
|
||||
float32 op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -469,8 +469,8 @@ void BX_CPU_C::CVTPS2PI_PqWps(bxInstruction_c *i)
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
|
||||
Float32 r0 = (Float32)(op & 0xFFFFFFFF);
|
||||
Float32 r1 = (Float32)(op >> 32);
|
||||
float32 r0 = (float32)(op & 0xFFFFFFFF);
|
||||
float32 r1 = (float32)(op >> 32);
|
||||
|
||||
MMXUD0(result) = float32_to_int32(r0, status_word);
|
||||
MMXUD1(result) = float32_to_int32(r1, status_word);
|
||||
@ -534,7 +534,7 @@ void BX_CPU_C::CVTSD2SI_GdWsd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op;
|
||||
float64 op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -581,7 +581,7 @@ void BX_CPU_C::CVTSS2SI_GdWss(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op;
|
||||
float32 op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -641,8 +641,8 @@ void BX_CPU_C::CVTPS2PD_VpsWps(bxInstruction_c *i)
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
|
||||
Float32 r0 = (Float32)(op & 0xFFFFFFFF);
|
||||
Float32 r1 = (Float32)(op >> 32);
|
||||
float32 r0 = (float32)(op & 0xFFFFFFFF);
|
||||
float32 r1 = (float32)(op >> 32);
|
||||
|
||||
if (MXCSR.get_DAZ()) {
|
||||
r0 = handleDAZ(r0);
|
||||
@ -722,8 +722,8 @@ void BX_CPU_C::CVTSD2SS_VsdWsd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op;
|
||||
Float32 result;
|
||||
float64 op;
|
||||
float32 result;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -757,8 +757,8 @@ void BX_CPU_C::CVTSS2SD_VssWss(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op;
|
||||
Float64 result;
|
||||
float32 op;
|
||||
float64 result;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -1034,7 +1034,7 @@ void BX_CPU_C::UCOMISS_VssWss(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2;
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -1073,7 +1073,7 @@ void BX_CPU_C::UCOMISD_VsdWsd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2;
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -1112,7 +1112,7 @@ void BX_CPU_C::COMISS_VpsWps(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2;
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -1151,7 +1151,7 @@ void BX_CPU_C::COMISD_VpdWpd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2;
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -1260,10 +1260,8 @@ void BX_CPU_C::SQRTPD_VpdWpd(bxInstruction_c *i)
|
||||
op.xmm64u(1) = handleDAZ(op.xmm64u(1));
|
||||
}
|
||||
|
||||
result.xmm64u(0) =
|
||||
float64_sqrt(op.xmm64u(0), status_word);
|
||||
result.xmm64u(1) =
|
||||
float64_sqrt(op.xmm64u(1), status_word);
|
||||
result.xmm64u(0) = float64_sqrt(op.xmm64u(0), status_word);
|
||||
result.xmm64u(1) = float64_sqrt(op.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
@ -1284,7 +1282,7 @@ void BX_CPU_C::SQRTSD_VsdWsd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op, result;
|
||||
float64 op, result;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -1318,7 +1316,7 @@ void BX_CPU_C::SQRTSS_VssWss(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op, result;
|
||||
float32 op, result;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -1428,10 +1426,8 @@ void BX_CPU_C::ADDPD_VpdWpd(bxInstruction_c *i)
|
||||
op2.xmm64u(1) = handleDAZ(op2.xmm64u(1));
|
||||
}
|
||||
|
||||
result.xmm64u(0) =
|
||||
float64_add(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
result.xmm64u(1) =
|
||||
float64_add(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
result.xmm64u(0) = float64_add(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
result.xmm64u(1) = float64_add(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
@ -1452,7 +1448,7 @@ void BX_CPU_C::ADDSD_VsdWsd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2, result;
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -1492,7 +1488,7 @@ void BX_CPU_C::ADDSS_VssWss(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2, result;
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -1608,10 +1604,8 @@ void BX_CPU_C::MULPD_VpdWpd(bxInstruction_c *i)
|
||||
op2.xmm64u(1) = handleDAZ(op2.xmm64u(1));
|
||||
}
|
||||
|
||||
result.xmm64u(0) =
|
||||
float64_mul(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
result.xmm64u(1) =
|
||||
float64_mul(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
result.xmm64u(0) = float64_mul(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
result.xmm64u(1) = float64_mul(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
@ -1632,7 +1626,7 @@ void BX_CPU_C::MULSD_VsdWsd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2, result;
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -1672,7 +1666,7 @@ void BX_CPU_C::MULSS_VssWss(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2, result;
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -1788,10 +1782,8 @@ void BX_CPU_C::SUBPD_VpdWpd(bxInstruction_c *i)
|
||||
op2.xmm64u(1) = handleDAZ(op2.xmm64u(1));
|
||||
}
|
||||
|
||||
result.xmm64u(0) =
|
||||
float64_sub(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
result.xmm64u(1) =
|
||||
float64_sub(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
result.xmm64u(0) = float64_sub(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
result.xmm64u(1) = float64_sub(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
@ -1812,7 +1804,7 @@ void BX_CPU_C::SUBSD_VsdWsd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2, result;
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -1852,7 +1844,7 @@ void BX_CPU_C::SUBSS_VssWss(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2, result;
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -2000,7 +1992,7 @@ void BX_CPU_C::MINSD_VsdWsd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2;
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -2041,7 +2033,7 @@ void BX_CPU_C::MINSS_VssWss(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2;
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -2158,10 +2150,8 @@ void BX_CPU_C::DIVPD_VpdWpd(bxInstruction_c *i)
|
||||
op2.xmm64u(1) = handleDAZ(op2.xmm64u(1));
|
||||
}
|
||||
|
||||
result.xmm64u(0) =
|
||||
float64_div(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
result.xmm64u(1) =
|
||||
float64_div(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
result.xmm64u(0) = float64_div(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
result.xmm64u(1) = float64_div(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
@ -2182,7 +2172,7 @@ void BX_CPU_C::DIVSD_VsdWsd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2, result;
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -2222,7 +2212,7 @@ void BX_CPU_C::DIVSS_VssWss(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2, result;
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2, result;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -2370,7 +2360,7 @@ void BX_CPU_C::MAXSD_VsdWsd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2;
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -2411,7 +2401,7 @@ void BX_CPU_C::MAXSS_VssWss(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2;
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -2474,10 +2464,8 @@ void BX_CPU_C::HADDPD_VpdWpd(bxInstruction_c *i)
|
||||
op2.xmm64u(1) = handleDAZ(op2.xmm64u(1));
|
||||
}
|
||||
|
||||
result.xmm64u(0) =
|
||||
float64_add(op1.xmm64u(0), op1.xmm64u(1), status_word);
|
||||
result.xmm64u(1) =
|
||||
float64_add(op2.xmm64u(0), op2.xmm64u(1), status_word);
|
||||
result.xmm64u(0) = float64_add(op1.xmm64u(0), op1.xmm64u(1), status_word);
|
||||
result.xmm64u(1) = float64_add(op2.xmm64u(0), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
@ -2574,10 +2562,8 @@ void BX_CPU_C::HSUBPD_VpdWpd(bxInstruction_c *i)
|
||||
op2.xmm64u(1) = handleDAZ(op2.xmm64u(1));
|
||||
}
|
||||
|
||||
result.xmm64u(0) =
|
||||
float64_sub(op1.xmm64u(0), op1.xmm64u(1), status_word);
|
||||
result.xmm64u(1) =
|
||||
float64_sub(op2.xmm64u(0), op2.xmm64u(1), status_word);
|
||||
result.xmm64u(0) = float64_sub(op1.xmm64u(0), op1.xmm64u(1), status_word);
|
||||
result.xmm64u(1) = float64_sub(op2.xmm64u(0), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
@ -2794,7 +2780,7 @@ void BX_CPU_C::CMPSD_VsdWsdIb(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2, result = 0;
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2, result = 0;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -2853,7 +2839,7 @@ void BX_CPU_C::CMPSS_VssWssIb(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2, result = 0;
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2, result = 0;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -2934,10 +2920,8 @@ void BX_CPU_C::ADDSUBPD_VpdWpd(bxInstruction_c *i)
|
||||
op2.xmm64u(1) = handleDAZ(op2.xmm64u(1));
|
||||
}
|
||||
|
||||
result.xmm64u(0) =
|
||||
float64_sub(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
result.xmm64u(1) =
|
||||
float64_add(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
result.xmm64u(0) = float64_sub(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
result.xmm64u(1) = float64_add(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
@ -2984,14 +2968,10 @@ void BX_CPU_C::ADDSUBPS_VpsWps(bxInstruction_c *i)
|
||||
op2.xmm32u(3) = handleDAZ(op2.xmm32u(3));
|
||||
}
|
||||
|
||||
result.xmm32u(0) =
|
||||
float32_sub(op1.xmm32u(0), op2.xmm32u(0), status_word);
|
||||
result.xmm32u(1) =
|
||||
float32_add(op1.xmm32u(1), op2.xmm32u(1), status_word);
|
||||
result.xmm32u(2) =
|
||||
float32_sub(op1.xmm32u(2), op2.xmm32u(2), status_word);
|
||||
result.xmm32u(3) =
|
||||
float32_add(op1.xmm32u(3), op2.xmm32u(3), status_word);
|
||||
result.xmm32u(0) = float32_sub(op1.xmm32u(0), op2.xmm32u(0), status_word);
|
||||
result.xmm32u(1) = float32_add(op1.xmm32u(1), op2.xmm32u(1), status_word);
|
||||
result.xmm32u(2) = float32_sub(op1.xmm32u(2), op2.xmm32u(2), status_word);
|
||||
result.xmm32u(3) = float32_add(op1.xmm32u(3), op2.xmm32u(3), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
@ -3001,3 +2981,319 @@ void BX_CPU_C::ADDSUBPS_VpsWps(bxInstruction_c *i)
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
|
||||
/* 66 0F 3A 08 */
|
||||
void BX_CPU_C::ROUNDPS_VpsWpsIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op, result;
|
||||
Bit8u control = i->Ib();
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
|
||||
// override MXCSR rounding mode with control coming from imm8
|
||||
if ((control & 0x4) == 0)
|
||||
status_word.float_rounding_mode = control & 0x3;
|
||||
|
||||
if (MXCSR.get_DAZ()) {
|
||||
op.xmm32u(0) = handleDAZ(op.xmm32u(0));
|
||||
op.xmm32u(1) = handleDAZ(op.xmm32u(1));
|
||||
op.xmm32u(2) = handleDAZ(op.xmm32u(2));
|
||||
op.xmm32u(3) = handleDAZ(op.xmm32u(3));
|
||||
}
|
||||
|
||||
for (unsigned j=0; j < 4; j++) {
|
||||
if (float32_is_nan(op.xmm32u(0)))
|
||||
result.xmm32u(j) = propagateFloat32NaN(op.xmm32u(j), status_word);
|
||||
else
|
||||
result.xmm32u(j) = float32_to_int32(op.xmm32u(j), status_word);
|
||||
}
|
||||
|
||||
// ignore precision exception result
|
||||
if (control & 0x8)
|
||||
status_word.float_exception_flags &= ~float_flag_inexact;
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("ROUNDPS_VpsWpsIb: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 3A 09 */
|
||||
void BX_CPU_C::ROUNDPD_VpdWpdIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op, result;
|
||||
Bit8u control = i->Ib();
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op);
|
||||
}
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
|
||||
// override MXCSR rounding mode with control coming from imm8
|
||||
if ((control & 0x4) == 0)
|
||||
status_word.float_rounding_mode = control & 0x3;
|
||||
|
||||
if (MXCSR.get_DAZ()) {
|
||||
op.xmm64u(0) = handleDAZ(op.xmm64u(0));
|
||||
op.xmm64u(1) = handleDAZ(op.xmm64u(1));
|
||||
}
|
||||
|
||||
for (unsigned j=0; j < 2; j++) {
|
||||
if (float64_is_nan(op.xmm64u(0)))
|
||||
result.xmm64u(j) = propagateFloat64NaN(op.xmm64u(j), status_word);
|
||||
else
|
||||
result.xmm64u(j) = float64_to_int64(op.xmm64u(j), status_word);
|
||||
}
|
||||
|
||||
// ignore precision exception result
|
||||
if (control & 0x8)
|
||||
status_word.float_exception_flags &= ~float_flag_inexact;
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("ROUNDPD_VpdWpdIb: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 3A 0A */
|
||||
void BX_CPU_C::ROUNDSS_VssWssIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Bit32u result;
|
||||
Bit8u control = i->Ib();
|
||||
float32 op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_dword(i->seg(), RMAddr(i), &op);
|
||||
}
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
|
||||
// override MXCSR rounding mode with control coming from imm8
|
||||
if ((control & 0x4) == 0)
|
||||
status_word.float_rounding_mode = control & 0x3;
|
||||
|
||||
if (MXCSR.get_DAZ()) op = handleDAZ(op);
|
||||
|
||||
if (float32_is_nan(op))
|
||||
result = propagateFloat32NaN(op, status_word);
|
||||
else
|
||||
result = float32_to_int32(op, status_word);
|
||||
|
||||
// ignore precision exception result
|
||||
if (control & 0x8)
|
||||
status_word.float_exception_flags &= ~float_flag_inexact;
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("ROUNDSS_VssWssIb: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* 66 0F 3A 0B */
|
||||
void BX_CPU_C::ROUNDSD_VsdWsdIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Bit64u result;
|
||||
Bit8u control = i->Ib();
|
||||
float64 op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_qword(i->seg(), RMAddr(i), &op);
|
||||
}
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
|
||||
// override MXCSR rounding mode with control coming from imm8
|
||||
if ((control & 0x4) == 0)
|
||||
status_word.float_rounding_mode = control & 0x3;
|
||||
|
||||
if (MXCSR.get_DAZ()) op = handleDAZ(op);
|
||||
|
||||
if (float64_is_nan(op))
|
||||
result = propagateFloat64NaN(op, status_word);
|
||||
else
|
||||
result = float64_to_int64(op, status_word);
|
||||
|
||||
// ignore precision exception result
|
||||
if (control & 0x8)
|
||||
status_word.float_exception_flags &= ~float_flag_inexact;
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("ROUNDSD_VsdWsdIb: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Opcode: 66 0F 3A 40
|
||||
* Selectively multiply packed SP floating-point values from xmm1 with
|
||||
* packed SP floating-point values from xmm2, add and selectively
|
||||
* store the packed SP floating-point values or zero values to xmm1
|
||||
*/
|
||||
void BX_CPU_C::DPPS_VpsWpsIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, tmp;
|
||||
Bit8u mask = i->Ib();
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
|
||||
if (MXCSR.get_DAZ()) {
|
||||
op1.xmm32u(0) = handleDAZ(op1.xmm32u(0));
|
||||
op1.xmm32u(1) = handleDAZ(op1.xmm32u(1));
|
||||
op1.xmm32u(2) = handleDAZ(op1.xmm32u(2));
|
||||
op1.xmm32u(3) = handleDAZ(op1.xmm32u(3));
|
||||
|
||||
op2.xmm32u(0) = handleDAZ(op2.xmm32u(0));
|
||||
op2.xmm32u(1) = handleDAZ(op2.xmm32u(1));
|
||||
op2.xmm32u(2) = handleDAZ(op2.xmm32u(2));
|
||||
op2.xmm32u(3) = handleDAZ(op2.xmm32u(3));
|
||||
}
|
||||
|
||||
tmp.xmm64u(0) = tmp.xmm64u(1) = 0;
|
||||
|
||||
if (mask & 0x10)
|
||||
tmp.xmm32u(0) = float32_mul(op1.xmm32u(0), op2.xmm32u(0), status_word);
|
||||
if (mask & 0x20)
|
||||
tmp.xmm32u(1) = float32_mul(op1.xmm32u(1), op2.xmm32u(1), status_word);
|
||||
if (mask & 0x40)
|
||||
tmp.xmm32u(2) = float32_mul(op1.xmm32u(2), op2.xmm32u(2), status_word);
|
||||
if (mask & 0x80)
|
||||
tmp.xmm32u(3) = float32_mul(op1.xmm32u(3), op2.xmm32u(3), status_word);
|
||||
|
||||
float32 r1 = float32_add(tmp.xmm32u(0), tmp.xmm32u(1), status_word);
|
||||
float32 r2 = float32_add(tmp.xmm32u(2), tmp.xmm32u(3), status_word);
|
||||
float32 r = float32_add(r1, r2, status_word);
|
||||
|
||||
op1.xmm64u(0) = op1.xmm64u(1) = 0;
|
||||
|
||||
if (mask & 0x01) op1.xmm32u(0) = r;
|
||||
if (mask & 0x02) op1.xmm32u(1) = r;
|
||||
if (mask & 0x04) op1.xmm32u(2) = r;
|
||||
if (mask & 0x08) op1.xmm32u(3) = r;
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("DPPS_VpsWpsIb: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Opcode: 66 0F 3A 41
|
||||
* Selectively multiply packed DP floating-point values from xmm1 with
|
||||
* packed DP floating-point values from xmm2, add and selectively
|
||||
* store the packed DP floating-point values or zero values to xmm1
|
||||
*/
|
||||
void BX_CPU_C::DPPD_VpdWpdIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 4
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, tmp;
|
||||
Bit8u mask = i->Ib();
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
|
||||
}
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
|
||||
if (MXCSR.get_DAZ()) {
|
||||
op1.xmm64u(0) = handleDAZ(op1.xmm64u(0));
|
||||
op1.xmm64u(1) = handleDAZ(op1.xmm64u(1));
|
||||
|
||||
op2.xmm64u(0) = handleDAZ(op2.xmm64u(0));
|
||||
op2.xmm64u(1) = handleDAZ(op2.xmm64u(1));
|
||||
}
|
||||
|
||||
tmp.xmm64u(0) = tmp.xmm64u(1) = 0;
|
||||
|
||||
if (mask & 0x10)
|
||||
tmp.xmm64u(0) = float64_mul(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
if (mask & 0x20)
|
||||
tmp.xmm64u(1) = float64_mul(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
|
||||
float64 result = float64_add(tmp.xmm64u(0), tmp.xmm64u(1), status_word);
|
||||
|
||||
op1.xmm64u(0) = op1.xmm64u(1) = 0;
|
||||
|
||||
if (mask & 0x01) op1.xmm64u(0) = result;
|
||||
if (mask & 0x02) op1.xmm64u(1) = result;
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("DPPD_VpdWpdIb: required SSE4, use --enable-sse option"));
|
||||
UndefinedOpcode(i);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif // BX_SUPPORT_SSE >= 4 || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: sse_rcp.cc,v 1.11 2007-03-23 21:27:12 sshwarts Exp $
|
||||
// $Id: sse_rcp.cc,v 1.12 2007-04-19 16:12:20 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2003 Stanislav Shwartsman
|
||||
@ -29,7 +29,7 @@
|
||||
|
||||
#include "fpu/softfloat-specialize.h"
|
||||
|
||||
BX_CPP_INLINE Float32 convert_to_QNaN(Float32 op)
|
||||
BX_CPP_INLINE float32 convert_to_QNaN(float32 op)
|
||||
{
|
||||
return op | 0x00400000;
|
||||
}
|
||||
@ -294,7 +294,7 @@ static Bit16u rcp_table[2048] = {
|
||||
};
|
||||
|
||||
// approximate reciprocal of scalar single precision FP
|
||||
static Float32 approximate_rcp(Float32 op)
|
||||
static float32 approximate_rcp(float32 op)
|
||||
{
|
||||
float_class_t op_class = float32_class(op);
|
||||
|
||||
@ -380,7 +380,7 @@ void BX_CPU_C::RCPSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
Float32 op;
|
||||
float32 op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -391,7 +391,7 @@ void BX_CPU_C::RCPSS_VssWss(bxInstruction_c *i)
|
||||
read_virtual_dword(i->seg(), RMAddr(i), &op);
|
||||
}
|
||||
|
||||
Float32 result = approximate_rcp(op);
|
||||
float32 result = approximate_rcp(op);
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), result);
|
||||
|
||||
#else
|
||||
@ -668,7 +668,7 @@ Bit16u rsqrt_table1[1024] =
|
||||
|
||||
|
||||
// approximate reciprocal sqrt of scalar single precision FP
|
||||
static Float32 approximate_rsqrt(Float32 op)
|
||||
static float32 approximate_rsqrt(float32 op)
|
||||
{
|
||||
float_class_t op_class = float32_class(op);
|
||||
|
||||
@ -729,7 +729,7 @@ void BX_CPU_C::RSQRTSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
Float32 op;
|
||||
float32 op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
@ -740,7 +740,7 @@ void BX_CPU_C::RSQRTSS_VssWss(bxInstruction_c *i)
|
||||
read_virtual_dword(i->seg(), RMAddr(i), &op);
|
||||
}
|
||||
|
||||
Float32 result = approximate_rsqrt(op);
|
||||
float32 result = approximate_rsqrt(op);
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), result);
|
||||
|
||||
#else
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: xmm.h,v 1.21 2007-03-23 21:27:12 sshwarts Exp $
|
||||
// $Id: xmm.h,v 1.22 2007-04-19 16:12:21 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2003 Stanislav Shwartsman
|
||||
@ -79,6 +79,10 @@ typedef union bx_xmm_reg_t {
|
||||
#define BX_READ_XMM_REG_LO_DWORD(index) \
|
||||
((BX_CPU_THIS_PTR xmm[index]).xmm32u(0))
|
||||
|
||||
/* read only low 16 bit of the register */
|
||||
#define BX_READ_XMM_REG_LO_WORD(index) \
|
||||
((BX_CPU_THIS_PTR xmm[index]).xmm16u(0))
|
||||
|
||||
/* short names for above macroses */
|
||||
#define BX_XMM_REG_HI_QWORD BX_READ_XMM_REG_HI_QWORD
|
||||
#define BX_XMM_REG_LO_QWORD BX_READ_XMM_REG_LO_QWORD
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: dis_decode.cc,v 1.37 2007-03-23 22:07:49 sshwarts Exp $
|
||||
// $Id: dis_decode.cc,v 1.38 2007-04-19 16:12:21 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include <stdio.h>
|
||||
@ -257,6 +257,10 @@ x86_insn disassembler::decode(bx_bool is_32, bx_bool is_64, bx_address base, bx_
|
||||
entry = &(OPCODE_TABLE(entry)[b3 & 15]);
|
||||
break;
|
||||
|
||||
case _GRP64B:
|
||||
entry = &(OPCODE_TABLE(entry)[insn.os_64]);
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("Internal disassembler error - unknown attribute !\n");
|
||||
return x86_insn(is_32, is_64);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: dis_groups.cc,v 1.35 2007-02-22 17:43:29 sshwarts Exp $
|
||||
// $Id: dis_groups.cc,v 1.36 2007-04-19 16:12:21 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include <stdio.h>
|
||||
@ -158,6 +158,38 @@ void disassembler::Eq(const x86_insn *insn)
|
||||
(this->*resolve_modrm)(insn, Q_SIZE);
|
||||
}
|
||||
|
||||
void disassembler::Hbd(const x86_insn *insn)
|
||||
{
|
||||
if (insn->mod == 3)
|
||||
dis_sprintf("%s", general_32bit_regname[insn->nnn]);
|
||||
else
|
||||
(this->*resolve_modrm)(insn, B_SIZE);
|
||||
}
|
||||
|
||||
void disassembler::Hwd(const x86_insn *insn)
|
||||
{
|
||||
if (insn->mod == 3)
|
||||
dis_sprintf("%s", general_32bit_regname[insn->nnn]);
|
||||
else
|
||||
(this->*resolve_modrm)(insn, W_SIZE);
|
||||
}
|
||||
|
||||
void disassembler::Hd(const x86_insn *insn)
|
||||
{
|
||||
if (insn->mod == 3)
|
||||
dis_sprintf("%s", general_32bit_regname[insn->nnn]);
|
||||
else
|
||||
(this->*resolve_modrm)(insn, D_SIZE);
|
||||
}
|
||||
|
||||
void disassembler::Hq(const x86_insn *insn)
|
||||
{
|
||||
if (insn->mod == 3)
|
||||
dis_sprintf("%s", general_32bit_regname[insn->nnn]);
|
||||
else
|
||||
(this->*resolve_modrm)(insn, Q_SIZE);
|
||||
}
|
||||
|
||||
// general purpose register
|
||||
void disassembler::Gb(const x86_insn *insn)
|
||||
{
|
||||
@ -361,6 +393,32 @@ void disassembler::Vsd(const x86_insn *insn) { Vq(insn); }
|
||||
void disassembler::Vps(const x86_insn *insn) { Vq(insn); }
|
||||
void disassembler::Vpd(const x86_insn *insn) { Vq(insn); }
|
||||
|
||||
void disassembler::Ww(const x86_insn *insn)
|
||||
{
|
||||
if (insn->mod == 3)
|
||||
{
|
||||
if (intel_mode)
|
||||
dis_sprintf ("xmm%d", insn->rm);
|
||||
else
|
||||
dis_sprintf("%%xmm%d", insn->rm);
|
||||
}
|
||||
else
|
||||
(this->*resolve_modrm)(insn, W_SIZE);
|
||||
}
|
||||
|
||||
void disassembler::Wd(const x86_insn *insn)
|
||||
{
|
||||
if (insn->mod == 3)
|
||||
{
|
||||
if (intel_mode)
|
||||
dis_sprintf ("xmm%d", insn->rm);
|
||||
else
|
||||
dis_sprintf("%%xmm%d", insn->rm);
|
||||
}
|
||||
else
|
||||
(this->*resolve_modrm)(insn, D_SIZE);
|
||||
}
|
||||
|
||||
void disassembler::Wq(const x86_insn *insn)
|
||||
{
|
||||
if (insn->mod == 3)
|
||||
@ -388,20 +446,7 @@ void disassembler::Wdq(const x86_insn *insn)
|
||||
}
|
||||
|
||||
void disassembler::Wsd(const x86_insn *insn) { Wq(insn); }
|
||||
|
||||
void disassembler::Wss(const x86_insn *insn)
|
||||
{
|
||||
if (insn->mod == 3)
|
||||
{
|
||||
if (intel_mode)
|
||||
dis_sprintf ("xmm%d", insn->rm);
|
||||
else
|
||||
dis_sprintf("%%xmm%d", insn->rm);
|
||||
}
|
||||
else
|
||||
(this->*resolve_modrm)(insn, D_SIZE);
|
||||
}
|
||||
|
||||
void disassembler::Wss(const x86_insn *insn) { Wd(insn); }
|
||||
void disassembler::Wpd(const x86_insn *insn) { Wdq(insn); }
|
||||
void disassembler::Wps(const x86_insn *insn) { Wdq(insn); }
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: dis_tables.h,v 1.29 2006-04-27 15:11:45 sshwarts Exp $
|
||||
// $Id: dis_tables.h,v 1.30 2007-04-19 16:12:21 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _BX_DISASM_TABLES_
|
||||
@ -14,6 +14,7 @@
|
||||
#define _GRPRM 6
|
||||
#define _GRP3BOP 7
|
||||
#define _GRP3BTAB 8
|
||||
#define _GRP64B 9
|
||||
|
||||
/* ************************************************************************ */
|
||||
#define GRPSSE(n) _GRPSSE, BxDisasmGroupSSE_##n
|
||||
@ -24,6 +25,7 @@
|
||||
#define GRP3DNOW _GRP3DNOW, BxDisasm3DNowGroup
|
||||
#define GR3BOP(n) _GRP3BOP, BxDisasm3ByteOp##n
|
||||
#define GR3BTAB(n) _GRP3BTAB, BxDisasm3ByteTable##n
|
||||
#define GR64BIT(n) _GRP64B, BxDisasmGrpOs64B_##n
|
||||
/* ************************************************************************ */
|
||||
|
||||
#define Apw &disassembler::Apw
|
||||
@ -69,6 +71,11 @@
|
||||
#define Gd &disassembler::Gd
|
||||
#define Gq &disassembler::Gq
|
||||
|
||||
#define Hbd &disassembler::Hbd
|
||||
#define Hwd &disassembler::Hwd
|
||||
#define Hd &disassembler::Hd
|
||||
#define Hq &disassembler::Hq
|
||||
|
||||
#define I1 &disassembler::I1
|
||||
#define Ib &disassembler::Ib
|
||||
#define Iw &disassembler::Iw
|
||||
@ -102,6 +109,8 @@
|
||||
#define Vpd &disassembler::Vpd
|
||||
#define Udq &disassembler::Udq
|
||||
|
||||
#define Ww &disassembler::Ww
|
||||
#define Wd &disassembler::Wd
|
||||
#define Wq &disassembler::Wq
|
||||
#define Wdq &disassembler::Wdq
|
||||
#define Wss &disassembler::Wss
|
||||
|
||||
@ -238,6 +238,34 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f380b[4] = {
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3810[4] = {
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pblendvb_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3814[4] = {
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_blendvps_Vps_Wps }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3815[4] = {
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_blendvpd_Vpd_Wpd }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3817[4] = {
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_ptest_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f381c[4] = {
|
||||
/* -- */ { 0, &Ia_pabsb_Pq_Qq }, // SSE3E
|
||||
/* 66 */ { 0, &Ia_pabsb_Vdq_Wdq },
|
||||
@ -259,6 +287,237 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f381e[4] = {
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3820[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmovsxbw_Vdq_Wq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3821[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmovsxbd_Vdq_Wd }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3822[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmovsxbq_Vdq_Ww }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3823[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmovsxwd_Vdq_Wq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3824[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmovsxwq_Vdq_Wd }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3825[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmovsxdq_Vdq_Wq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3828[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmuldq_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3829[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pcmpeqq_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f382a[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_movntdqa_Vdq_Mdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f382b[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_packusdw_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3830[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmovzxbw_Vdq_Wq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3831[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmovzxbd_Vdq_Wd }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3832[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmovzxbq_Vdq_Ww }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3833[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmovzxwd_Vdq_Wq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3834[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmovzxwq_Vdq_Wd }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3835[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmovzxdq_Vdq_Wq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3838[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pminsb_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3839[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pminsd_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f383a[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pminuw_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f383b[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pminud_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f383c[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmaxsb_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f383d[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmaxsd_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f383e[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmaxuw_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f383f[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmaxud_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3840[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_pmulld_Vdq_Wdq }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3841[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_phminposuw_Vdq_Wdq },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a08[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_roundps_Vps_Wps_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a09[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_roundpd_Vpd_Wpd_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a0a[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_roundss_Vss_Wss_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a0b[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_roundsd_Vsd_Wsd_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a0c[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_blendps_Vps_Wps_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a0d[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_blendpd_Vpd_Wpd_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a0e[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_pblendw_Vdq_Wdq_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a0f[4] = {
|
||||
/* -- */ { 0, &Ia_palignr_Pq_Qq_Ib }, // SSE3E
|
||||
/* 66 */ { 0, &Ia_palignr_Vdq_Wdq_Ib },
|
||||
@ -266,6 +525,86 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a0f[4] = {
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a14[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_pextrb_Hbd_Udq_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a15[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_pextrw_Hwd_Udq_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGrpOs64B_pextr[2] = {
|
||||
/* 32 */ { 0, &Ia_pextrd_Hd_Udq_Ib },
|
||||
/* 64 */ { 0, &Ia_pextrq_Hq_Udq_Ib },
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a16[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { GR64BIT(pextr) }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a17[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_extractps_Hd_Udq_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a20[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_pinsrb_Vdq_Ed_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a21[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_insertps_Vps_Wss_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGrpOs64B_pinsr[2] = {
|
||||
/* 32 */ { 0, &Ia_pinsrd_Vdq_Ed_Ib },
|
||||
/* 64 */ { 0, &Ia_pinsrq_Vdq_Eq_Ib },
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a22[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { GR64BIT(pinsr) }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a40[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_dpps_Vps_Wps_Ib }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a41[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_dppd_Vpd_Wpd_Ib }, // SSE4
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a42[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid }, // SSE4
|
||||
/* 66 */ { 0, &Ia_mpsadbw_Vdq_Wdq_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f50[4] = {
|
||||
/* -- */ { 0, &Ia_movmskps_Gd_Vps },
|
||||
/* 66 */ { 0, &Ia_movmskpd_Gd_Vpd },
|
||||
@ -610,8 +949,8 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0fc3Q[4] = {
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0fc4[4] = {
|
||||
/* -- */ { 0, &Ia_pinsrw_Pq_Ed_Ib },
|
||||
/* 66 */ { 0, &Ia_pinsrw_Vdq_Ed_Ib },
|
||||
/* -- */ { 0, &Ia_pinsrw_Pq_Ew_Ib },
|
||||
/* 66 */ { 0, &Ia_pinsrw_Vdq_Ew_Ib },
|
||||
/* F2 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
@ -857,7 +1196,7 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0fef[4] = {
|
||||
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0ff0[4] = {
|
||||
/* -- */ { 0, &Ia_Invalid },
|
||||
/* 66 */ { 0, &Ia_Invalid },
|
||||
/* F3 */ { 0, &Ia_lddqu_Vdq_Mdq },
|
||||
/* F2 */ { 0, &Ia_lddqu_Vdq_Mdq },
|
||||
/* F3 */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
@ -2484,14 +2823,14 @@ static BxDisasmOpcodeTable_t BxDisasm3ByteOp0f380x[16] = {
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasm3ByteOp0f381x[16] = {
|
||||
/* 00 */ { 0, &Ia_Invalid },
|
||||
/* 00 */ { GRPSSE(0f3810) },
|
||||
/* 01 */ { 0, &Ia_Invalid },
|
||||
/* 02 */ { 0, &Ia_Invalid },
|
||||
/* 03 */ { 0, &Ia_Invalid },
|
||||
/* 04 */ { 0, &Ia_Invalid },
|
||||
/* 05 */ { 0, &Ia_Invalid },
|
||||
/* 04 */ { GRPSSE(0f3814) },
|
||||
/* 05 */ { GRPSSE(0f3815) },
|
||||
/* 06 */ { 0, &Ia_Invalid },
|
||||
/* 07 */ { 0, &Ia_Invalid },
|
||||
/* 07 */ { GRPSSE(0f3817) },
|
||||
/* 08 */ { 0, &Ia_Invalid },
|
||||
/* 09 */ { 0, &Ia_Invalid },
|
||||
/* 0A */ { 0, &Ia_Invalid },
|
||||
@ -2502,9 +2841,47 @@ static BxDisasmOpcodeTable_t BxDisasm3ByteOp0f381x[16] = {
|
||||
/* 0F */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasm3ByteTableA4[16] = {
|
||||
/* 00 */ { GR3BOP(0f380x) },
|
||||
/* 01 */ { GR3BOP(0f381x) },
|
||||
static BxDisasmOpcodeTable_t BxDisasm3ByteOp0f382x[16] = {
|
||||
/* 00 */ { GRPSSE(0f3820) },
|
||||
/* 01 */ { GRPSSE(0f3821) },
|
||||
/* 02 */ { GRPSSE(0f3822) },
|
||||
/* 03 */ { GRPSSE(0f3823) },
|
||||
/* 04 */ { GRPSSE(0f3824) },
|
||||
/* 05 */ { GRPSSE(0f3825) },
|
||||
/* 06 */ { 0, &Ia_Invalid },
|
||||
/* 07 */ { 0, &Ia_Invalid },
|
||||
/* 08 */ { GRPSSE(0f3828) },
|
||||
/* 09 */ { GRPSSE(0f3829) },
|
||||
/* 0A */ { GRPSSE(0f382a) },
|
||||
/* 0B */ { GRPSSE(0f382b) },
|
||||
/* 0C */ { 0, &Ia_Invalid },
|
||||
/* 0D */ { 0, &Ia_Invalid },
|
||||
/* 0E */ { 0, &Ia_Invalid },
|
||||
/* 0F */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasm3ByteOp0f383x[16] = {
|
||||
/* 00 */ { GRPSSE(0f3830) },
|
||||
/* 01 */ { GRPSSE(0f3831) },
|
||||
/* 02 */ { GRPSSE(0f3832) },
|
||||
/* 03 */ { GRPSSE(0f3833) },
|
||||
/* 04 */ { GRPSSE(0f3834) },
|
||||
/* 05 */ { GRPSSE(0f3835) },
|
||||
/* 06 */ { 0, &Ia_Invalid },
|
||||
/* 07 */ { 0, &Ia_Invalid },
|
||||
/* 08 */ { GRPSSE(0f3838) },
|
||||
/* 09 */ { GRPSSE(0f3839) },
|
||||
/* 0A */ { GRPSSE(0f383a) },
|
||||
/* 0B */ { GRPSSE(0f383b) },
|
||||
/* 0C */ { GRPSSE(0f383c) },
|
||||
/* 0D */ { GRPSSE(0f383d) },
|
||||
/* 0E */ { GRPSSE(0f383e) },
|
||||
/* 0F */ { GRPSSE(0f383f) }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasm3ByteOp0f384x[16] = {
|
||||
/* 00 */ { GRPSSE(0f3840) },
|
||||
/* 01 */ { GRPSSE(0f3841) },
|
||||
/* 02 */ { 0, &Ia_Invalid },
|
||||
/* 03 */ { 0, &Ia_Invalid },
|
||||
/* 04 */ { 0, &Ia_Invalid },
|
||||
@ -2521,6 +2898,25 @@ static BxDisasmOpcodeTable_t BxDisasm3ByteTableA4[16] = {
|
||||
/* 0F */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasm3ByteTableA4[16] = {
|
||||
/* 00 */ { GR3BOP(0f380x) },
|
||||
/* 01 */ { GR3BOP(0f381x) },
|
||||
/* 02 */ { GR3BOP(0f382x) },
|
||||
/* 03 */ { GR3BOP(0f383x) },
|
||||
/* 04 */ { GR3BOP(0f384x) },
|
||||
/* 05 */ { 0, &Ia_Invalid },
|
||||
/* 06 */ { 0, &Ia_Invalid },
|
||||
/* 07 */ { 0, &Ia_Invalid },
|
||||
/* 08 */ { 0, &Ia_Invalid },
|
||||
/* 09 */ { 0, &Ia_Invalid },
|
||||
/* 0A */ { 0, &Ia_Invalid },
|
||||
/* 0B */ { 0, &Ia_Invalid },
|
||||
/* 0C */ { 0, &Ia_Invalid },
|
||||
/* 0D */ { 0, &Ia_Invalid },
|
||||
/* 0E */ { 0, &Ia_Invalid },
|
||||
/* 0F */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
/* ************************************************************************ */
|
||||
/* 3-byte opcode table (Table A-5, 0F 3A) */
|
||||
|
||||
@ -2533,6 +2929,25 @@ static BxDisasmOpcodeTable_t BxDisasm3ByteOp0f3a0x[16] = {
|
||||
/* 05 */ { 0, &Ia_Invalid },
|
||||
/* 06 */ { 0, &Ia_Invalid },
|
||||
/* 07 */ { 0, &Ia_Invalid },
|
||||
/* 08 */ { GRPSSE(0f3a08) },
|
||||
/* 09 */ { GRPSSE(0f3a09) },
|
||||
/* 0A */ { GRPSSE(0f3a0a) },
|
||||
/* 0B */ { GRPSSE(0f3a0b) },
|
||||
/* 0C */ { GRPSSE(0f3a0c) },
|
||||
/* 0D */ { GRPSSE(0f3a0d) },
|
||||
/* 0E */ { GRPSSE(0f3a0e) },
|
||||
/* 0F */ { GRPSSE(0f3a0f) }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasm3ByteOp0f3a1x[16] = {
|
||||
/* 00 */ { 0, &Ia_Invalid },
|
||||
/* 01 */ { 0, &Ia_Invalid },
|
||||
/* 02 */ { 0, &Ia_Invalid },
|
||||
/* 03 */ { 0, &Ia_Invalid },
|
||||
/* 04 */ { GRPSSE(0f3a14) },
|
||||
/* 05 */ { GRPSSE(0f3a15) },
|
||||
/* 06 */ { GRPSSE(0f3a16) },
|
||||
/* 07 */ { GRPSSE(0f3a17) },
|
||||
/* 08 */ { 0, &Ia_Invalid },
|
||||
/* 09 */ { 0, &Ia_Invalid },
|
||||
/* 0A */ { 0, &Ia_Invalid },
|
||||
@ -2540,15 +2955,53 @@ static BxDisasmOpcodeTable_t BxDisasm3ByteOp0f3a0x[16] = {
|
||||
/* 0C */ { 0, &Ia_Invalid },
|
||||
/* 0D */ { 0, &Ia_Invalid },
|
||||
/* 0E */ { 0, &Ia_Invalid },
|
||||
/* 0F */ { GRPSSE(0f3a0f) }
|
||||
/* 0F */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasm3ByteOp0f3a2x[16] = {
|
||||
/* 00 */ { GRPSSE(0f3a20) },
|
||||
/* 01 */ { GRPSSE(0f3a21) },
|
||||
/* 02 */ { GRPSSE(0f3a22) },
|
||||
/* 03 */ { 0, &Ia_Invalid },
|
||||
/* 04 */ { 0, &Ia_Invalid },
|
||||
/* 05 */ { 0, &Ia_Invalid },
|
||||
/* 06 */ { 0, &Ia_Invalid },
|
||||
/* 07 */ { 0, &Ia_Invalid },
|
||||
/* 08 */ { 0, &Ia_Invalid },
|
||||
/* 09 */ { 0, &Ia_Invalid },
|
||||
/* 0A */ { 0, &Ia_Invalid },
|
||||
/* 0B */ { 0, &Ia_Invalid },
|
||||
/* 0C */ { 0, &Ia_Invalid },
|
||||
/* 0D */ { 0, &Ia_Invalid },
|
||||
/* 0E */ { 0, &Ia_Invalid },
|
||||
/* 0F */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasm3ByteOp0f3a4x[16] = {
|
||||
/* 00 */ { GRPSSE(0f3a40) },
|
||||
/* 01 */ { GRPSSE(0f3a41) },
|
||||
/* 02 */ { GRPSSE(0f3a42) },
|
||||
/* 03 */ { 0, &Ia_Invalid },
|
||||
/* 04 */ { 0, &Ia_Invalid },
|
||||
/* 05 */ { 0, &Ia_Invalid },
|
||||
/* 06 */ { 0, &Ia_Invalid },
|
||||
/* 07 */ { 0, &Ia_Invalid },
|
||||
/* 08 */ { 0, &Ia_Invalid },
|
||||
/* 09 */ { 0, &Ia_Invalid },
|
||||
/* 0A */ { 0, &Ia_Invalid },
|
||||
/* 0B */ { 0, &Ia_Invalid },
|
||||
/* 0C */ { 0, &Ia_Invalid },
|
||||
/* 0D */ { 0, &Ia_Invalid },
|
||||
/* 0E */ { 0, &Ia_Invalid },
|
||||
/* 0F */ { 0, &Ia_Invalid }
|
||||
};
|
||||
|
||||
static BxDisasmOpcodeTable_t BxDisasm3ByteTableA5[16] = {
|
||||
/* 00 */ { GR3BOP(0f3a0x) },
|
||||
/* 01 */ { 0, &Ia_Invalid },
|
||||
/* 02 */ { 0, &Ia_Invalid },
|
||||
/* 01 */ { GR3BOP(0f3a1x) },
|
||||
/* 01 */ { GR3BOP(0f3a2x) },
|
||||
/* 03 */ { 0, &Ia_Invalid },
|
||||
/* 04 */ { 0, &Ia_Invalid },
|
||||
/* 04 */ { GR3BOP(0f3a4x) },
|
||||
/* 05 */ { 0, &Ia_Invalid },
|
||||
/* 06 */ { 0, &Ia_Invalid },
|
||||
/* 07 */ { 0, &Ia_Invalid },
|
||||
|
||||
@ -32,10 +32,11 @@
|
||||
#define IA_SSE3 0x00001000 /* SSE3 instruction */
|
||||
#define IA_SSE3E 0x00002000 /* SSE3E instruction */
|
||||
#define IA_SSE4 0x00004000 /* SSE4 instruction */
|
||||
#define IA_X86_64 0x00008000 /* x86-64 instruction */
|
||||
#define IA_SYSCALL_SYSRET 0x00010000 /* SYSCALL/SYSRET instruction */
|
||||
#define IA_SYSENTER_SYSEXIT 0x00020000 /* SYSENTER/SYSEXIT instruction */
|
||||
#define IA_VMX 0x00040000 /* VMX instruction */
|
||||
#define IA_SSE4E 0x00008000 /* SSE4E instruction */
|
||||
#define IA_X86_64 0x00010000 /* x86-64 instruction */
|
||||
#define IA_SYSCALL_SYSRET 0x00020000 /* SYSCALL/SYSRET instruction */
|
||||
#define IA_SYSENTER_SYSEXIT 0x00040000 /* SYSENTER/SYSEXIT instruction */
|
||||
#define IA_VMX 0x00080000 /* VMX instruction */
|
||||
|
||||
/* general purpose bit register */
|
||||
enum {
|
||||
@ -296,11 +297,14 @@ public:
|
||||
* D - The reg field of the ModR/M byte selects a debug register.
|
||||
* E - A ModR/M byte follows the opcode and specifies the operand. The
|
||||
* operand is either a general-purpose register or a memory address.
|
||||
* If it is a memory address, the address is computed from a segment
|
||||
* register and any of the following values: a base register, an
|
||||
* index register, a scaling factor, a displacement.
|
||||
* In case of the register operand, the R/M field of the ModR/M byte
|
||||
* selects a general register.
|
||||
* F - Flags Register.
|
||||
* G - The reg field of the ModR/M byte selects a general register.
|
||||
* H - A ModR/M byte follows the opcode and specifies the operand. The
|
||||
* operand is either a general-purpose register or a memory address.
|
||||
* In case of the register operand, the reg field of the ModR/M byte
|
||||
* selects a general register.
|
||||
* I - Immediate data. The operand value is encoded in subsequent bytes of
|
||||
* the instruction.
|
||||
* J - The instruction contains a relative offset to be added to the
|
||||
@ -321,8 +325,8 @@ public:
|
||||
* index register, a scaling factor, and a displacement.
|
||||
* R - The mod field of the ModR/M byte may refer only to a general register.
|
||||
* S - The reg field of the ModR/M byte selects a segment register.
|
||||
* U - The R/M field of the ModR/M byte selects a 128-bit XMM register.
|
||||
* T - The reg field of the ModR/M byte selects a test register.
|
||||
* U - The R/M field of the ModR/M byte selects a 128-bit XMM register.
|
||||
* V - The reg field of the ModR/M byte selects a 128-bit XMM register.
|
||||
* W - A ModR/M byte follows the opcode and specifies the operand. The
|
||||
* operand is either a 128-bit XMM register or a memory address. If
|
||||
@ -419,6 +423,11 @@ public:
|
||||
void Gd(const x86_insn *insn);
|
||||
void Gq(const x86_insn *insn);
|
||||
|
||||
void Hbd(const x86_insn *insn);
|
||||
void Hwd(const x86_insn *insn);
|
||||
void Hd(const x86_insn *insn);
|
||||
void Hq(const x86_insn *insn);
|
||||
|
||||
// immediate
|
||||
void I1(const x86_insn *insn);
|
||||
void Ib(const x86_insn *insn);
|
||||
@ -462,7 +471,10 @@ public:
|
||||
void Vpd(const x86_insn *insn);
|
||||
|
||||
// xmm register or memory operand
|
||||
void Ww(const x86_insn *insn);
|
||||
void Wd(const x86_insn *insn);
|
||||
void Wq(const x86_insn *insn);
|
||||
|
||||
void Wdq(const x86_insn *insn);
|
||||
void Wss(const x86_insn *insn);
|
||||
void Wsd(const x86_insn *insn);
|
||||
|
||||
@ -70,6 +70,10 @@ Ia_andw_Ew_Iw = { "and", "andw", Ew, Iw, XX, 0 },
|
||||
Ia_andw_Ew_sIb = { "and", "andw", Ew, sIbw, XX, 0 },
|
||||
Ia_andw_Gw_Ew = { "and", "andw", Gw, Ew, XX, 0 },
|
||||
Ia_arpl_Ew_Rw = { "arpl", "arpl", Ew, Rw, XX, 0 },
|
||||
Ia_blendpd_Vpd_Wpd_Ib = { "blendpd", "blendpd", Vpd, Wpd, Ib, IA_SSE4 },
|
||||
Ia_blendps_Vps_Wps_Ib = { "blendps", "blendps", Vps, Wps, Ib, IA_SSE4 },
|
||||
Ia_blendvpd_Vpd_Wpd = { "blendvpd", "blendvpd", Vpd, Wpd, XX, IA_SSE4 },
|
||||
Ia_blendvps_Vps_Wps = { "blendvps", "blendvps", Vps, Wps, XX, IA_SSE4 },
|
||||
Ia_boundl_Gd_Ma = { "bound", "boundl", Gd, Ma, XX, 0 },
|
||||
Ia_boundw_Gw_Ma = { "bound", "boundw", Gw, Ma, XX, 0 },
|
||||
Ia_bsfl_Gd_Ed = { "bsf", "bsfl", Gd, Ed, XX, 0 },
|
||||
@ -249,9 +253,12 @@ Ia_divq_RAX_Eq = { "div", "divq", RAX, Eq, XX, IA_X86_64 },
|
||||
Ia_divsd_Vsd_Wsd = { "divsd", "divsd", Vsd, Wsd, XX, IA_SSE2 },
|
||||
Ia_divss_Vss_Wss = { "divss", "divss", Vss, Wss, XX, IA_SSE },
|
||||
Ia_divw_AX_Ew = { "div", "divw", AX, Ew, XX, 0 },
|
||||
Ia_dppd_Vpd_Wpd_Ib = { "dppd", "dppd", Vpd, Wpd, Ib, IA_SSE4 },
|
||||
Ia_dpps_Vps_Wps_Ib = { "dpps", "dpps", Vps, Wps, Ib, IA_SSE4 },
|
||||
Ia_emms = { "emms", "emms", XX, XX, XX, IA_MMX },
|
||||
Ia_enter = { "enter", "enter", IwIb, XX, XX, 0 },
|
||||
Ia_error = { "(error)", "(error)", XX, XX, XX, 0 },
|
||||
Ia_extractps_Hd_Udq_Ib = { "extractps", "extractps", Hd, Udq, Ib, IA_SSE4 },
|
||||
Ia_f2xm1 = { "f2xm1", "f2xm1", XX, XX, XX, IA_X87 },
|
||||
Ia_fabs = { "fabs", "fabs", XX, XX, XX, IA_X87 },
|
||||
Ia_fadd_ST0_STi = { "fadd", "fadd", ST0, STi, XX, IA_X87 },
|
||||
@ -425,6 +432,7 @@ Ia_incw_RX = { "inc", "incw", RX, XX, XX, 0 },
|
||||
Ia_inl_EAX_DX = { "in", "inl", EAX, DX, XX, 0 },
|
||||
Ia_inl_EAX_Ib = { "in", "inl", EAX, Ib, XX, 0 },
|
||||
Ia_insb_Yb_DX = { "insb", "insb", Yb, DX, XX, 0 },
|
||||
Ia_insertps_Vps_Wss_Ib = { "insertps", "insertps", Vps, Wss, Ib, IA_SSE4 },
|
||||
Ia_insl_Yd_DX = { "insd", "insl", Yd, DX, XX, 0 },
|
||||
Ia_insw_Yw_DX = { "insw", "insw", Yw, DX, XX, 0 },
|
||||
Ia_int_Ib = { "int", "int", Ib, XX, XX, 0 },
|
||||
@ -602,6 +610,7 @@ Ia_movlps_Vps_Mq = { "movlps", "movlps", Vps, Mq, XX, IA_SSE },
|
||||
Ia_movmskpd_Gd_Vpd = { "movmskpd", "movmskpd", Gd, Vpd, XX, IA_SSE2 },
|
||||
Ia_movmskps_Gd_Vps = { "movmskps", "movmskps", Gd, Vps, XX, IA_SSE },
|
||||
Ia_movntdq_Mdq_Vdq = { "movntdq", "movntdq", Mdq, Vdq, XX, IA_SSE2 },
|
||||
Ia_movntdqa_Vdq_Mdq = { "movntdqa", "movntdqa", Vdq, Mdq, XX, IA_SSE4 },
|
||||
Ia_movnti_Md_Gd = { "movnti", "movnti", Md, Gd, XX, IA_SSE2 },
|
||||
Ia_movntiq_Mq_Gq = { "movntiq", "movntiq", Mq, Gq, XX, IA_X86_64 },
|
||||
Ia_movntpd_Mpd_Vpd = { "movntpd", "movntpd", Mpd, Vpd, XX, IA_SSE2 },
|
||||
@ -659,6 +668,7 @@ Ia_movzbq_Gq_Eb = { "movzx", "movzbq", Gq, Eb, XX, IA_X86_64 },
|
||||
Ia_movzbw_Gw_Eb = { "movzx", "movzbw", Gw, Eb, XX, 0 },
|
||||
Ia_movzwl_Gd_Ew = { "movzx", "movzwl", Gd, Ew, XX, 0 },
|
||||
Ia_movzwq_Gq_Ew = { "movzx", "movzwq", Gq, Ew, XX, IA_X86_64 },
|
||||
Ia_mpsadbw_Vdq_Wdq_Ib = { "mpsadbw", "mpsadbw", Vdq, Wdq, Ib, IA_SSE4 },
|
||||
Ia_mulb_AL_Eb = { "mul", "mulb", AL, Eb, XX, 0 },
|
||||
Ia_mull_EAX_Ed = { "mul", "mull", EAX, Ed, XX, 0 },
|
||||
Ia_mulpd_Vpd_Wpd = { "mulpd", "mulpd", Vpd, Wpd, XX, IA_SSE2 },
|
||||
@ -718,6 +728,7 @@ Ia_packssdw_Pq_Qq = { "packssdw", "packssdw", Pq, Qq, XX, IA_MMX },
|
||||
Ia_packssdw_Vdq_Wdq = { "packssdw", "packssdw", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_packsswb_Pq_Qq = { "packsswb", "packsswb", Pq, Qq, XX, IA_MMX },
|
||||
Ia_packsswb_Vdq_Wq = { "packsswb", "packsswb", Vdq, Wq, XX, IA_SSE2 },
|
||||
Ia_packusdw_Vdq_Wdq = { "packusdw", "packusdw", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_packuswb_Pq_Qq = { "packuswb", "packuswb", Pq, Qq, XX, IA_MMX },
|
||||
Ia_packuswb_Vdq_Wdq = { "packuswb", "packuswb", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_paddb_Pq_Qq = { "paddb", "paddb", Pq, Qq, XX, IA_MMX },
|
||||
@ -747,10 +758,13 @@ Ia_pavgb_Pq_Qq = { "pavgb", "pavgb", Pq, Qq, XX, IA_MMX },
|
||||
Ia_pavgb_Vdq_Wdq = { "pavgb", "pavgb", Vdq, Wdq, XX, IA_SSE },
|
||||
Ia_pavgw_Pq_Qq = { "pavgw", "pavgw", Pq, Qq, XX, IA_MMX },
|
||||
Ia_pavgw_Vdq_Wdq = { "pavgw", "pavgw", Vdq, Wdq, XX, IA_SSE },
|
||||
Ia_pblendvb_Vdq_Wdq = { "pblendvb", "pblendvb", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_pblendw_Vdq_Wdq_Ib = { "pblendw", "pblendw", Vdq, Wdq, Ib, IA_SSE4 },
|
||||
Ia_pcmpeqb_Pq_Qq = { "pcmpeqb", "pcmpeqb", Pq, Qq, XX, IA_MMX },
|
||||
Ia_pcmpeqb_Vdq_Wdq = { "pcmpeqb", "pcmpeqb", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_pcmpeqd_Pq_Qq = { "pcmpeqd", "pcmpeqd", Pq, Qq, XX, IA_MMX },
|
||||
Ia_pcmpeqd_Vdq_Wdq = { "pcmpeqd", "pcmpeqd", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_pcmpeqq_Vdq_Wdq = { "pcmpeqq", "pcmpeqq", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_pcmpeqw_Pq_Qq = { "pcmpeqw", "pcmpeqw", Pq, Qq, XX, IA_MMX },
|
||||
Ia_pcmpeqw_Vdq_Wdq = { "pcmpeqw", "pcmpeqw", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_pcmpgtb_Pq_Qq = { "pcmpgtb", "pcmpgtb", Pq, Qq, XX, IA_MMX },
|
||||
@ -759,8 +773,12 @@ Ia_pcmpgtd_Pq_Qq = { "pcmpgtd", "pcmpgtd", Pq, Qq, XX, IA_MMX },
|
||||
Ia_pcmpgtd_Vdq_Wdq = { "pcmpgtd", "pcmpgtd", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_pcmpgtw_Pq_Qq = { "pcmpgtw", "pcmpgtw", Pq, Qq, XX, IA_MMX },
|
||||
Ia_pcmpgtw_Vdq_Wq = { "pcmpgtw", "pcmpgtw", Vdq, Wq, XX, IA_SSE2 },
|
||||
Ia_pextrb_Hbd_Udq_Ib = { "pextrb", "pextrb", Hbd, Udq, Ib, IA_SSE4 },
|
||||
Ia_pextrd_Hd_Udq_Ib = { "pextrd", "pextrd", Hd, Udq, Ib, IA_SSE4 },
|
||||
Ia_pextrq_Hq_Udq_Ib = { "pextrq", "pextrq", Hq, Udq, Ib, IA_SSE4 },
|
||||
Ia_pextrw_Gd_Nq_Ib = { "pextrw", "pextrw", Gd, Nq, Ib, IA_3DNOW | IA_SSE },
|
||||
Ia_pextrw_Gd_Udq_Ib = { "pextrw", "pextrw", Gd, Udq, Ib, IA_SSE2 },
|
||||
Ia_pextrw_Hwd_Udq_Ib = { "pextrw", "pextrw", Hwd, Udq, Ib, IA_SSE4 },
|
||||
Ia_pf2id_Pq_Qq = { "pf2id", "pf2id", Pq, Qq, XX, IA_3DNOW },
|
||||
Ia_pf2iw_Pq_Qq = { "pf2iw", "pf2iw", Pq, Qq, XX, IA_3DNOW },
|
||||
Ia_pfacc_Pq_Qq = { "pfacc", "pfacc", Pq, Qq, XX, IA_3DNOW },
|
||||
@ -786,6 +804,7 @@ Ia_phaddsw_Pq_Qq = { "phaddsw", "phaddsw", Pq, Qq, XX, IA_SSE3E },
|
||||
Ia_phaddsw_Vdq_Wdq = { "phaddsw", "phaddsw", Vdq, Wdq, XX, IA_SSE3E },
|
||||
Ia_phaddw_Pq_Qq = { "phaddw", "phaddw", Pq, Qq, XX, IA_SSE3E },
|
||||
Ia_phaddw_Vdq_Wdq = { "phaddw", "phaddw", Vdq, Wdq, XX, IA_SSE3E },
|
||||
Ia_phminposuw_Vdq_Wdq = { "phminposuw", "phminposuw", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_phsubd_Pq_Qq = { "phsubd", "phsubd", Pq, Qq, XX, IA_SSE3E },
|
||||
Ia_phsubd_Vdq_Wdq = { "phsubd", "phsubd", Vdq, Wdq, XX, IA_SSE3E },
|
||||
Ia_phsubsw_Pq_Qq = { "phsubsw", "phsubsw", Pq, Qq, XX, IA_SSE3E },
|
||||
@ -794,22 +813,46 @@ Ia_phsubw_Pq_Qq = { "phsubw", "phsubw", Pq, Qq, XX, IA_SSE3E },
|
||||
Ia_phsubw_Vdq_Wdq = { "phsubw", "phsubw", Vdq, Wdq, XX, IA_SSE3E },
|
||||
Ia_pi2fd_Pq_Qq = { "pi2fd", "pi2fd", Pq, Qq, XX, IA_3DNOW },
|
||||
Ia_pi2fw_Pq_Qq = { "pi2fw", "pi2fw", Pq, Qq, XX, IA_3DNOW },
|
||||
Ia_pinsrw_Pq_Ed_Ib = { "pinsrw", "pinsrw", Pq, Ed, Ib, IA_3DNOW | IA_SSE },
|
||||
Ia_pinsrw_Vdq_Ed_Ib = { "pinsrw", "pinsrw", Vdq, Ed, Ib, IA_SSE2 },
|
||||
Ia_pinsrb_Vdq_Ed_Ib = { "pinsrb", "pinsrb", Vdq, Ed, Ib, IA_SSE4 },
|
||||
Ia_pinsrd_Vdq_Ed_Ib = { "pinsrd", "pinsrd", Vdq, Ed, Ib, IA_SSE4 },
|
||||
Ia_pinsrq_Vdq_Eq_Ib = { "pinsrq", "pinsrq", Vdq, Eq, Ib, IA_SSE4 },
|
||||
Ia_pinsrw_Pq_Ew_Ib = { "pinsrw", "pinsrw", Pq, Ew, Ib, IA_3DNOW | IA_SSE },
|
||||
Ia_pinsrw_Vdq_Ew_Ib = { "pinsrw", "pinsrw", Vdq, Ew, Ib, IA_SSE2 },
|
||||
Ia_pmaddubsw_Pq_Qq = { "pmaddubsw", "pmaddubsw", Pq, Qq, XX, IA_SSE3E },
|
||||
Ia_pmaddubsw_Vdq_Wdq = { "pmaddubsw", "pmaddubsw", Vdq, Wdq, XX, IA_SSE3E },
|
||||
Ia_pmaddwd_Pq_Qq = { "pmaddwd", "pmaddwd", Pq, Qq, XX, IA_MMX },
|
||||
Ia_pmaddwd_Vdq_Wdq = { "pmaddwd", "pmaddwd", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_pmaxsb_Vdq_Wdq = { "pmaxsb", "pmaxsb", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_pmaxsd_Vdq_Wdq = { "pmaxsd", "pmaxsd", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_pmaxsw_Pq_Qq = { "pmaxsw", "pmaxsw", Pq, Qq, XX, 0 },
|
||||
Ia_pmaxsw_Vdq_Wdq = { "pmaxsw", "pmaxsw", Vdq, Wdq, XX, 0 },
|
||||
Ia_pmaxub_Pq_Qq = { "pmaxub", "pmaxub", Pq, Qq, XX, IA_3DNOW | IA_SSE },
|
||||
Ia_pmaxub_Vdq_Wdq = { "pmaxub", "pmaxub", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_pmaxud_Vdq_Wdq = { "pmaxud", "pmaxud", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_pmaxuw_Vdq_Wdq = { "pmaxuw", "pmaxuw", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_pminsb_Vdq_Wdq = { "pminsb", "pminsb", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_pminsd_Vdq_Wdq = { "pminsd", "pminsd", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_pminsw_Pq_Qq = { "pminsw", "pminsw", Pq, Qq, XX, IA_3DNOW | IA_SSE },
|
||||
Ia_pminsw_Vdq_Wdq = { "pminsw", "pminsw", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_pminub_Pq_Qq = { "pminub", "pminub", Pq, Qq, XX, IA_3DNOW | IA_SSE },
|
||||
Ia_pminub_Vdq_Wdq = { "pminub", "pminub", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_pminud_Vdq_Wdq = { "pminud", "pminud", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_pminuw_Vdq_Wdq = { "pminuw", "pminuw", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_pmovmskb_Gd_Nq = { "pmovmskb", "pmovmskb", Gd, Nq, XX, IA_3DNOW | IA_SSE },
|
||||
Ia_pmovmskb_Gd_Udq = { "pmovmskb", "pmovmskb", Gd, Udq, XX, IA_SSE2 },
|
||||
Ia_pmovsxbd_Vdq_Wd = { "pmovsxbd", "pmovsxbd", Vdq, Wd, XX, IA_SSE4 },
|
||||
Ia_pmovsxbq_Vdq_Ww = { "pmovsxbq", "pmovsxbq", Vdq, Ww, XX, IA_SSE4 },
|
||||
Ia_pmovsxbw_Vdq_Wq = { "pmovsxbw", "pmovsxbw", Vdq, Wq, XX, IA_SSE4 },
|
||||
Ia_pmovsxdq_Vdq_Wq = { "pmovsxdq", "pmovsxdq", Vdq, Wq, XX, IA_SSE4 },
|
||||
Ia_pmovsxwd_Vdq_Wq = { "pmovsxwd", "pmovsxwd", Vdq, Wq, XX, IA_SSE4 },
|
||||
Ia_pmovsxwq_Vdq_Wd = { "pmovsxwq", "pmovsxwq", Vdq, Wd, XX, IA_SSE4 },
|
||||
Ia_pmovzxbd_Vdq_Wd = { "pmovzxbd", "pmovzxbd", Vdq, Wd, XX, IA_SSE4 },
|
||||
Ia_pmovzxbq_Vdq_Ww = { "pmovzxbq", "pmovzxbq", Vdq, Ww, XX, IA_SSE4 },
|
||||
Ia_pmovzxbw_Vdq_Wq = { "pmovzxbw", "pmovzxbw", Vdq, Wq, XX, IA_SSE4 },
|
||||
Ia_pmovzxdq_Vdq_Wq = { "pmovzxdq", "pmovzxdq", Vdq, Wq, XX, IA_SSE4 },
|
||||
Ia_pmovzxwd_Vdq_Wq = { "pmovzxwd", "pmovzxwd", Vdq, Wq, XX, IA_SSE4 },
|
||||
Ia_pmovzxwq_Vdq_Wd = { "pmovzxwq", "pmovzxwq", Vdq, Wd, XX, IA_SSE4 },
|
||||
Ia_pmuldq_Vdq_Wdq = { "pmuldq", "pmuldq", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_pmulhrsw_Pq_Qq = { "pmulhrsw", "pmulhrsw", Pq, Qq, XX, IA_SSE3E },
|
||||
Ia_pmulhrsw_Vdq_Wdq = { "pmulhrsw", "pmulhrsw", Vdq, Wdq, XX, IA_SSE3E },
|
||||
Ia_pmulhrw_Pq_Qq = { "pmulhrw", "pmulhrw", Pq, Qq, XX, IA_3DNOW },
|
||||
@ -817,6 +860,7 @@ Ia_pmulhuw_Pq_Qq = { "pmulhuw", "pmulhuw", Pq, Qq, XX, IA_3DNOW | IA_MMX },
|
||||
Ia_pmulhuw_Vdq_Wdq = { "pmulhuw", "pmulhuw", Vdq, Wdq, XX, IA_SSE },
|
||||
Ia_pmulhw_Pq_Qq = { "pmulhw", "pmulhw", Pq, Qq, XX, IA_MMX },
|
||||
Ia_pmulhw_Vdq_Wdq = { "pmulhw", "pmulhw", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_pmulld_Vdq_Wdq = { "pmulld", "pmulld", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_pmullw_Pq_Qq = { "pmullw", "pmullw", Pq, Qq, XX, IA_MMX },
|
||||
Ia_pmullw_Vdq_Wdq = { "pmullw", "pmullw", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_pmuludq_Pq_Qq = { "pmuludq", "pmuludq", Pq, Qq, XX, IA_SSE2 },
|
||||
@ -928,6 +972,7 @@ Ia_psubusw_Vdq_Wdq = { "psubusw", "psubusw", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_psubw_Pq_Qq = { "psubw", "psubw", Pq, Qq, XX, IA_MMX },
|
||||
Ia_psubw_Vdq_Wdq = { "psubw", "psubw", Vdq, Wdq, XX, IA_SSE2 },
|
||||
Ia_pswapd_Pq_Qq = { "pswapd", "pswapd", Pq, Qq, XX, IA_3DNOW },
|
||||
Ia_ptest_Vdq_Wdq = { "ptest", "ptest", Vdq, Wdq, XX, IA_SSE4 },
|
||||
Ia_punpckhbw_Pq_Qq = { "punpckhbw", "punpckhbw", Pq, Qq, XX, IA_MMX },
|
||||
Ia_punpckhbw_Vdq_Wq = { "punpckhbw", "punpckhbw", Vdq, Wq, XX, IA_SSE2 },
|
||||
Ia_punpckhdq_Pq_Qq = { "punpckhdq", "punpckhdq", Pq, Qq, XX, IA_MMX },
|
||||
@ -1031,6 +1076,10 @@ Ia_rorq_Eq_Ib = { "ror", "rorq", Eq, Ib, XX, IA_X86_64 },
|
||||
Ia_rorw_Ew_CL = { "ror", "rorw", Ew, CL, XX, 0 },
|
||||
Ia_rorw_Ew_I1 = { "ror", "rorw", Ew, I1, XX, 0 },
|
||||
Ia_rorw_Ew_Ib = { "ror", "rorw", Ew, Ib, XX, 0 },
|
||||
Ia_roundpd_Vpd_Wpd_Ib = { "roundpd", "roundpd", Vpd, Wpd, Ib, IA_SSE4 },
|
||||
Ia_roundps_Vps_Wps_Ib = { "roundps", "roundps", Vps, Wps, Ib, IA_SSE4 },
|
||||
Ia_roundsd_Vsd_Wsd_Ib = { "roundsd", "roundsd", Vsd, Wsd, Ib, IA_SSE4 },
|
||||
Ia_roundss_Vss_Wss_Ib = { "roundss", "roundss", Vss, Wss, Ib, IA_SSE4 },
|
||||
Ia_rsm = { "rsm", "rsm", XX, XX, XX, 0 },
|
||||
Ia_rsqrtps_Vps_Wps = { "rsqrtps", "rsqrtps", Vps, Wps, XX, IA_SSE },
|
||||
Ia_rsqrtss_Vss_Wss = { "rsqrtss", "rsqrtss", Vss, Wss, XX, IA_SSE },
|
||||
|
||||
@ -42,8 +42,8 @@ these four paragraphs for those parts of this code that are retained.
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE floating-point types.
|
||||
*----------------------------------------------------------------------------*/
|
||||
typedef Bit32u float32, Float32;
|
||||
typedef Bit64u float64, Float64;
|
||||
typedef Bit32u float32;
|
||||
typedef Bit64u float64;
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE floating-point class.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user