Split SHRD/SHLD instructions
This commit is contained in:
Stanislav Shwartsman
parent
16bf4402b0
commit
1bdddc1f78
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.446 2008-04-05 17:51:54 sshwarts Exp $
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// $Id: cpu.h,v 1.447 2008-04-05 19:08:01 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1339,10 +1339,14 @@ public: // for now...
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BX_SMF void CPUID(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHRD_EwGw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHRD_EdGd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHLD_EdGd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHLD_EwGw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHRD_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHRD_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHLD_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHLD_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHRD_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHRD_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHLD_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHLD_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSF_GwEw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void BSF_GdEd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -2544,8 +2548,11 @@ public: // for now...
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BX_SMF void MOV_RqCq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOV_RqDq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHLD_EqGq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHRD_EqGq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHLD_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHLD_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHRD_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SHRD_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void IMUL_GqEq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void IMUL_GqEqId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.179 2008-04-05 17:51:54 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.180 2008-04-05 19:08:01 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -654,16 +654,16 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* 0F A1 /wr */ { 0, BX_IA_POP16_FS },
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/* 0F A2 /wr */ { 0, BX_IA_CPUID },
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/* 0F A3 /wr */ { 0, BX_IA_BT_EwGwR },
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/* 0F A4 /wr */ { BxImmediate_Ib, BX_IA_SHLD_EwGw },
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/* 0F A5 /wr */ { 0, BX_IA_SHLD_EwGw },
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/* 0F A4 /wr */ { BxImmediate_Ib, BX_IA_SHLD_EwGwR },
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/* 0F A5 /wr */ { 0, BX_IA_SHLD_EwGwR },
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/* 0F A6 /wr */ { BxTraceEnd, BX_IA_CMPXCHG_XBTS }, // not implemented
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/* 0F A7 /wr */ { BxTraceEnd, BX_IA_CMPXCHG_IBTS }, // not implemented
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/* 0F A8 /wr */ { 0, BX_IA_PUSH16_GS },
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/* 0F A9 /wr */ { 0, BX_IA_POP16_GS },
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/* 0F AA /wr */ { BxTraceEnd, BX_IA_RSM },
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/* 0F AB /wr */ { 0, BX_IA_BTS_EwGwR },
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/* 0F AC /wr */ { BxImmediate_Ib, BX_IA_SHRD_EwGw },
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/* 0F AD /wr */ { 0, BX_IA_SHRD_EwGw },
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/* 0F AC /wr */ { BxImmediate_Ib, BX_IA_SHRD_EwGwR },
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/* 0F AD /wr */ { 0, BX_IA_SHRD_EwGwR },
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/* 0F AE /wr */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15R },
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/* 0F AF /wr */ { 0, BX_IA_IMUL_GwEw },
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/* 0F B0 /wr */ { 0, BX_IA_CMPXCHG_EbGbR },
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@ -1216,16 +1216,16 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* 0F A1 /dr */ { 0, BX_IA_POP32_FS },
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/* 0F A2 /dr */ { 0, BX_IA_CPUID },
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/* 0F A3 /dr */ { 0, BX_IA_BT_EdGdR },
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/* 0F A4 /dr */ { BxImmediate_Ib, BX_IA_SHLD_EdGd },
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/* 0F A5 /dr */ { 0, BX_IA_SHLD_EdGd },
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/* 0F A4 /dr */ { BxImmediate_Ib, BX_IA_SHLD_EdGdR },
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/* 0F A5 /dr */ { 0, BX_IA_SHLD_EdGdR },
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/* 0F A6 /dr */ { BxTraceEnd, BX_IA_CMPXCHG_XBTS }, // not implemented
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/* 0F A7 /dr */ { BxTraceEnd, BX_IA_CMPXCHG_IBTS }, // not implemented
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/* 0F A8 /dr */ { 0, BX_IA_PUSH32_GS },
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/* 0F A9 /dr */ { 0, BX_IA_POP32_GS },
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/* 0F AA /dr */ { BxTraceEnd, BX_IA_RSM },
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/* 0F AB /dr */ { 0, BX_IA_BTS_EdGdR },
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/* 0F AC /dr */ { BxImmediate_Ib, BX_IA_SHRD_EdGd },
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/* 0F AD /dr */ { 0, BX_IA_SHRD_EdGd },
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/* 0F AC /dr */ { BxImmediate_Ib, BX_IA_SHRD_EdGdR },
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/* 0F AD /dr */ { 0, BX_IA_SHRD_EdGdR },
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/* 0F AE /dr */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15R },
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/* 0F AF /dr */ { 0, BX_IA_IMUL_GdEd },
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/* 0F B0 /dr */ { 0, BX_IA_CMPXCHG_EbGbR },
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@ -1785,16 +1785,16 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* 0F A1 /wm */ { 0, BX_IA_POP16_FS },
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/* 0F A2 /wm */ { 0, BX_IA_CPUID },
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/* 0F A3 /wm */ { 0, BX_IA_BT_EwGwM },
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/* 0F A4 /wm */ { BxImmediate_Ib, BX_IA_SHLD_EwGw },
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/* 0F A5 /wm */ { 0, BX_IA_SHLD_EwGw },
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/* 0F A4 /wm */ { BxImmediate_Ib, BX_IA_SHLD_EwGwM },
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/* 0F A5 /wm */ { 0, BX_IA_SHLD_EwGwM },
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/* 0F A6 /wm */ { BxTraceEnd, BX_IA_CMPXCHG_XBTS }, // not implemented
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/* 0F A7 /wm */ { BxTraceEnd, BX_IA_CMPXCHG_IBTS }, // not implemented
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/* 0F A8 /wm */ { 0, BX_IA_PUSH16_GS },
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/* 0F A9 /wm */ { 0, BX_IA_POP16_GS },
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/* 0F AA /wm */ { BxTraceEnd, BX_IA_RSM },
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/* 0F AB /wm */ { BxLockable, BX_IA_BTS_EwGwM },
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/* 0F AC /wm */ { BxImmediate_Ib, BX_IA_SHRD_EwGw },
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/* 0F AD /wm */ { 0, BX_IA_SHRD_EwGw },
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/* 0F AC /wm */ { BxImmediate_Ib, BX_IA_SHRD_EwGwM },
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/* 0F AD /wm */ { 0, BX_IA_SHRD_EwGwM },
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/* 0F AE /wm */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15M },
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/* 0F AF /wm */ { 0, BX_IA_IMUL_GwEw },
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/* 0F B0 /wm */ { BxLockable, BX_IA_CMPXCHG_EbGbM },
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@ -2347,16 +2347,16 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* 0F A1 /dm */ { 0, BX_IA_POP32_FS },
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/* 0F A2 /dm */ { 0, BX_IA_CPUID },
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/* 0F A3 /dm */ { 0, BX_IA_BT_EdGdM },
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/* 0F A4 /dm */ { BxImmediate_Ib, BX_IA_SHLD_EdGd },
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/* 0F A5 /dm */ { 0, BX_IA_SHLD_EdGd },
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/* 0F A4 /dm */ { BxImmediate_Ib, BX_IA_SHLD_EdGdM },
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/* 0F A5 /dm */ { 0, BX_IA_SHLD_EdGdM },
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/* 0F A6 /dm */ { BxTraceEnd, BX_IA_CMPXCHG_XBTS }, // not implemented
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/* 0F A7 /dm */ { BxTraceEnd, BX_IA_CMPXCHG_IBTS }, // not implemented
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/* 0F A8 /dm */ { 0, BX_IA_PUSH32_GS },
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/* 0F A9 /dm */ { 0, BX_IA_POP32_GS },
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/* 0F AA /dm */ { BxTraceEnd, BX_IA_RSM },
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/* 0F AB /dm */ { BxLockable, BX_IA_BTS_EdGdM },
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/* 0F AC /dm */ { BxImmediate_Ib, BX_IA_SHRD_EdGd },
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/* 0F AD /dm */ { 0, BX_IA_SHRD_EdGd },
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/* 0F AC /dm */ { BxImmediate_Ib, BX_IA_SHRD_EdGdM },
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/* 0F AD /dm */ { 0, BX_IA_SHRD_EdGdM },
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/* 0F AE /dm */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15M },
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/* 0F AF /dm */ { 0, BX_IA_IMUL_GdEd },
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/* 0F B0 /dm */ { BxLockable, BX_IA_CMPXCHG_EbGbM },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode64.cc,v 1.186 2008-04-05 17:51:55 sshwarts Exp $
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// $Id: fetchdecode64.cc,v 1.187 2008-04-05 19:08:01 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -614,16 +614,16 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
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/* 0F A1 /wr */ { 0, BX_IA_POP16_FS },
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/* 0F A2 /wr */ { 0, BX_IA_CPUID },
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/* 0F A3 /wr */ { 0, BX_IA_BT_EwGwR },
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/* 0F A4 /wr */ { BxImmediate_Ib, BX_IA_SHLD_EwGw },
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/* 0F A5 /wr */ { 0, BX_IA_SHLD_EwGw },
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/* 0F A4 /wr */ { BxImmediate_Ib, BX_IA_SHLD_EwGwR },
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/* 0F A5 /wr */ { 0, BX_IA_SHLD_EwGwR },
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/* 0F A6 /wr */ { 0, BX_IA_ERROR },
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/* 0F A7 /wr */ { 0, BX_IA_ERROR },
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/* 0F A8 /wr */ { 0, BX_IA_PUSH16_GS },
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/* 0F A9 /wr */ { 0, BX_IA_POP16_GS },
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/* 0F AA /wr */ { BxTraceEnd, BX_IA_RSM },
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/* 0F AB /wr */ { 0, BX_IA_BTS_EwGwR },
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/* 0F AC /wr */ { BxImmediate_Ib, BX_IA_SHRD_EwGw },
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/* 0F AD /wr */ { 0, BX_IA_SHRD_EwGw },
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/* 0F AC /wr */ { BxImmediate_Ib, BX_IA_SHRD_EwGwR },
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/* 0F AD /wr */ { 0, BX_IA_SHRD_EwGwR },
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/* 0F AE /wr */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15R },
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/* 0F AF /wr */ { 0, BX_IA_IMUL_GwEw },
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/* 0F B0 /wr */ { 0, BX_IA_CMPXCHG_EbGbR },
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@ -1141,16 +1141,16 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
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/* 0F A1 /dr */ { 0, BX_IA_POP64_FS },
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/* 0F A2 /dr */ { 0, BX_IA_CPUID },
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/* 0F A3 /dr */ { 0, BX_IA_BT_EdGdR },
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/* 0F A4 /dr */ { BxImmediate_Ib, BX_IA_SHLD_EdGd },
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/* 0F A5 /dr */ { 0, BX_IA_SHLD_EdGd },
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/* 0F A4 /dr */ { BxImmediate_Ib, BX_IA_SHLD_EdGdR },
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/* 0F A5 /dr */ { 0, BX_IA_SHLD_EdGdR },
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/* 0F A6 /dr */ { 0, BX_IA_ERROR },
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/* 0F A7 /dr */ { 0, BX_IA_ERROR },
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/* 0F A8 /dr */ { 0, BX_IA_PUSH64_GS },
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/* 0F A9 /dr */ { 0, BX_IA_POP64_GS },
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/* 0F AA /dr */ { BxTraceEnd, BX_IA_RSM },
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/* 0F AB /dr */ { 0, BX_IA_BTS_EdGdR },
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/* 0F AC /dr */ { BxImmediate_Ib, BX_IA_SHRD_EdGd },
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/* 0F AD /dr */ { 0, BX_IA_SHRD_EdGd },
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/* 0F AC /dr */ { BxImmediate_Ib, BX_IA_SHRD_EdGdR },
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/* 0F AD /dr */ { 0, BX_IA_SHRD_EdGdR },
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/* 0F AE /dr */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15R },
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/* 0F AF /dr */ { 0, BX_IA_IMUL_GdEd },
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/* 0F B0 /dr */ { 0, BX_IA_CMPXCHG_EbGbR },
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@ -1668,16 +1668,16 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
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/* 0F A1 /qr */ { 0, BX_IA_POP64_FS },
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/* 0F A2 /qr */ { 0, BX_IA_CPUID },
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/* 0F A3 /qr */ { 0, BX_IA_BT_EqGqR },
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/* 0F A4 /qr */ { BxImmediate_Ib, BX_IA_SHLD_EqGq },
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/* 0F A5 /qr */ { 0, BX_IA_SHLD_EqGq },
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/* 0F A4 /qr */ { BxImmediate_Ib, BX_IA_SHLD_EqGqR },
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/* 0F A5 /qr */ { 0, BX_IA_SHLD_EqGqR },
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/* 0F A6 /qr */ { 0, BX_IA_ERROR },
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/* 0F A7 /qr */ { 0, BX_IA_ERROR },
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/* 0F A8 /qr */ { 0, BX_IA_PUSH64_GS },
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/* 0F A9 /qr */ { 0, BX_IA_POP64_GS },
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/* 0F AA /qr */ { BxTraceEnd, BX_IA_RSM },
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/* 0F AB /qr */ { 0, BX_IA_BTS_EqGqR },
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/* 0F AC /qr */ { BxImmediate_Ib, BX_IA_SHRD_EqGq },
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/* 0F AD /qr */ { 0, BX_IA_SHRD_EqGq },
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/* 0F AC /qr */ { BxImmediate_Ib, BX_IA_SHRD_EqGqR },
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/* 0F AD /qr */ { 0, BX_IA_SHRD_EqGqR },
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/* 0F AE /qr */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15R },
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/* 0F AF /qr */ { 0, BX_IA_IMUL_GqEq },
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/* 0F B0 /qr */ { 0, BX_IA_CMPXCHG_EbGbR },
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@ -2201,16 +2201,16 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
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/* 0F A1 /wm */ { 0, BX_IA_POP16_FS },
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/* 0F A2 /wm */ { 0, BX_IA_CPUID },
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/* 0F A3 /wm */ { 0, BX_IA_BT_EwGwM },
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/* 0F A4 /wm */ { BxImmediate_Ib, BX_IA_SHLD_EwGw },
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/* 0F A5 /wm */ { 0, BX_IA_SHLD_EwGw },
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/* 0F A4 /wm */ { BxImmediate_Ib, BX_IA_SHLD_EwGwM },
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/* 0F A5 /wm */ { 0, BX_IA_SHLD_EwGwM },
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/* 0F A6 /wm */ { 0, BX_IA_ERROR },
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/* 0F A7 /wm */ { 0, BX_IA_ERROR },
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/* 0F A8 /wm */ { 0, BX_IA_PUSH16_GS },
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/* 0F A9 /wm */ { 0, BX_IA_POP16_GS },
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/* 0F AA /wm */ { BxTraceEnd, BX_IA_RSM },
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/* 0F AB /wm */ { BxLockable, BX_IA_BTS_EwGwM },
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/* 0F AC /wm */ { BxImmediate_Ib, BX_IA_SHRD_EwGw },
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/* 0F AD /wm */ { 0, BX_IA_SHRD_EwGw },
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/* 0F AC /wm */ { BxImmediate_Ib, BX_IA_SHRD_EwGwM },
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/* 0F AD /wm */ { 0, BX_IA_SHRD_EwGwM },
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/* 0F AE /wm */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15M },
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/* 0F AF /wm */ { 0, BX_IA_IMUL_GwEw },
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/* 0F B0 /wm */ { BxLockable, BX_IA_CMPXCHG_EbGbM },
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@ -2728,16 +2728,16 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
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/* 0F A1 /dm */ { 0, BX_IA_POP64_FS },
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/* 0F A2 /dm */ { 0, BX_IA_CPUID },
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/* 0F A3 /dm */ { 0, BX_IA_BT_EdGdM },
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/* 0F A4 /dm */ { BxImmediate_Ib, BX_IA_SHLD_EdGd },
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/* 0F A5 /dm */ { 0, BX_IA_SHLD_EdGd },
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/* 0F A4 /dm */ { BxImmediate_Ib, BX_IA_SHLD_EdGdM },
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/* 0F A5 /dm */ { 0, BX_IA_SHLD_EdGdM },
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/* 0F A6 /dm */ { 0, BX_IA_ERROR },
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/* 0F A7 /dm */ { 0, BX_IA_ERROR },
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/* 0F A8 /dm */ { 0, BX_IA_PUSH64_GS },
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/* 0F A9 /dm */ { 0, BX_IA_POP64_GS },
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/* 0F AA /dm */ { BxTraceEnd, BX_IA_RSM },
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/* 0F AB /dm */ { BxLockable, BX_IA_BTS_EdGdM },
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/* 0F AC /dm */ { BxImmediate_Ib, BX_IA_SHRD_EdGd },
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/* 0F AD /dm */ { 0, BX_IA_SHRD_EdGd },
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/* 0F AC /dm */ { BxImmediate_Ib, BX_IA_SHRD_EdGdM },
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/* 0F AD /dm */ { 0, BX_IA_SHRD_EdGdM },
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/* 0F AE /dm */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15M },
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/* 0F AF /dm */ { 0, BX_IA_IMUL_GdEd },
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/* 0F B0 /dm */ { BxLockable, BX_IA_CMPXCHG_EbGbM },
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@ -3255,16 +3255,16 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
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/* 0F A1 /qm */ { 0, BX_IA_POP64_FS },
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/* 0F A2 /qm */ { 0, BX_IA_CPUID },
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/* 0F A3 /qm */ { 0, BX_IA_BT_EqGqM },
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/* 0F A4 /qm */ { BxImmediate_Ib, BX_IA_SHLD_EqGq },
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/* 0F A5 /qm */ { 0, BX_IA_SHLD_EqGq },
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/* 0F A4 /qm */ { BxImmediate_Ib, BX_IA_SHLD_EqGqM },
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/* 0F A5 /qm */ { 0, BX_IA_SHLD_EqGqM },
|
||||
/* 0F A6 /qm */ { 0, BX_IA_ERROR },
|
||||
/* 0F A7 /qm */ { 0, BX_IA_ERROR },
|
||||
/* 0F A8 /qm */ { 0, BX_IA_PUSH64_GS },
|
||||
/* 0F A9 /qm */ { 0, BX_IA_POP64_GS },
|
||||
/* 0F AA /qm */ { BxTraceEnd, BX_IA_RSM },
|
||||
/* 0F AB /qm */ { BxLockable, BX_IA_BTS_EqGqM },
|
||||
/* 0F AC /qm */ { BxImmediate_Ib, BX_IA_SHRD_EqGq },
|
||||
/* 0F AD /qm */ { 0, BX_IA_SHRD_EqGq },
|
||||
/* 0F AC /qm */ { BxImmediate_Ib, BX_IA_SHRD_EqGqM },
|
||||
/* 0F AD /qm */ { 0, BX_IA_SHRD_EqGqM },
|
||||
/* 0F AE /qm */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15M },
|
||||
/* 0F AF /qm */ { 0, BX_IA_IMUL_GqEq },
|
||||
/* 0F B0 /qm */ { BxLockable, BX_IA_CMPXCHG_EbGbM },
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: ia_opcodes.h,v 1.2 2008-04-05 17:51:55 sshwarts Exp $
|
||||
// $Id: ia_opcodes.h,v 1.3 2008-04-05 19:08:01 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2008 Stanislav Shwartsman
|
||||
@ -25,6 +25,8 @@ bx_define_opcode(BX_IA_AAA, BX_CPU_C::AAA)
|
||||
bx_define_opcode(BX_IA_AAD, BX_CPU_C::AAD)
|
||||
bx_define_opcode(BX_IA_AAM, BX_CPU_C::AAM)
|
||||
bx_define_opcode(BX_IA_AAS, BX_CPU_C::AAS)
|
||||
bx_define_opcode(BX_IA_DAA, BX_CPU_C::DAA)
|
||||
bx_define_opcode(BX_IA_DAS, BX_CPU_C::DAS)
|
||||
bx_define_opcode(BX_IA_ADC_ALIb, BX_CPU_C::ADC_ALIb)
|
||||
bx_define_opcode(BX_IA_ADC_AXIw, BX_CPU_C::ADC_AXIw)
|
||||
bx_define_opcode(BX_IA_ADC_EAXId, BX_CPU_C::ADC_EAXId)
|
||||
@ -244,8 +246,6 @@ bx_define_opcode(BX_IA_CMPXCHG8B, BX_CPU_C::CMPXCHG8B)
|
||||
bx_define_opcode(BX_IA_CPUID, BX_CPU_C::CPUID)
|
||||
bx_define_opcode(BX_IA_CWD, BX_CPU_C::CWD)
|
||||
bx_define_opcode(BX_IA_CWDE, BX_CPU_C::CWDE)
|
||||
bx_define_opcode(BX_IA_DAA, BX_CPU_C::DAA)
|
||||
bx_define_opcode(BX_IA_DAS, BX_CPU_C::DAS)
|
||||
bx_define_opcode(BX_IA_DEC_EbM, BX_CPU_C::DEC_EbM)
|
||||
bx_define_opcode(BX_IA_DEC_EbR, BX_CPU_C::DEC_EbR)
|
||||
bx_define_opcode(BX_IA_DEC_EdM, BX_CPU_C::DEC_EdM)
|
||||
@ -257,7 +257,6 @@ bx_define_opcode(BX_IA_DIV_AXEw, BX_CPU_C::DIV_AXEw)
|
||||
bx_define_opcode(BX_IA_DIV_EAXEd, BX_CPU_C::DIV_EAXEd)
|
||||
bx_define_opcode(BX_IA_ENTER16_IwIb, BX_CPU_C::ENTER16_IwIb)
|
||||
bx_define_opcode(BX_IA_ENTER32_IwIb, BX_CPU_C::ENTER32_IwIb)
|
||||
bx_define_opcode(BX_IA_FWAIT, BX_CPU_C::FWAIT)
|
||||
bx_define_opcode(BX_IA_HLT, BX_CPU_C::HLT)
|
||||
bx_define_opcode(BX_IA_IDIV_ALEb, BX_CPU_C::IDIV_ALEb)
|
||||
bx_define_opcode(BX_IA_IDIV_AXEw, BX_CPU_C::IDIV_AXEw)
|
||||
@ -356,6 +355,7 @@ bx_define_opcode(BX_IA_LSS_GdMp, BX_CPU_C::LSS_GdMp)
|
||||
bx_define_opcode(BX_IA_LSS_GwMp, BX_CPU_C::LSS_GwMp)
|
||||
bx_define_opcode(BX_IA_LTR_Ew, BX_CPU_C::LTR_Ew)
|
||||
bx_define_opcode(BX_IA_MONITOR, BX_CPU_C::MONITOR)
|
||||
bx_define_opcode(BX_IA_MWAIT, BX_CPU_C::MWAIT)
|
||||
bx_define_opcode(BX_IA_MOV_ALOd, BX_CPU_C::MOV_ALOd)
|
||||
bx_define_opcode(BX_IA_MOV_AXOd, BX_CPU_C::MOV_AXOd)
|
||||
bx_define_opcode(BX_IA_MOV_CdRd, BX_CPU_C::MOV_CdRd)
|
||||
@ -408,7 +408,6 @@ bx_define_opcode(BX_IA_MOVZX_GwEbR, BX_CPU_C::MOVZX_GwEbR)
|
||||
bx_define_opcode(BX_IA_MUL_ALEb, BX_CPU_C::MUL_ALEb)
|
||||
bx_define_opcode(BX_IA_MUL_AXEw, BX_CPU_C::MUL_AXEw)
|
||||
bx_define_opcode(BX_IA_MUL_EAXEd, BX_CPU_C::MUL_EAXEd)
|
||||
bx_define_opcode(BX_IA_MWAIT, BX_CPU_C::MWAIT)
|
||||
bx_define_opcode(BX_IA_NEG_EbM, BX_CPU_C::NEG_EbM)
|
||||
bx_define_opcode(BX_IA_NEG_EbR, BX_CPU_C::NEG_EbR)
|
||||
bx_define_opcode(BX_IA_NEG_EdM, BX_CPU_C::NEG_EdM)
|
||||
@ -602,13 +601,17 @@ bx_define_opcode(BX_IA_SGDT_Ms, BX_CPU_C::SGDT_Ms)
|
||||
bx_define_opcode(BX_IA_SHL_Eb, BX_CPU_C::SHL_Eb)
|
||||
bx_define_opcode(BX_IA_SHL_Ed, BX_CPU_C::SHL_Ed)
|
||||
bx_define_opcode(BX_IA_SHL_Ew, BX_CPU_C::SHL_Ew)
|
||||
bx_define_opcode(BX_IA_SHLD_EdGd, BX_CPU_C::SHLD_EdGd)
|
||||
bx_define_opcode(BX_IA_SHLD_EwGw, BX_CPU_C::SHLD_EwGw)
|
||||
bx_define_opcode(BX_IA_SHLD_EdGdR, BX_CPU_C::SHLD_EdGdR)
|
||||
bx_define_opcode(BX_IA_SHLD_EdGdM, BX_CPU_C::SHLD_EdGdM)
|
||||
bx_define_opcode(BX_IA_SHLD_EwGwR, BX_CPU_C::SHLD_EwGwR)
|
||||
bx_define_opcode(BX_IA_SHLD_EwGwM, BX_CPU_C::SHLD_EwGwM)
|
||||
bx_define_opcode(BX_IA_SHR_Eb, BX_CPU_C::SHR_Eb)
|
||||
bx_define_opcode(BX_IA_SHR_Ed, BX_CPU_C::SHR_Ed)
|
||||
bx_define_opcode(BX_IA_SHR_Ew, BX_CPU_C::SHR_Ew)
|
||||
bx_define_opcode(BX_IA_SHRD_EdGd, BX_CPU_C::SHRD_EdGd)
|
||||
bx_define_opcode(BX_IA_SHRD_EwGw, BX_CPU_C::SHRD_EwGw)
|
||||
bx_define_opcode(BX_IA_SHRD_EdGdR, BX_CPU_C::SHRD_EdGdR)
|
||||
bx_define_opcode(BX_IA_SHRD_EdGdM, BX_CPU_C::SHRD_EdGdM)
|
||||
bx_define_opcode(BX_IA_SHRD_EwGwR, BX_CPU_C::SHRD_EwGwR)
|
||||
bx_define_opcode(BX_IA_SHRD_EwGwM, BX_CPU_C::SHRD_EwGwM)
|
||||
bx_define_opcode(BX_IA_SIDT_Ms, BX_CPU_C::SIDT_Ms)
|
||||
bx_define_opcode(BX_IA_SLDT_Ew, BX_CPU_C::SLDT_Ew)
|
||||
bx_define_opcode(BX_IA_SMSW_Ew, BX_CPU_C::SMSW_Ew)
|
||||
@ -697,6 +700,7 @@ bx_define_opcode(BX_IA_XOR_GdEdR, BX_CPU_C::XOR_GdEdR)
|
||||
bx_define_opcode(BX_IA_XOR_GwEwM, BX_CPU_C::XOR_GwEwM)
|
||||
bx_define_opcode(BX_IA_XOR_GwEwR, BX_CPU_C::XOR_GwEwR)
|
||||
|
||||
bx_define_opcode(BX_IA_FWAIT, BX_CPU_C::FWAIT)
|
||||
#if BX_SUPPORT_FPU
|
||||
bx_define_opcode(BX_IA_FLD_STi, BX_CPU_C::FLD_STi)
|
||||
bx_define_opcode(BX_IA_FLD_SINGLE_REAL, BX_CPU_C::FLD_SINGLE_REAL)
|
||||
@ -1362,8 +1366,10 @@ bx_define_opcode(BX_IA_MOV_CqRq, BX_CPU_C::MOV_CqRq)
|
||||
bx_define_opcode(BX_IA_MOV_DqRq, BX_CPU_C::MOV_DqRq)
|
||||
bx_define_opcode(BX_IA_MOV_RqCq, BX_CPU_C::MOV_RqCq)
|
||||
bx_define_opcode(BX_IA_MOV_RqDq, BX_CPU_C::MOV_RqDq)
|
||||
bx_define_opcode(BX_IA_SHLD_EqGq, BX_CPU_C::SHLD_EqGq)
|
||||
bx_define_opcode(BX_IA_SHRD_EqGq, BX_CPU_C::SHRD_EqGq)
|
||||
bx_define_opcode(BX_IA_SHLD_EqGqR, BX_CPU_C::SHLD_EqGqR)
|
||||
bx_define_opcode(BX_IA_SHLD_EqGqM, BX_CPU_C::SHLD_EqGqM)
|
||||
bx_define_opcode(BX_IA_SHRD_EqGqR, BX_CPU_C::SHRD_EqGqR)
|
||||
bx_define_opcode(BX_IA_SHRD_EqGqM, BX_CPU_C::SHRD_EqGqM)
|
||||
bx_define_opcode(BX_IA_IMUL_GqEq, BX_CPU_C::IMUL_GqEq)
|
||||
bx_define_opcode(BX_IA_IMUL_GqEqId, BX_CPU_C::IMUL_GqEqId)
|
||||
bx_define_opcode(BX_IA_MOVZX_GqEbM, BX_CPU_C::MOVZX_GqEbM)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: shift16.cc,v 1.45 2008-04-05 17:51:55 sshwarts Exp $
|
||||
// $Id: shift16.cc,v 1.46 2008-04-05 19:08:01 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -30,7 +30,7 @@
|
||||
#include "cpu.h"
|
||||
#define LOG_THIS BX_CPU_THIS_PTR
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EwGw(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EwGwM(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, op2_16, result_16;
|
||||
Bit32u temp_32, result_32;
|
||||
@ -45,15 +45,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EwGw(bxInstruction_c *i)
|
||||
|
||||
count &= 0x1f; // use only 5 LSB's
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_16 = BX_READ_16BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op1_16 = read_RMW_virtual_word(i->seg(), RMAddr(i));
|
||||
}
|
||||
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
/* pointer, segment address pair */
|
||||
op1_16 = read_RMW_virtual_word(i->seg(), RMAddr(i));
|
||||
|
||||
if (!count) return;
|
||||
|
||||
@ -70,15 +65,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EwGw(bxInstruction_c *i)
|
||||
result_32 |= (op1_16 << (count - 16));
|
||||
}
|
||||
|
||||
result_16 = result_32 >> 16;
|
||||
result_16 = (Bit16u)(result_32 >> 16);
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
}
|
||||
else {
|
||||
write_RMW_virtual_word(result_16);
|
||||
}
|
||||
write_RMW_virtual_word(result_16);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(result_16); /* handle SF, ZF and AF flags */
|
||||
|
||||
@ -87,7 +76,49 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EwGw(bxInstruction_c *i)
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EwGw(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EwGwR(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, op2_16, result_16;
|
||||
Bit32u temp_32, result_32;
|
||||
unsigned count;
|
||||
unsigned of, cf;
|
||||
|
||||
/* op1:op2 << count. result stored in op1 */
|
||||
if (i->b1() == 0xa4) // 0x1a4
|
||||
count = i->Ib();
|
||||
else // 0x1a5
|
||||
count = CL;
|
||||
|
||||
count &= 0x1f; // use only 5 LSB's
|
||||
|
||||
if (!count) return;
|
||||
|
||||
op1_16 = BX_READ_16BIT_REG(i->rm());
|
||||
op2_16 = BX_READ_16BIT_REG(i->nnn());
|
||||
|
||||
/* count < 32, since only lower 5 bits used */
|
||||
temp_32 = ((Bit32u)(op1_16) << 16) | (op2_16); // double formed by op1:op2
|
||||
result_32 = temp_32 << count;
|
||||
|
||||
// hack to act like x86 SHLD when count > 16
|
||||
if (count > 16) {
|
||||
// when count > 16 actually shifting op1:op2:op2 << count,
|
||||
// it is the same as shifting op2:op2 by count-16
|
||||
result_32 |= (op1_16 << (count - 16));
|
||||
}
|
||||
|
||||
result_16 = (Bit16u)(result_32 >> 16);
|
||||
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(result_16); /* handle SF, ZF and AF flags */
|
||||
|
||||
cf = (temp_32 >> (32 - count)) & 0x1;
|
||||
of = cf ^ (result_16 >> 15); // of = cf ^ result15
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EwGwM(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, op2_16, result_16;
|
||||
Bit32u temp_32, result_32;
|
||||
@ -101,15 +132,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EwGw(bxInstruction_c *i)
|
||||
|
||||
count &= 0x1f; /* use only 5 LSB's */
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_16 = BX_READ_16BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op1_16 = read_RMW_virtual_word(i->seg(), RMAddr(i));
|
||||
}
|
||||
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
/* pointer, segment address pair */
|
||||
op1_16 = read_RMW_virtual_word(i->seg(), RMAddr(i));
|
||||
|
||||
if (!count) return;
|
||||
|
||||
@ -126,16 +152,51 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EwGw(bxInstruction_c *i)
|
||||
result_32 |= (op1_16 << (32 - count));
|
||||
}
|
||||
|
||||
result_16 = result_32;
|
||||
result_16 = (Bit16u) result_32;
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
}
|
||||
else {
|
||||
write_RMW_virtual_word(result_16);
|
||||
write_RMW_virtual_word(result_16);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(result_16); /* handle SF, ZF and AF flags */
|
||||
|
||||
cf = (op1_16 >> (count - 1)) & 0x1;
|
||||
of = ((result_16 << 1) ^ result_16) >> 15; // of = result14 ^ result15
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EwGwR(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, op2_16, result_16;
|
||||
Bit32u temp_32, result_32;
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xac) // 0x1ac
|
||||
count = i->Ib();
|
||||
else // 0x1ad
|
||||
count = CL;
|
||||
|
||||
count &= 0x1f; /* use only 5 LSB's */
|
||||
|
||||
if (!count) return;
|
||||
|
||||
op1_16 = BX_READ_16BIT_REG(i->rm());
|
||||
op2_16 = BX_READ_16BIT_REG(i->nnn());
|
||||
|
||||
/* count < 32, since only lower 5 bits used */
|
||||
temp_32 = (op2_16 << 16) | op1_16; // double formed by op2:op1
|
||||
result_32 = temp_32 >> count;
|
||||
|
||||
// hack to act like x86 SHRD when count > 16
|
||||
if (count > 16) {
|
||||
// when count > 16 actually shifting op2:op2:op1 >> count,
|
||||
// it is the same as shifting op2:op2 by count-16
|
||||
result_32 |= (op1_16 << (32 - count));
|
||||
}
|
||||
|
||||
result_16 = (Bit16u) result_32;
|
||||
|
||||
BX_WRITE_16BIT_REG(i->rm(), result_16);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(result_16); /* handle SF, ZF and AF flags */
|
||||
|
||||
cf = (op1_16 >> (count - 1)) & 0x1;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: shift32.cc,v 1.43 2008-04-05 17:51:55 sshwarts Exp $
|
||||
// $Id: shift32.cc,v 1.44 2008-04-05 19:08:01 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -30,7 +30,7 @@
|
||||
#include "cpu.h"
|
||||
#define LOG_THIS BX_CPU_THIS_PTR
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EdGd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EdGdM(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, op2_32, result_32;
|
||||
unsigned count;
|
||||
@ -43,15 +43,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EdGd(bxInstruction_c *i)
|
||||
|
||||
count &= 0x1f; // use only 5 LSB's
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op1_32 = read_RMW_virtual_dword(i->seg(), RMAddr(i));
|
||||
}
|
||||
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
/* pointer, segment address pair */
|
||||
op1_32 = read_RMW_virtual_dword(i->seg(), RMAddr(i));
|
||||
|
||||
if (!count) return;
|
||||
|
||||
@ -59,13 +54,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EdGd(bxInstruction_c *i)
|
||||
|
||||
result_32 = (op1_32 << count) | (op2_32 >> (32 - count));
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
write_RMW_virtual_dword(result_32);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
|
||||
|
||||
@ -74,7 +63,36 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EdGd(bxInstruction_c *i)
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EdGd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EdGdR(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, op2_32, result_32;
|
||||
unsigned count;
|
||||
unsigned of, cf;
|
||||
|
||||
if (i->b1() == 0xa4) // 0x1a4
|
||||
count = i->Ib();
|
||||
else // 0x1a5
|
||||
count = CL;
|
||||
|
||||
count &= 0x1f; // use only 5 LSB's
|
||||
|
||||
if (!count) return;
|
||||
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
op2_32 = BX_READ_32BIT_REG(i->nnn());
|
||||
|
||||
result_32 = (op1_32 << count) | (op2_32 >> (32 - count));
|
||||
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
|
||||
|
||||
cf = (op1_32 >> (32 - count)) & 0x1;
|
||||
of = cf ^ (result_32 >> 31); // of = cf ^ result31
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EdGdM(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, op2_32, result_32;
|
||||
unsigned count;
|
||||
@ -87,15 +105,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EdGd(bxInstruction_c *i)
|
||||
|
||||
count &= 0x1f; // use only 5 LSB's
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op1_32 = read_RMW_virtual_dword(i->seg(), RMAddr(i));
|
||||
}
|
||||
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
/* pointer, segment address pair */
|
||||
op1_32 = read_RMW_virtual_dword(i->seg(), RMAddr(i));
|
||||
|
||||
if (!count) return;
|
||||
|
||||
@ -103,13 +116,36 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EdGd(bxInstruction_c *i)
|
||||
|
||||
result_32 = (op2_32 << (32 - count)) | (op1_32 >> count);
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
}
|
||||
else {
|
||||
write_RMW_virtual_dword(result_32);
|
||||
}
|
||||
write_RMW_virtual_dword(result_32);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
|
||||
|
||||
cf = (op1_32 >> (count - 1)) & 0x1;
|
||||
of = ((result_32 << 1) ^ result_32) >> 31; // of = result30 ^ result31
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EdGdR(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, op2_32, result_32;
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xac) // 0x1ac
|
||||
count = i->Ib();
|
||||
else // 0x1ad
|
||||
count = CL;
|
||||
|
||||
count &= 0x1f; // use only 5 LSB's
|
||||
|
||||
if (!count) return;
|
||||
|
||||
op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
op2_32 = BX_READ_32BIT_REG(i->nnn());
|
||||
|
||||
result_32 = (op2_32 << (32 - count)) | (op1_32 >> count);
|
||||
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: shift64.cc,v 1.34 2008-04-05 17:51:55 sshwarts Exp $
|
||||
// $Id: shift64.cc,v 1.35 2008-04-05 19:08:01 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -32,7 +32,7 @@
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGqM(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64, result_64;
|
||||
unsigned count;
|
||||
@ -45,15 +45,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGq(bxInstruction_c *i)
|
||||
|
||||
count &= 0x3f; // use only 6 LSB's
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op1_64 = read_RMW_virtual_qword(i->seg(), RMAddr(i));
|
||||
}
|
||||
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
/* pointer, segment address pair */
|
||||
op1_64 = read_RMW_virtual_qword(i->seg(), RMAddr(i));
|
||||
|
||||
if (!count) return;
|
||||
|
||||
@ -61,13 +56,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGq(bxInstruction_c *i)
|
||||
|
||||
result_64 = (op1_64 << count) | (op2_64 >> (64 - count));
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
write_RMW_virtual_qword(result_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
|
||||
|
||||
@ -76,7 +65,36 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGq(bxInstruction_c *i)
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGqR(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64, result_64;
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xa4) // 0x1a4
|
||||
count = i->Ib();
|
||||
else // 0x1a5
|
||||
count = CL;
|
||||
|
||||
count &= 0x3f; // use only 6 LSB's
|
||||
|
||||
if (!count) return;
|
||||
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
||||
|
||||
result_64 = (op1_64 << count) | (op2_64 >> (64 - count));
|
||||
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
|
||||
|
||||
cf = (op1_64 >> (64 - count)) & 0x1;
|
||||
of = cf ^ (result_64 >> 63); // of = cf ^ result63
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGqM(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64, result_64;
|
||||
unsigned count;
|
||||
@ -89,15 +107,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGq(bxInstruction_c *i)
|
||||
|
||||
count &= 0x3f; // use only 6 LSB's
|
||||
|
||||
/* op1 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op1_64 = read_RMW_virtual_qword(i->seg(), RMAddr(i));
|
||||
}
|
||||
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
/* pointer, segment address pair */
|
||||
op1_64 = read_RMW_virtual_qword(i->seg(), RMAddr(i));
|
||||
|
||||
if (!count) return;
|
||||
|
||||
@ -105,13 +118,36 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGq(bxInstruction_c *i)
|
||||
|
||||
result_64 = (op2_64 << (64 - count)) | (op1_64 >> count);
|
||||
|
||||
/* now write result back to destination */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
}
|
||||
else {
|
||||
write_RMW_virtual_qword(result_64);
|
||||
}
|
||||
write_RMW_virtual_qword(result_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
|
||||
|
||||
cf = (op1_64 >> (count - 1)) & 0x1;
|
||||
of = ((result_64 << 1) ^ result_64) >> 63; // of = result62 ^ result63
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGqR(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64, result_64;
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xac) // 0x1ac
|
||||
count = i->Ib();
|
||||
else // 0x1ad
|
||||
count = CL;
|
||||
|
||||
count &= 0x3f; // use only 6 LSB's
|
||||
|
||||
if (!count) return;
|
||||
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
||||
|
||||
result_64 = (op2_64 << (64 - count)) | (op1_64 >> count);
|
||||
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user