split opcodes by ModC0
This commit is contained in:
Stanislav Shwartsman
parent
a259ba7321
commit
8e3276cf14
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.607 2009-08-10 15:44:49 sshwarts Exp $
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// $Id: cpu.h,v 1.608 2009-08-22 11:47:42 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1953,8 +1953,10 @@ public: // for now...
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BX_SMF void MOVHPS_MqVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVAPS_VpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVAPS_WpsVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPI2PS_VpsQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSI2SS_VssEd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPI2PS_VpsQqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPI2PS_VpsQqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSI2SS_VssEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSI2SS_VssEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVNTPS_MpsVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTTPS2PI_PqWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTTSS2SI_GdWss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -2004,8 +2006,10 @@ public: // for now...
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/* SSE2 */
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BX_SMF void MOVSD_VsdWsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVSD_WsdVsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPI2PD_VpdQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSI2SD_VsdEd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPI2PD_VpdQqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPI2PD_VpdQqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSI2SD_VsdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSI2SD_VsdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTTPD2PI_PqWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTTSD2SI_GdWsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPD2PI_PqWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.227 2009-04-06 18:44:28 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.228 2009-08-22 11:47:42 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -536,7 +536,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* 0F 27 /wr */ { 0, BX_IA_ERROR },
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/* 0F 28 /wr */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
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/* 0F 29 /wr */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
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/* 0F 2A /wr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
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/* 0F 2A /wr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqR, BxOpcodeGroupSSE_0f2aR },
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/* 0F 2B /wr */ { 0, BX_IA_ERROR }, // MOVNTPS/PD/SS/SD
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/* 0F 2C /wr */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /wr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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@ -1099,7 +1099,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* 0F 27 /dr */ { 0, BX_IA_ERROR },
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/* 0F 28 /dr */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
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/* 0F 29 /dr */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
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/* 0F 2A /dr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
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/* 0F 2A /dr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqR, BxOpcodeGroupSSE_0f2aR },
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/* 0F 2B /dr */ { 0, BX_IA_ERROR }, // MOVNTPS/PD/SS/SD
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/* 0F 2C /dr */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /dr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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@ -1669,7 +1669,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* 0F 27 /wm */ { 0, BX_IA_ERROR },
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/* 0F 28 /wm */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
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/* 0F 29 /wm */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
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/* 0F 2A /wm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
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/* 0F 2A /wm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqM, BxOpcodeGroupSSE_0f2aM },
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/* 0F 2B /wm */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
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/* 0F 2C /wm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /wm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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@ -2232,7 +2232,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* 0F 27 /dm */ { 0, BX_IA_ERROR },
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/* 0F 28 /dm */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
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/* 0F 29 /dm */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
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/* 0F 2A /dm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
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/* 0F 2A /dm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqM, BxOpcodeGroupSSE_0f2aM },
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/* 0F 2B /dm */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
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/* 0F 2C /dm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /dm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.h,v 1.87 2009-08-15 15:43:40 sshwarts Exp $
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// $Id: fetchdecode.h,v 1.88 2009-08-22 11:47:42 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005 Stanislav Shwartsman
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@ -1072,10 +1072,16 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f29[3] = {
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/* F3 */ { 0, BX_IA_ERROR }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2a[3] = {
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/* 66 */ { 0, BX_IA_CVTPI2PD_VpdQq },
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/* F2 */ { 0, BX_IA_CVTSI2SD_VsdEd },
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/* F3 */ { 0, BX_IA_CVTSI2SS_VssEd }
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2aR[3] = {
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/* 66 */ { 0, BX_IA_CVTPI2PD_VpdQqR },
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/* F2 */ { 0, BX_IA_CVTSI2SD_VsdEdR },
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/* F3 */ { 0, BX_IA_CVTSI2SS_VssEdR }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2aM[3] = {
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/* 66 */ { 0, BX_IA_CVTPI2PD_VpdQqM },
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/* F2 */ { 0, BX_IA_CVTSI2SD_VsdEdM },
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/* F3 */ { 0, BX_IA_CVTSI2SS_VssEdM }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2bM[3] = {
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode64.cc,v 1.230 2009-04-06 18:44:28 sshwarts Exp $
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// $Id: fetchdecode64.cc,v 1.231 2009-08-22 11:47:42 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -484,7 +484,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
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/* 0F 27 /wr */ { 0, BX_IA_ERROR },
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/* 0F 28 /wr */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
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/* 0F 29 /wr */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
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/* 0F 2A /wr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
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/* 0F 2A /wr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqR, BxOpcodeGroupSSE_0f2aR },
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/* 0F 2B /wr */ { 0, BX_IA_ERROR }, // MOVNTPS/PD/SS/SD
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/* 0F 2C /wr */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /wr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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@ -1011,7 +1011,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
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/* 0F 27 /dr */ { 0, BX_IA_ERROR },
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/* 0F 28 /dr */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
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/* 0F 29 /dr */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
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/* 0F 2A /dr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
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/* 0F 2A /dr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqR, BxOpcodeGroupSSE_0f2aR },
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/* 0F 2B /dr */ { 0, BX_IA_ERROR }, // MOVNTPS/PD/SS/SD
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/* 0F 2C /dr */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /dr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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@ -1538,7 +1538,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
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/* 0F 27 /qr */ { 0, BX_IA_ERROR },
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/* 0F 28 /qr */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
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/* 0F 29 /qr */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
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/* 0F 2A /qr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
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/* 0F 2A /qr */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqR, BxOpcodeGroupSSE_0f2aR },
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/* 0F 2B /qr */ { 0, BX_IA_ERROR }, // MOVNTPS/PD/SS/SD
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/* 0F 2C /qr */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /qr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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@ -2071,7 +2071,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
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/* 0F 27 /wm */ { 0, BX_IA_ERROR },
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/* 0F 28 /wm */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
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/* 0F 29 /wm */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
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/* 0F 2A /wm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
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/* 0F 2A /wm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqM, BxOpcodeGroupSSE_0f2aM },
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/* 0F 2B /wm */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
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/* 0F 2C /wm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /wm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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@ -2598,7 +2598,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
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/* 0F 27 /dm */ { 0, BX_IA_ERROR },
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/* 0F 28 /dm */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
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/* 0F 29 /dm */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
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/* 0F 2A /dm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
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/* 0F 2A /dm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqM, BxOpcodeGroupSSE_0f2aM },
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/* 0F 2B /dm */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
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/* 0F 2C /dm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /dm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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@ -3125,7 +3125,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
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/* 0F 27 /qm */ { 0, BX_IA_ERROR },
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/* 0F 28 /qm */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
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/* 0F 29 /qm */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
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/* 0F 2A /qm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
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/* 0F 2A /qm */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQqM, BxOpcodeGroupSSE_0f2aM },
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/* 0F 2B /qm */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
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/* 0F 2C /qm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /qm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: ia_opcodes.h,v 1.27 2009-04-06 18:44:28 sshwarts Exp $
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// $Id: ia_opcodes.h,v 1.28 2009-08-22 11:47:42 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2008 Stanislav Shwartsman
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@ -937,8 +937,10 @@ bx_define_opcode(BX_IA_MOVHPS_VpsMq, &BX_CPU_C::MOVHPS_VpsMq, NULL)
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bx_define_opcode(BX_IA_MOVHPS_MqVps, &BX_CPU_C::MOVHPS_MqVps, NULL)
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bx_define_opcode(BX_IA_MOVAPS_VpsWps, &BX_CPU_C::MOVAPS_VpsWps, NULL)
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bx_define_opcode(BX_IA_MOVAPS_WpsVps, &BX_CPU_C::MOVAPS_WpsVps, NULL)
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bx_define_opcode(BX_IA_CVTPI2PS_VpsQq, &BX_CPU_C::CVTPI2PS_VpsQq, NULL)
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bx_define_opcode(BX_IA_CVTSI2SS_VssEd, &BX_CPU_C::CVTSI2SS_VssEd, NULL)
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bx_define_opcode(BX_IA_CVTPI2PS_VpsQqR, &BX_CPU_C::CVTPI2PS_VpsQqR, NULL)
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bx_define_opcode(BX_IA_CVTPI2PS_VpsQqM, &BX_CPU_C::CVTPI2PS_VpsQqM, NULL)
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bx_define_opcode(BX_IA_CVTSI2SS_VssEdR, &BX_CPU_C::CVTSI2SS_VssEdR, NULL)
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bx_define_opcode(BX_IA_CVTSI2SS_VssEdM, &BX_CPU_C::CVTSI2SS_VssEdM, NULL)
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bx_define_opcode(BX_IA_MOVNTPS_MpsVps, &BX_CPU_C::MOVNTPS_MpsVps, NULL)
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bx_define_opcode(BX_IA_CVTTPS2PI_PqWps, &BX_CPU_C::CVTTPS2PI_PqWps, NULL)
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bx_define_opcode(BX_IA_CVTTSS2SI_GdWss, &BX_CPU_C::CVTTSS2SI_GdWss, NULL)
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@ -988,8 +990,10 @@ bx_define_opcode(BX_IA_MASKMOVQ_PqPRq, &BX_CPU_C::MASKMOVQ_PqPRq, NULL)
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// SSE2
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bx_define_opcode(BX_IA_MOVSD_VsdWsd, &BX_CPU_C::MOVSD_VsdWsd, NULL)
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bx_define_opcode(BX_IA_MOVSD_WsdVsd, &BX_CPU_C::MOVSD_WsdVsd, NULL)
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bx_define_opcode(BX_IA_CVTPI2PD_VpdQq, &BX_CPU_C::CVTPI2PD_VpdQq, NULL)
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bx_define_opcode(BX_IA_CVTSI2SD_VsdEd, &BX_CPU_C::CVTSI2SD_VsdEd, NULL)
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bx_define_opcode(BX_IA_CVTPI2PD_VpdQqR, &BX_CPU_C::CVTPI2PD_VpdQqR, NULL)
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bx_define_opcode(BX_IA_CVTPI2PD_VpdQqM, &BX_CPU_C::CVTPI2PD_VpdQqM, NULL)
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bx_define_opcode(BX_IA_CVTSI2SD_VsdEdR, &BX_CPU_C::CVTSI2SD_VsdEdR, NULL)
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bx_define_opcode(BX_IA_CVTSI2SD_VsdEdM, &BX_CPU_C::CVTSI2SD_VsdEdM, NULL)
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bx_define_opcode(BX_IA_CVTTPD2PI_PqWpd, &BX_CPU_C::CVTTPD2PI_PqWpd, NULL)
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bx_define_opcode(BX_IA_CVTTSD2SI_GdWsd, &BX_CPU_C::CVTTSD2SI_GdWsd, NULL)
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bx_define_opcode(BX_IA_CVTPD2PI_PqWpd, &BX_CPU_C::CVTPD2PI_PqWpd, NULL)
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: sse_pfp.cc,v 1.60 2009-08-22 11:02:45 sshwarts Exp $
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// $Id: sse_pfp.cc,v 1.61 2009-08-22 11:47:42 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2003 Stanislav Shwartsman
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@ -83,7 +83,34 @@ static float64_compare_method compare64[4] = {
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* to rounding control bits in MXCSR register.
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* Possible floating point exceptions: #P
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*/
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQqR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister result;
|
||||
|
||||
/* check floating point status word for a pending FPU exceptions */
|
||||
FPU_check_pending_exceptions();
|
||||
|
||||
BxPackedMmxRegister op = BX_READ_MMX_REG(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
|
||||
result.xmm32u(0) = int32_to_float32(MMXUD0(op), status_word);
|
||||
result.xmm32u(1) = int32_to_float32(MMXUD1(op), status_word);
|
||||
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
prepareFPU2MMX(); /* cause FPU2MMX state transition */
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), result.xmm64u(0));
|
||||
#else
|
||||
BX_INFO(("CVTPI2PS_VpsQq: required SSE, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQqM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
@ -91,19 +118,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQq(bxInstruction_c *i)
|
||||
BxPackedMmxRegister op;
|
||||
BxPackedXmmRegister result;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
/* check floating point status word for a pending FPU exceptions */
|
||||
FPU_check_pending_exceptions();
|
||||
op = BX_READ_MMX_REG(i->rm());
|
||||
prepareFPU2MMX(); /* cause FPU2MMX state transition */
|
||||
}
|
||||
else {
|
||||
// do not cause transition to MMX state if no MMX register touched
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);
|
||||
}
|
||||
// do not cause transition to MMX state if no MMX register touched
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -124,7 +141,30 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQq(bxInstruction_c *i)
|
||||
* Convert two 32bit signed integers from MMX/MEM to two double precision FP
|
||||
* Possible floating point exceptions: -
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQqR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister result;
|
||||
|
||||
/* check floating point status word for a pending FPU exceptions */
|
||||
FPU_check_pending_exceptions();
|
||||
prepareFPU2MMX(); /* cause FPU2MMX state transition */
|
||||
|
||||
BxPackedMmxRegister op = BX_READ_MMX_REG(i->rm());
|
||||
|
||||
result.xmm64u(0) = int32_to_float64(MMXUD0(op));
|
||||
result.xmm64u(1) = int32_to_float64(MMXUD1(op));
|
||||
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("CVTPI2PD_VpdQd: required SSE2, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQqM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
@ -132,19 +172,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQq(bxInstruction_c *i)
|
||||
BxPackedMmxRegister op;
|
||||
BxPackedXmmRegister result;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
/* check floating point status word for a pending FPU exceptions */
|
||||
FPU_check_pending_exceptions();
|
||||
op = BX_READ_MMX_REG(i->rm());
|
||||
prepareFPU2MMX(); /* cause FPU2MMX state transition */
|
||||
}
|
||||
else {
|
||||
// do not cause transition to MMX state if no MMX register touched
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);
|
||||
}
|
||||
// do not cause transition to MMX state if no MMX register touched
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);
|
||||
|
||||
result.xmm64u(0) = int32_to_float64(MMXUD0(op));
|
||||
result.xmm64u(1) = int32_to_float64(MMXUD1(op));
|
||||
@ -161,7 +191,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQq(bxInstruction_c *i)
|
||||
* Convert one 32bit signed integer to one double precision FP
|
||||
* Possible floating point exceptions: -
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SD_VsdEd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SD_VsdEdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
@ -171,37 +201,41 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SD_VsdEd(bxInstruction_c *i)
|
||||
float64 result;
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->os64L()) /* 64 bit operand size mode */
|
||||
if (i->os64L()) /* 64 bit operand size */
|
||||
result = int64_to_float64(BX_READ_64BIT_REG(i->rm()), status_word);
|
||||
else
|
||||
#endif
|
||||
result = int32_to_float64(BX_READ_32BIT_REG(i->rm()));
|
||||
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("CVTSI2SD_VsdEd: required SSE2, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SD_VsdEdM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
float64 result;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->os64L()) /* 64 bit operand size */
|
||||
{
|
||||
Bit64u op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op = read_virtual_qword_64(i->seg(), eaddr);
|
||||
}
|
||||
|
||||
Bit64u op = read_virtual_qword_64(i->seg(), eaddr);
|
||||
result = int64_to_float64(op, status_word);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
Bit32u op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op = read_virtual_dword(i->seg(), eaddr);
|
||||
}
|
||||
|
||||
Bit32u op = read_virtual_dword(i->seg(), eaddr);
|
||||
result = int32_to_float64(op);
|
||||
}
|
||||
|
||||
@ -220,7 +254,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SD_VsdEd(bxInstruction_c *i)
|
||||
* to rounding control bits in MXCSR register.
|
||||
* Possible floating point exceptions: #P
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SS_VssEd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SS_VssEdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
@ -230,37 +264,41 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SS_VssEd(bxInstruction_c *i)
|
||||
float32 result;
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->os64L()) /* 64 bit operand size mode */
|
||||
if (i->os64L()) /* 64 bit operand size */
|
||||
result = int64_to_float32(BX_READ_64BIT_REG(i->rm()), status_word);
|
||||
else
|
||||
#endif
|
||||
result = int32_to_float32(BX_READ_32BIT_REG(i->rm()), status_word);
|
||||
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("CVTSI2SS_VssEd: required SSE, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SS_VssEdM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
float32 result;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->os64L()) /* 64 bit operand size */
|
||||
{
|
||||
Bit64u op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op = read_virtual_qword_64(i->seg(), eaddr);
|
||||
}
|
||||
|
||||
Bit64u op = read_virtual_qword_64(i->seg(), eaddr);
|
||||
result = int64_to_float32(op, status_word);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
Bit32u op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op = read_virtual_dword(i->seg(), eaddr);
|
||||
}
|
||||
|
||||
Bit32u op = read_virtual_dword(i->seg(), eaddr);
|
||||
result = int32_to_float32(op, status_word);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user