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- support 64-bit write to MSR_TSC using WRMSR instruction

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- fixed save/restore param type for async_event
- fixed setting of reserved bits in upper part of CR4 in 64-bit mode
This commit is contained in:
Stanislav Shwartsman 2008-04-18 18:32:40 +00:00
parent ab76cbb4a0
commit 15e9dca062
3 changed files with 14 additions and 16 deletions
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4
bochs/cpu/cpu.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.456 2008-04-16 16:44:04 sshwarts Exp $
// $Id: cpu.h,v 1.457 2008-04-18 18:32:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -3115,7 +3115,7 @@ public: // for now...
#if BX_CPU_LEVEL >= 5
BX_SMF Bit64u get_TSC();
BX_SMF void set_TSC(Bit32u tsc);
BX_SMF void set_TSC(bx_address tsc);
#endif
#if BX_SUPPORT_FPU

5
bochs/cpu/init.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: init.cc,v 1.166 2008-04-16 16:44:05 sshwarts Exp $
// $Id: init.cc,v 1.167 2008-04-18 18:32:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -507,8 +507,9 @@ void BX_CPU_C::register_state(void)
local_apic.register_state(cpu);
#endif
BXRS_HEX_PARAM_SIMPLE32(cpu, async_event);
BXRS_PARAM_BOOL(cpu, EXT, EXT);
BXRS_PARAM_BOOL(cpu, async_event, async_event);
BXRS_PARAM_BOOL(cpu, INTR, INTR);
BXRS_PARAM_BOOL(cpu, smi_pending, smi_pending);
BXRS_PARAM_BOOL(cpu, nmi_pending, nmi_pending);

21
bochs/cpu/proc_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: proc_ctrl.cc,v 1.213 2008-04-16 16:44:05 sshwarts Exp $
// $Id: proc_ctrl.cc,v 1.214 2008-04-18 18:32:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1332,7 +1332,7 @@ void BX_CPU_C::SetCR0(Bit32u val_32)
bx_bool BX_CPU_C::SetCR4(bx_address val)
{
Bit32u oldCR4 = BX_CPU_THIS_PTR cr4.getRegister();
Bit32u allowMask = 0;
bx_address allowMask = 0;
// CR4 bits definitions:
// [31-19] Reserved, Must be Zero
@ -1409,7 +1409,6 @@ bx_bool BX_CPU_C::SetCR4(bx_address val)
return 0;
}
val &= allowMask; // Screen out unsupported bits. (not needed, for good measure)
BX_CPU_THIS_PTR cr4.setRegister(val);
pagingCR4Changed(oldCR4, BX_CPU_THIS_PTR cr4.getRegister());
return 1;
@ -1458,28 +1457,26 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDPMC(bxInstruction_c *i)
}
#if BX_CPU_LEVEL >= 5
Bit64u BX_CPU_C::get_TSC(void)
BX_CPP_INLINE Bit64u BX_CPU_C::get_TSC(void)
{
return bx_pc_system.time_ticks() - BX_CPU_THIS_PTR msr.tsc_last_reset;
}
void BX_CPU_C::set_TSC(Bit32u newval)
void BX_CPU_C::set_TSC(Bit64u newval)
{
// compute the correct setting of tsc_last_reset so that a get_TSC()
// will return newval
BX_CPU_THIS_PTR msr.tsc_last_reset =
bx_pc_system.time_ticks() - (Bit64u) newval;
BX_CPU_THIS_PTR msr.tsc_last_reset = bx_pc_system.time_ticks() - newval;
// verify
BX_ASSERT (get_TSC() == (Bit64u) newval);
BX_ASSERT (get_TSC() == newval);
}
#endif
void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDTSC(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 5
bx_bool tsd = BX_CPU_THIS_PTR cr4.get_TSD();
if ((tsd==0) || (tsd==1 && CPL==0)) {
if (! BX_CPU_THIS_PTR cr4.get_TSD() || CPL==0) {
// return ticks
Bit64u ticks = BX_CPU_THIS_PTR get_TSC();
RAX = (Bit32u) (ticks & 0xffffffff);
@ -1805,8 +1802,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::WRMSR(bxInstruction_c *i)
#endif /* BX_CPU_LEVEL == 5 */
case BX_MSR_TSC:
BX_CPU_THIS_PTR set_TSC(EAX); /* ignore the high 32bits */
BX_INFO(("WRMSR: wrote 0x%08x to MSR_TSC", EAX));
BX_CPU_THIS_PTR set_TSC(val64);
BX_INFO(("WRMSR: wrote 0x%08x%08x to MSR_TSC", EDX, EAX));
return;
/* MSR_APICBASE