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remove obsolete comments from fetchdecode

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This commit is contained in:
Stanislav Shwartsman 2004-09-06 20:22:39 +00:00
parent 00bf370db2
commit fc631037ff
3 changed files with 21 additions and 91 deletions
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25
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.174 2004-08-30 21:47:24 sshwarts Exp $
// $Id: cpu.h,v 1.175 2004-09-06 20:22:37 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -180,10 +180,6 @@
#define BX_READ_16BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].word.rx)
#define BX_READ_32BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].dword.erx)
#define BX_WRITE_16BIT_REG(index, val) {\
BX_CPU_THIS_PTR gen_reg[index].word.rx = val; \
}
#define BX_READ_16BIT_BASE_REG(var, index) {\
var = *BX_CPU_THIS_PTR _16bit_base_reg[index];\
}
@ -192,6 +188,14 @@
var = *BX_CPU_THIS_PTR _16bit_index_reg[index];\
}
#define BX_WRITE_16BIT_REG(index, val) {\
BX_CPU_THIS_PTR gen_reg[index].word.rx = val; \
}
#define BX_WRITE_32BIT_REG(index, val) {\
BX_CPU_THIS_PTR gen_reg[index].dword.erx = val; \
}
#if BX_SUPPORT_X86_64
#define BX_WRITE_8BIT_REGx(index, extended, val) {\
@ -200,9 +204,7 @@
else \
BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh = val; \
}
#define BX_WRITE_32BIT_REG(index, val) {\
BX_CPU_THIS_PTR gen_reg[index].dword.erx = val; \
}
#define BX_WRITE_32BIT_REGZ(index, val) {\
BX_CPU_THIS_PTR gen_reg[index].rrx = (Bit32u) val; \
}
@ -224,9 +226,6 @@
}
#define BX_WRITE_8BIT_REGx(index, ext, val) BX_WRITE_8BIT_REG(index, val)
#define BX_WRITE_32BIT_REG(index, val) {\
BX_CPU_THIS_PTR gen_reg[index].dword.erx = val; \
}
// For x86-32, I just pretend this one is like the macro above,
// so common code can be used.
#define BX_WRITE_32BIT_REGZ(index, val) {\
@ -326,9 +325,9 @@
#define BX_MODE_LONG_64 0x2
#if BX_SUPPORT_APIC
#define BX_CPU_INTR (BX_CPU_THIS_PTR INTR || BX_CPU_THIS_PTR local_apic.INTR)
#define BX_CPU_INTR (BX_CPU_THIS_PTR INTR || BX_CPU_THIS_PTR local_apic.INTR)
#else
#define BX_CPU_INTR BX_CPU_THIS_PTR INTR
#define BX_CPU_INTR BX_CPU_THIS_PTR INTR
#endif
class BX_CPU_C;

26
bochs/cpu/fetchdecode.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.cc,v 1.66 2004-08-28 08:41:46 sshwarts Exp $
// $Id: fetchdecode.cc,v 1.67 2004-09-06 20:22:38 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -39,30 +39,6 @@
///////////////////////////
// sign extended to osize:
// 6a push ib
// 6b imul gvevib
// 70..7f jo..jnle
// 83 G1 0..7 ADD..CMP Evib
// is 6b imul_gvevib sign extended? don't think
// I'm sign extending it properly in old decode/execute
// check all the groups. Make sure to add duplicates rather
// than error.
// mark instructions as changing control transfer, then
// don't always load from fetch_ptr, etc.
// cant use immediate as another because of Group3 where
// some have immediate and some don't, and those won't
// be picked up by logic until indirection.
// get attr and execute ptr at same time
// maybe move 16bit only i's like MOV_EwSw, MOV_SwEw
// to 32 bit modules.
// UD2 opcode (according to Intel manuals):
// Use the 0F0B opcode (UD2 instruction) or the 0FB9H opcode when deliberately
// trying to generate an invalid opcode exception (#UD).

61
bochs/cpu/fetchdecode64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode64.cc,v 1.60 2004-05-03 17:58:36 sshwarts Exp $
// $Id: fetchdecode64.cc,v 1.61 2004-09-06 20:22:39 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -53,39 +53,11 @@
///////////////////////////
// sign extended to osize:
// 6a push ib
// 6b imul gvevib
// 70..7f jo..jnle
// 83 G1 0..7 ADD..CMP Evib
// is 6b imul_gvevib sign extended? don't think
// I'm sign extending it properly in old decode/execute
// check all the groups. Make sure to add duplicates rather
// than error.
// mark instructions as changing control transfer, then
// don't always load from fetch_ptr, etc.
// cant use immediate as another because of Group3 where
// some have immediate and some don't, and those won't
// be picked up by logic until indirection.
// get attr and execute ptr at same time
// maybe move 16bit only i's like MOV_EwSw, MOV_SwEw
// to 32 bit modules.
// use 0F as a prefix too?
// UD2 opcode (according to Intel manuals):
// Use the 0F0B opcode (UD2 instruction) or the 0FB9H opcode when deliberately
// trying to generate an invalid opcode exception (#UD).
void BxResolveError(bxInstruction_c *);
static BxExecutePtr_tR BxResolve32Mod0[8] = {
@ -2228,25 +2200,14 @@ another_byte:
BX_INSTR_PREFIX_EXTEND8B(BX_CPU_ID);
instruction->assertExtend8bit();
//BX_DEBUG (("REX byte = %02x",b1));
if (b1 & 0x8) {
instruction->assertOs64();
instruction->assertOs32();
offset = 512*2;
//BX_DEBUG ((" 64bit")):
}
if (b1 & 0x4) {
rex_r = 8;
//BX_DEBUG((" reg+8"));
}
if (b1 & 0x2) {
rex_x = 8;
//BX_DEBUG((" index+8"));
}
if (b1 & 0x1) {
rex_b = 8;
//BX_DEBUG((" base+8"));
}
if (b1 & 0x4) rex_r = 8;
if (b1 & 0x2) rex_x = 8;
if (b1 & 0x1) rex_b = 8;
if (ilen < remain) {
ilen++;
goto fetch_b1;
@ -2362,9 +2323,7 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1));
instruction->metaInfo |= (1<<22); // (modC0)
goto modrm_done;
}
if (rm != 4) {
rm |= rex_b;
}
if (rm != 4) rm |= rex_b;
instruction->modRMForm.modRMData |= rm;
if (instruction->as64L()) {
// 64-bit addressing modes; note that mod==11b handled above
@ -2638,8 +2597,7 @@ modrm_done:
break;
case BxImmediate_Ib_SE: // Sign extend to OS size
if (ilen < remain) {
Bit8s temp8s;
temp8s = *iptr;
Bit8s temp8s = *iptr;
if (instruction->os32L())
instruction->modRMForm.Id = (Bit32s) temp8s;
else
@ -2716,9 +2674,7 @@ modrm_done:
iptr += 2;
ilen += 2;
}
else {
return(0);
}
else return(0);
if (imm_mode == BxImmediate_Iw) break;
if (ilen < remain) {
instruction->IxIxForm.Ib2 = *iptr;
@ -2730,8 +2686,7 @@ modrm_done:
break;
case BxImmediate_BrOff8:
if (ilen < remain) {
Bit8s temp8s;
temp8s = *iptr;
Bit8s temp8s = *iptr;
instruction->modRMForm.Id = temp8s;
ilen++;
}