Fix in BSWAP 64-bit mode - allow to use additional R8-R15 registers
Also fixed code duplication story with BSWAP instruction
This commit is contained in:
Stanislav Shwartsman
parent
d69eba6c07
commit
20b14aefa6
296
bochs/cpu/bit.cc
296
bochs/cpu/bit.cc
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: bit.cc,v 1.27 2006-03-26 18:58:00 sshwarts Exp $
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// $Id: bit.cc,v 1.28 2006-05-07 18:58:45 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -521,289 +521,43 @@ void BX_CPU_C::BSR_GqEq(bxInstruction_c *i)
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}
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#endif
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void BX_CPU_C::BSWAP_EAX(bxInstruction_c *i)
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void BX_CPU_C::BSWAP_ERX(bxInstruction_c *i)
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{
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#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
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Bit32u eax, b0, b1, b2, b3;
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Bit32u val32, b0, b1, b2, b3;
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eax = EAX;
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b0 = eax & 0xff; eax >>= 8;
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b1 = eax & 0xff; eax >>= 8;
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b2 = eax & 0xff; eax >>= 8;
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b3 = eax;
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val32 = BX_READ_32BIT_REG(i->opcodeReg());
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b0 = val32 & 0xff; val32 >>= 8;
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b1 = val32 & 0xff; val32 >>= 8;
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b2 = val32 & 0xff; val32 >>= 8;
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b3 = val32;
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val32 = (b0<<24) | (b1<<16) | (b2<<8) | b3; // zero extended
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RAX = (b0<<24) | (b1<<16) | (b2<<8) | b3; // zero extended
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// in 64-bit mode, hi-order 32 bits are not modified
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BX_WRITE_32BIT_REG(i->opcodeReg(), val32);
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#else
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BX_INFO(("BSWAP_EAX: not implemented CPU <= 3"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::BSWAP_ECX(bxInstruction_c *i)
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{
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#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
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Bit32u ecx, b0, b1, b2, b3;
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ecx = ECX;
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b0 = ecx & 0xff; ecx >>= 8;
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b1 = ecx & 0xff; ecx >>= 8;
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b2 = ecx & 0xff; ecx >>= 8;
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b3 = ecx;
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RCX = (b0<<24) | (b1<<16) | (b2<<8) | b3;
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#else
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BX_INFO(("BSWAP_ECX: not implemented CPU <= 3"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::BSWAP_EDX(bxInstruction_c *i)
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{
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#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
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Bit32u edx, b0, b1, b2, b3;
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edx = EDX;
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b0 = edx & 0xff; edx >>= 8;
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b1 = edx & 0xff; edx >>= 8;
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b2 = edx & 0xff; edx >>= 8;
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b3 = edx;
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RDX = (b0<<24) | (b1<<16) | (b2<<8) | b3;
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#else
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BX_INFO(("BSWAP_EDX: not implemented CPU <= 3"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::BSWAP_EBX(bxInstruction_c *i)
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{
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#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
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Bit32u ebx, b0, b1, b2, b3;
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ebx = EBX;
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b0 = ebx & 0xff; ebx >>= 8;
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b1 = ebx & 0xff; ebx >>= 8;
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b2 = ebx & 0xff; ebx >>= 8;
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b3 = ebx;
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RBX = (b0<<24) | (b1<<16) | (b2<<8) | b3;
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#else
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BX_INFO(("BSWAP_EBX: not implemented CPU <= 3"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::BSWAP_ESP(bxInstruction_c *i)
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{
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#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
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Bit32u esp, b0, b1, b2, b3;
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esp = ESP;
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b0 = esp & 0xff; esp >>= 8;
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b1 = esp & 0xff; esp >>= 8;
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b2 = esp & 0xff; esp >>= 8;
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b3 = esp;
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RSP = (b0<<24) | (b1<<16) | (b2<<8) | b3;
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#else
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BX_INFO(("BSWAP_ESP: not implemented CPU <= 3"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::BSWAP_EBP(bxInstruction_c *i)
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{
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#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
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Bit32u ebp, b0, b1, b2, b3;
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ebp = EBP;
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b0 = ebp & 0xff; ebp >>= 8;
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b1 = ebp & 0xff; ebp >>= 8;
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b2 = ebp & 0xff; ebp >>= 8;
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b3 = ebp;
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RBP = (b0<<24) | (b1<<16) | (b2<<8) | b3;
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#else
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BX_INFO(("BSWAP_EBP: not implemented CPU <= 3"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::BSWAP_ESI(bxInstruction_c *i)
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{
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#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
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Bit32u esi, b0, b1, b2, b3;
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esi = ESI;
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b0 = esi & 0xff; esi >>= 8;
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b1 = esi & 0xff; esi >>= 8;
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b2 = esi & 0xff; esi >>= 8;
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b3 = esi;
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RSI = (b0<<24) | (b1<<16) | (b2<<8) | b3;
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#else
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BX_INFO(("BSWAP_ESI: not implemented CPU <= 3"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::BSWAP_EDI(bxInstruction_c *i)
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{
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#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
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Bit32u edi, b0, b1, b2, b3;
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edi = EDI;
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b0 = edi & 0xff; edi >>= 8;
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b1 = edi & 0xff; edi >>= 8;
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b2 = edi & 0xff; edi >>= 8;
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b3 = edi;
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RDI = (b0<<24) | (b1<<16) | (b2<<8) | b3;
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#else
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BX_INFO(("BSWAP_EDI: not implemented CPU <= 3"));
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BX_INFO(("BSWAP_ERX: required CPU >= 4, use --enable-cpu-level=4 option"));
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UndefinedOpcode(i);
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#endif
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}
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#if BX_SUPPORT_X86_64
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void BX_CPU_C::BSWAP_RAX(bxInstruction_c *i)
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void BX_CPU_C::BSWAP_RRX(bxInstruction_c *i)
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{
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Bit64u rax, b0, b1, b2, b3, b4, b5, b6, b7;
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Bit64u val64, b0, b1, b2, b3, b4, b5, b6, b7;
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rax = RAX;
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b0 = rax & 0xff; rax >>= 8;
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b1 = rax & 0xff; rax >>= 8;
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b2 = rax & 0xff; rax >>= 8;
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b3 = rax & 0xff; rax >>= 8;
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b4 = rax & 0xff; rax >>= 8;
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b5 = rax & 0xff; rax >>= 8;
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b6 = rax & 0xff; rax >>= 8;
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b7 = rax;
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val64 = BX_READ_64BIT_REG(i->opcodeReg());
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b0 = val64 & 0xff; val64 >>= 8;
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b1 = val64 & 0xff; val64 >>= 8;
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b2 = val64 & 0xff; val64 >>= 8;
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b3 = val64 & 0xff; val64 >>= 8;
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b4 = val64 & 0xff; val64 >>= 8;
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b5 = val64 & 0xff; val64 >>= 8;
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b6 = val64 & 0xff; val64 >>= 8;
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b7 = val64;
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val64 = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b4<<16) | (b4<<8) | b7;
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RAX = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b4<<16) | (b4<<8) | b7;
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}
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void BX_CPU_C::BSWAP_RCX(bxInstruction_c *i)
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{
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Bit64u rcx, b0, b1, b2, b3, b4, b5, b6, b7;
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rcx = RCX;
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b0 = rcx & 0xff; rcx >>= 8;
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b1 = rcx & 0xff; rcx >>= 8;
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b2 = rcx & 0xff; rcx >>= 8;
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b3 = rcx & 0xff; rcx >>= 8;
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b4 = rcx & 0xff; rcx >>= 8;
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b5 = rcx & 0xff; rcx >>= 8;
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b6 = rcx & 0xff; rcx >>= 8;
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b7 = rcx;
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RCX = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
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}
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void BX_CPU_C::BSWAP_RDX(bxInstruction_c *i)
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{
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Bit64u rdx, b0, b1, b2, b3, b4, b5, b6, b7;
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rdx = RDX;
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b0 = rdx & 0xff; rdx >>= 8;
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b1 = rdx & 0xff; rdx >>= 8;
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b2 = rdx & 0xff; rdx >>= 8;
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b3 = rdx & 0xff; rdx >>= 8;
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b4 = rdx & 0xff; rdx >>= 8;
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b5 = rdx & 0xff; rdx >>= 8;
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b6 = rdx & 0xff; rdx >>= 8;
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b7 = rdx;
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RDX = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
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}
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void BX_CPU_C::BSWAP_RBX(bxInstruction_c *i)
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{
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Bit64u rbx, b0, b1, b2, b3, b4, b5, b6, b7;
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rbx = RBX;
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b0 = rbx & 0xff; rbx >>= 8;
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b1 = rbx & 0xff; rbx >>= 8;
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b2 = rbx & 0xff; rbx >>= 8;
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b3 = rbx & 0xff; rbx >>= 8;
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b4 = rbx & 0xff; rbx >>= 8;
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b5 = rbx & 0xff; rbx >>= 8;
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b6 = rbx & 0xff; rbx >>= 8;
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b7 = rbx;
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RBX = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
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}
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void BX_CPU_C::BSWAP_RSP(bxInstruction_c *i)
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{
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Bit64u rsp, b0, b1, b2, b3, b4, b5, b6, b7;
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rsp = RSP;
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b0 = rsp & 0xff; rsp >>= 8;
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b1 = rsp & 0xff; rsp >>= 8;
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b2 = rsp & 0xff; rsp >>= 8;
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b3 = rsp & 0xff; rsp >>= 8;
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b4 = rsp & 0xff; rsp >>= 8;
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b5 = rsp & 0xff; rsp >>= 8;
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b6 = rsp & 0xff; rsp >>= 8;
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b7 = rsp;
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RSP = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
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}
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void BX_CPU_C::BSWAP_RBP(bxInstruction_c *i)
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{
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Bit64u rbp, b0, b1, b2, b3, b4, b5, b6, b7;
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rbp = RBP;
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b0 = rbp & 0xff; rbp >>= 8;
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b1 = rbp & 0xff; rbp >>= 8;
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b2 = rbp & 0xff; rbp >>= 8;
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b3 = rbp & 0xff; rbp >>= 8;
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b4 = rbp & 0xff; rbp >>= 8;
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b5 = rbp & 0xff; rbp >>= 8;
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b6 = rbp & 0xff; rbp >>= 8;
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b7 = rbp;
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RBP = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
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}
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void BX_CPU_C::BSWAP_RSI(bxInstruction_c *i)
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{
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Bit64u rsi, b0, b1, b2, b3, b4, b5, b6, b7;
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rsi = RSI;
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b0 = rsi & 0xff; rsi >>= 8;
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b1 = rsi & 0xff; rsi >>= 8;
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b2 = rsi & 0xff; rsi >>= 8;
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b3 = rsi & 0xff; rsi >>= 8;
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b4 = rsi & 0xff; rsi >>= 8;
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b5 = rsi & 0xff; rsi >>= 8;
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b6 = rsi & 0xff; rsi >>= 8;
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b7 = rsi;
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RSI = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
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}
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void BX_CPU_C::BSWAP_RDI(bxInstruction_c *i)
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{
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Bit64u rdi, b0, b1, b2, b3, b4, b5, b6, b7;
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rdi = RDI;
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b0 = rdi & 0xff; rdi >>= 8;
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b1 = rdi & 0xff; rdi >>= 8;
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b2 = rdi & 0xff; rdi >>= 8;
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b3 = rdi & 0xff; rdi >>= 8;
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b4 = rdi & 0xff; rdi >>= 8;
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b5 = rdi & 0xff; rdi >>= 8;
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b6 = rdi & 0xff; rdi >>= 8;
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b7 = rdi;
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RDI = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7;
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BX_WRITE_64BIT_REG(i->opcodeReg(), val64);
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}
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#endif // #if BX_SUPPORT_X86_64
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.287 2006-05-07 18:27:35 sshwarts Exp $
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// $Id: cpu.h,v 1.288 2006-05-07 18:58:45 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1618,28 +1618,18 @@ public: // for now...
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BX_SMF void MOVSX_GwEb(bxInstruction_c *);
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BX_SMF void MOVSX_GdEw(bxInstruction_c *);
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BX_SMF void BSWAP_EAX(bxInstruction_c *);
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BX_SMF void BSWAP_ECX(bxInstruction_c *);
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BX_SMF void BSWAP_EDX(bxInstruction_c *);
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BX_SMF void BSWAP_EBX(bxInstruction_c *);
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BX_SMF void BSWAP_ESP(bxInstruction_c *);
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BX_SMF void BSWAP_EBP(bxInstruction_c *);
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BX_SMF void BSWAP_ESI(bxInstruction_c *);
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BX_SMF void BSWAP_EDI(bxInstruction_c *);
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BX_SMF void BSWAP_ERX(bxInstruction_c *);
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BX_SMF void ADD_EbIb(bxInstruction_c *);
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BX_SMF void ADC_EbIb(bxInstruction_c *);
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BX_SMF void SBB_EbIb(bxInstruction_c *);
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BX_SMF void SUB_EbIb(bxInstruction_c *);
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BX_SMF void CMP_EbIb(bxInstruction_c *);
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BX_SMF void XOR_EbIb(bxInstruction_c *);
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BX_SMF void OR_EbIb(bxInstruction_c *);
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BX_SMF void AND_EbIb(bxInstruction_c *);
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BX_SMF void ADD_EEdId(bxInstruction_c *);
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BX_SMF void ADD_EGdId(bxInstruction_c *);
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BX_SMF void OR_EdId(bxInstruction_c *);
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BX_SMF void OR_EwIw(bxInstruction_c *);
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BX_SMF void ADC_EdId(bxInstruction_c *);
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@ -2431,14 +2421,7 @@ public: // for now...
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BX_SMF void BTC_EqGq(bxInstruction_c *);
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BX_SMF void BTC_EqIb(bxInstruction_c *);
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BX_SMF void BSWAP_RAX(bxInstruction_c *);
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BX_SMF void BSWAP_RCX(bxInstruction_c *);
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BX_SMF void BSWAP_RDX(bxInstruction_c *);
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BX_SMF void BSWAP_RBX(bxInstruction_c *);
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BX_SMF void BSWAP_RSP(bxInstruction_c *);
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BX_SMF void BSWAP_RBP(bxInstruction_c *);
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BX_SMF void BSWAP_RSI(bxInstruction_c *);
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BX_SMF void BSWAP_RDI(bxInstruction_c *);
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BX_SMF void BSWAP_RRX(bxInstruction_c *);
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BX_SMF void ADD_EqId(bxInstruction_c *);
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BX_SMF void OR_EqId(bxInstruction_c *);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.93 2006-05-07 18:27:35 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.94 2006-05-07 18:58:46 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -902,14 +902,14 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
|
||||
/* 0F C5 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 },
|
||||
/* 0F C6 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 },
|
||||
/* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfoG9 },
|
||||
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_EAX },
|
||||
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ECX },
|
||||
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_EDX },
|
||||
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_EBX },
|
||||
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_ESP },
|
||||
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_EBP },
|
||||
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_ESI },
|
||||
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_EDI },
|
||||
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F D0 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd0 },
|
||||
/* 0F D1 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd1 },
|
||||
/* 0F D2 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd2 },
|
||||
@ -1460,14 +1460,14 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
|
||||
/* 0F C5 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 },
|
||||
/* 0F C6 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 },
|
||||
/* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfoG9 },
|
||||
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_EAX },
|
||||
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ECX },
|
||||
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_EDX },
|
||||
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_EBX },
|
||||
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_ESP },
|
||||
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_EBP },
|
||||
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_ESI },
|
||||
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_EDI },
|
||||
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F D0 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd0 },
|
||||
/* 0F D1 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd1 },
|
||||
/* 0F D2 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd2 },
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: fetchdecode64.cc,v 1.93 2006-05-07 18:27:36 sshwarts Exp $
|
||||
// $Id: fetchdecode64.cc,v 1.94 2006-05-07 18:58:47 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -1025,14 +1025,14 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* 0F C5 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 },
|
||||
/* 0F C6 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 },
|
||||
/* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfo64G9 },
|
||||
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_EAX },
|
||||
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ECX },
|
||||
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_EDX },
|
||||
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_EBX },
|
||||
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_ESP },
|
||||
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_EBP },
|
||||
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_ESI },
|
||||
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_EDI },
|
||||
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F D0 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd0 },
|
||||
/* 0F D1 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd1 },
|
||||
/* 0F D2 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd2 },
|
||||
@ -1554,14 +1554,14 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* 0F C5 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 },
|
||||
/* 0F C6 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 },
|
||||
/* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfo64G9 },
|
||||
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_EAX },
|
||||
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ECX },
|
||||
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_EDX },
|
||||
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_EBX },
|
||||
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_ESP },
|
||||
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_EBP },
|
||||
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_ESI },
|
||||
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_EDI },
|
||||
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_ERX },
|
||||
/* 0F D0 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd0 },
|
||||
/* 0F D1 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd1 },
|
||||
/* 0F D2 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd2 },
|
||||
@ -2083,14 +2083,14 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* 0F C5 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 },
|
||||
/* 0F C6 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 },
|
||||
/* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfo64G9q },
|
||||
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_RAX },
|
||||
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_RCX },
|
||||
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_RDX },
|
||||
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_RBX },
|
||||
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_RSP },
|
||||
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_RBP },
|
||||
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_RSI },
|
||||
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_RDI },
|
||||
/* 0F C8 */ { 0, &BX_CPU_C::BSWAP_RRX },
|
||||
/* 0F C9 */ { 0, &BX_CPU_C::BSWAP_RRX },
|
||||
/* 0F CA */ { 0, &BX_CPU_C::BSWAP_RRX },
|
||||
/* 0F CB */ { 0, &BX_CPU_C::BSWAP_RRX },
|
||||
/* 0F CC */ { 0, &BX_CPU_C::BSWAP_RRX },
|
||||
/* 0F CD */ { 0, &BX_CPU_C::BSWAP_RRX },
|
||||
/* 0F CE */ { 0, &BX_CPU_C::BSWAP_RRX },
|
||||
/* 0F CF */ { 0, &BX_CPU_C::BSWAP_RRX },
|
||||
/* 0F D0 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd0 },
|
||||
/* 0F D1 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd1 },
|
||||
/* 0F D2 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd2 },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user