From 20b14aefa69e0b6ea3c4a764f3945c2f61dc6d91 Mon Sep 17 00:00:00 2001 From: Stanislav Shwartsman Date: Sun, 7 May 2006 18:58:47 +0000 Subject: [PATCH] Fix in BSWAP 64-bit mode - allow to use additional R8-R15 registers Also fixed code duplication story with BSWAP instruction --- bochs/cpu/bit.cc | 296 ++++--------------------------------- bochs/cpu/cpu.h | 23 +-- bochs/cpu/fetchdecode.cc | 34 ++--- bochs/cpu/fetchdecode64.cc | 50 +++---- 4 files changed, 70 insertions(+), 333 deletions(-) diff --git a/bochs/cpu/bit.cc b/bochs/cpu/bit.cc index 3a9125275..62a5f6462 100644 --- a/bochs/cpu/bit.cc +++ b/bochs/cpu/bit.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: bit.cc,v 1.27 2006-03-26 18:58:00 sshwarts Exp $ +// $Id: bit.cc,v 1.28 2006-05-07 18:58:45 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -521,289 +521,43 @@ void BX_CPU_C::BSR_GqEq(bxInstruction_c *i) } #endif -void BX_CPU_C::BSWAP_EAX(bxInstruction_c *i) +void BX_CPU_C::BSWAP_ERX(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) - Bit32u eax, b0, b1, b2, b3; + Bit32u val32, b0, b1, b2, b3; - eax = EAX; - b0 = eax & 0xff; eax >>= 8; - b1 = eax & 0xff; eax >>= 8; - b2 = eax & 0xff; eax >>= 8; - b3 = eax; + val32 = BX_READ_32BIT_REG(i->opcodeReg()); + b0 = val32 & 0xff; val32 >>= 8; + b1 = val32 & 0xff; val32 >>= 8; + b2 = val32 & 0xff; val32 >>= 8; + b3 = val32; + val32 = (b0<<24) | (b1<<16) | (b2<<8) | b3; // zero extended - RAX = (b0<<24) | (b1<<16) | (b2<<8) | b3; // zero extended + // in 64-bit mode, hi-order 32 bits are not modified + BX_WRITE_32BIT_REG(i->opcodeReg(), val32); #else - BX_INFO(("BSWAP_EAX: not implemented CPU <= 3")); - UndefinedOpcode(i); -#endif -} - -void BX_CPU_C::BSWAP_ECX(bxInstruction_c *i) -{ -#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) - Bit32u ecx, b0, b1, b2, b3; - - ecx = ECX; - b0 = ecx & 0xff; ecx >>= 8; - b1 = ecx & 0xff; ecx >>= 8; - b2 = ecx & 0xff; ecx >>= 8; - b3 = ecx; - - RCX = (b0<<24) | (b1<<16) | (b2<<8) | b3; -#else - BX_INFO(("BSWAP_ECX: not implemented CPU <= 3")); - UndefinedOpcode(i); -#endif -} - -void BX_CPU_C::BSWAP_EDX(bxInstruction_c *i) -{ -#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) - Bit32u edx, b0, b1, b2, b3; - - edx = EDX; - b0 = edx & 0xff; edx >>= 8; - b1 = edx & 0xff; edx >>= 8; - b2 = edx & 0xff; edx >>= 8; - b3 = edx; - - RDX = (b0<<24) | (b1<<16) | (b2<<8) | b3; -#else - BX_INFO(("BSWAP_EDX: not implemented CPU <= 3")); - UndefinedOpcode(i); -#endif -} - -void BX_CPU_C::BSWAP_EBX(bxInstruction_c *i) -{ -#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) - Bit32u ebx, b0, b1, b2, b3; - - ebx = EBX; - b0 = ebx & 0xff; ebx >>= 8; - b1 = ebx & 0xff; ebx >>= 8; - b2 = ebx & 0xff; ebx >>= 8; - b3 = ebx; - - RBX = (b0<<24) | (b1<<16) | (b2<<8) | b3; -#else - BX_INFO(("BSWAP_EBX: not implemented CPU <= 3")); - UndefinedOpcode(i); -#endif -} - -void BX_CPU_C::BSWAP_ESP(bxInstruction_c *i) -{ -#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) - - Bit32u esp, b0, b1, b2, b3; - - esp = ESP; - b0 = esp & 0xff; esp >>= 8; - b1 = esp & 0xff; esp >>= 8; - b2 = esp & 0xff; esp >>= 8; - b3 = esp; - - RSP = (b0<<24) | (b1<<16) | (b2<<8) | b3; -#else - BX_INFO(("BSWAP_ESP: not implemented CPU <= 3")); - UndefinedOpcode(i); -#endif -} - -void BX_CPU_C::BSWAP_EBP(bxInstruction_c *i) -{ -#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) - - Bit32u ebp, b0, b1, b2, b3; - - ebp = EBP; - b0 = ebp & 0xff; ebp >>= 8; - b1 = ebp & 0xff; ebp >>= 8; - b2 = ebp & 0xff; ebp >>= 8; - b3 = ebp; - - RBP = (b0<<24) | (b1<<16) | (b2<<8) | b3; -#else - BX_INFO(("BSWAP_EBP: not implemented CPU <= 3")); - UndefinedOpcode(i); -#endif -} - -void BX_CPU_C::BSWAP_ESI(bxInstruction_c *i) -{ -#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) - - Bit32u esi, b0, b1, b2, b3; - - esi = ESI; - b0 = esi & 0xff; esi >>= 8; - b1 = esi & 0xff; esi >>= 8; - b2 = esi & 0xff; esi >>= 8; - b3 = esi; - - RSI = (b0<<24) | (b1<<16) | (b2<<8) | b3; -#else - BX_INFO(("BSWAP_ESI: not implemented CPU <= 3")); - UndefinedOpcode(i); -#endif -} - -void BX_CPU_C::BSWAP_EDI(bxInstruction_c *i) -{ -#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) - - Bit32u edi, b0, b1, b2, b3; - - edi = EDI; - b0 = edi & 0xff; edi >>= 8; - b1 = edi & 0xff; edi >>= 8; - b2 = edi & 0xff; edi >>= 8; - b3 = edi; - - RDI = (b0<<24) | (b1<<16) | (b2<<8) | b3; -#else - BX_INFO(("BSWAP_EDI: not implemented CPU <= 3")); + BX_INFO(("BSWAP_ERX: required CPU >= 4, use --enable-cpu-level=4 option")); UndefinedOpcode(i); #endif } #if BX_SUPPORT_X86_64 -void BX_CPU_C::BSWAP_RAX(bxInstruction_c *i) +void BX_CPU_C::BSWAP_RRX(bxInstruction_c *i) { - Bit64u rax, b0, b1, b2, b3, b4, b5, b6, b7; + Bit64u val64, b0, b1, b2, b3, b4, b5, b6, b7; - rax = RAX; - b0 = rax & 0xff; rax >>= 8; - b1 = rax & 0xff; rax >>= 8; - b2 = rax & 0xff; rax >>= 8; - b3 = rax & 0xff; rax >>= 8; - b4 = rax & 0xff; rax >>= 8; - b5 = rax & 0xff; rax >>= 8; - b6 = rax & 0xff; rax >>= 8; - b7 = rax; + val64 = BX_READ_64BIT_REG(i->opcodeReg()); + b0 = val64 & 0xff; val64 >>= 8; + b1 = val64 & 0xff; val64 >>= 8; + b2 = val64 & 0xff; val64 >>= 8; + b3 = val64 & 0xff; val64 >>= 8; + b4 = val64 & 0xff; val64 >>= 8; + b5 = val64 & 0xff; val64 >>= 8; + b6 = val64 & 0xff; val64 >>= 8; + b7 = val64; + val64 = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b4<<16) | (b4<<8) | b7; - RAX = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b4<<16) | (b4<<8) | b7; -} - -void BX_CPU_C::BSWAP_RCX(bxInstruction_c *i) -{ - Bit64u rcx, b0, b1, b2, b3, b4, b5, b6, b7; - - rcx = RCX; - b0 = rcx & 0xff; rcx >>= 8; - b1 = rcx & 0xff; rcx >>= 8; - b2 = rcx & 0xff; rcx >>= 8; - b3 = rcx & 0xff; rcx >>= 8; - b4 = rcx & 0xff; rcx >>= 8; - b5 = rcx & 0xff; rcx >>= 8; - b6 = rcx & 0xff; rcx >>= 8; - b7 = rcx; - - RCX = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7; -} - -void BX_CPU_C::BSWAP_RDX(bxInstruction_c *i) -{ - Bit64u rdx, b0, b1, b2, b3, b4, b5, b6, b7; - - rdx = RDX; - b0 = rdx & 0xff; rdx >>= 8; - b1 = rdx & 0xff; rdx >>= 8; - b2 = rdx & 0xff; rdx >>= 8; - b3 = rdx & 0xff; rdx >>= 8; - b4 = rdx & 0xff; rdx >>= 8; - b5 = rdx & 0xff; rdx >>= 8; - b6 = rdx & 0xff; rdx >>= 8; - b7 = rdx; - - RDX = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7; -} - -void BX_CPU_C::BSWAP_RBX(bxInstruction_c *i) -{ - Bit64u rbx, b0, b1, b2, b3, b4, b5, b6, b7; - - rbx = RBX; - b0 = rbx & 0xff; rbx >>= 8; - b1 = rbx & 0xff; rbx >>= 8; - b2 = rbx & 0xff; rbx >>= 8; - b3 = rbx & 0xff; rbx >>= 8; - b4 = rbx & 0xff; rbx >>= 8; - b5 = rbx & 0xff; rbx >>= 8; - b6 = rbx & 0xff; rbx >>= 8; - b7 = rbx; - - RBX = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7; -} - -void BX_CPU_C::BSWAP_RSP(bxInstruction_c *i) -{ - Bit64u rsp, b0, b1, b2, b3, b4, b5, b6, b7; - - rsp = RSP; - b0 = rsp & 0xff; rsp >>= 8; - b1 = rsp & 0xff; rsp >>= 8; - b2 = rsp & 0xff; rsp >>= 8; - b3 = rsp & 0xff; rsp >>= 8; - b4 = rsp & 0xff; rsp >>= 8; - b5 = rsp & 0xff; rsp >>= 8; - b6 = rsp & 0xff; rsp >>= 8; - b7 = rsp; - - RSP = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7; -} - -void BX_CPU_C::BSWAP_RBP(bxInstruction_c *i) -{ - Bit64u rbp, b0, b1, b2, b3, b4, b5, b6, b7; - - rbp = RBP; - b0 = rbp & 0xff; rbp >>= 8; - b1 = rbp & 0xff; rbp >>= 8; - b2 = rbp & 0xff; rbp >>= 8; - b3 = rbp & 0xff; rbp >>= 8; - b4 = rbp & 0xff; rbp >>= 8; - b5 = rbp & 0xff; rbp >>= 8; - b6 = rbp & 0xff; rbp >>= 8; - b7 = rbp; - - RBP = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7; -} - -void BX_CPU_C::BSWAP_RSI(bxInstruction_c *i) -{ - Bit64u rsi, b0, b1, b2, b3, b4, b5, b6, b7; - - rsi = RSI; - b0 = rsi & 0xff; rsi >>= 8; - b1 = rsi & 0xff; rsi >>= 8; - b2 = rsi & 0xff; rsi >>= 8; - b3 = rsi & 0xff; rsi >>= 8; - b4 = rsi & 0xff; rsi >>= 8; - b5 = rsi & 0xff; rsi >>= 8; - b6 = rsi & 0xff; rsi >>= 8; - b7 = rsi; - - RSI = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7; -} - -void BX_CPU_C::BSWAP_RDI(bxInstruction_c *i) -{ - Bit64u rdi, b0, b1, b2, b3, b4, b5, b6, b7; - - rdi = RDI; - b0 = rdi & 0xff; rdi >>= 8; - b1 = rdi & 0xff; rdi >>= 8; - b2 = rdi & 0xff; rdi >>= 8; - b3 = rdi & 0xff; rdi >>= 8; - b4 = rdi & 0xff; rdi >>= 8; - b5 = rdi & 0xff; rdi >>= 8; - b6 = rdi & 0xff; rdi >>= 8; - b7 = rdi; - - RDI = (b0<<56) | (b1<<48) | (b2<<40) | (b3<<32) | (b4<<24) | (b5<<16) | (b6<<8) | b7; + BX_WRITE_64BIT_REG(i->opcodeReg(), val64); } #endif // #if BX_SUPPORT_X86_64 diff --git a/bochs/cpu/cpu.h b/bochs/cpu/cpu.h index 5aab9c616..8474cbbbc 100644 --- a/bochs/cpu/cpu.h +++ b/bochs/cpu/cpu.h @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: cpu.h,v 1.287 2006-05-07 18:27:35 sshwarts Exp $ +// $Id: cpu.h,v 1.288 2006-05-07 18:58:45 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -1618,28 +1618,18 @@ public: // for now... BX_SMF void MOVSX_GwEb(bxInstruction_c *); BX_SMF void MOVSX_GdEw(bxInstruction_c *); - BX_SMF void BSWAP_EAX(bxInstruction_c *); - BX_SMF void BSWAP_ECX(bxInstruction_c *); - BX_SMF void BSWAP_EDX(bxInstruction_c *); - BX_SMF void BSWAP_EBX(bxInstruction_c *); - BX_SMF void BSWAP_ESP(bxInstruction_c *); - BX_SMF void BSWAP_EBP(bxInstruction_c *); - BX_SMF void BSWAP_ESI(bxInstruction_c *); - BX_SMF void BSWAP_EDI(bxInstruction_c *); + BX_SMF void BSWAP_ERX(bxInstruction_c *); BX_SMF void ADD_EbIb(bxInstruction_c *); BX_SMF void ADC_EbIb(bxInstruction_c *); BX_SMF void SBB_EbIb(bxInstruction_c *); BX_SMF void SUB_EbIb(bxInstruction_c *); BX_SMF void CMP_EbIb(bxInstruction_c *); - BX_SMF void XOR_EbIb(bxInstruction_c *); BX_SMF void OR_EbIb(bxInstruction_c *); BX_SMF void AND_EbIb(bxInstruction_c *); - BX_SMF void ADD_EEdId(bxInstruction_c *); BX_SMF void ADD_EGdId(bxInstruction_c *); - BX_SMF void OR_EdId(bxInstruction_c *); BX_SMF void OR_EwIw(bxInstruction_c *); BX_SMF void ADC_EdId(bxInstruction_c *); @@ -2431,14 +2421,7 @@ public: // for now... BX_SMF void BTC_EqGq(bxInstruction_c *); BX_SMF void BTC_EqIb(bxInstruction_c *); - BX_SMF void BSWAP_RAX(bxInstruction_c *); - BX_SMF void BSWAP_RCX(bxInstruction_c *); - BX_SMF void BSWAP_RDX(bxInstruction_c *); - BX_SMF void BSWAP_RBX(bxInstruction_c *); - BX_SMF void BSWAP_RSP(bxInstruction_c *); - BX_SMF void BSWAP_RBP(bxInstruction_c *); - BX_SMF void BSWAP_RSI(bxInstruction_c *); - BX_SMF void BSWAP_RDI(bxInstruction_c *); + BX_SMF void BSWAP_RRX(bxInstruction_c *); BX_SMF void ADD_EqId(bxInstruction_c *); BX_SMF void OR_EqId(bxInstruction_c *); diff --git a/bochs/cpu/fetchdecode.cc b/bochs/cpu/fetchdecode.cc index 7dcd6e171..5e78d2862 100644 --- a/bochs/cpu/fetchdecode.cc +++ b/bochs/cpu/fetchdecode.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: fetchdecode.cc,v 1.93 2006-05-07 18:27:35 sshwarts Exp $ +// $Id: fetchdecode.cc,v 1.94 2006-05-07 18:58:46 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -902,14 +902,14 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = { /* 0F C5 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 }, /* 0F C6 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 }, /* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfoG9 }, - /* 0F C8 */ { 0, &BX_CPU_C::BSWAP_EAX }, - /* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ECX }, - /* 0F CA */ { 0, &BX_CPU_C::BSWAP_EDX }, - /* 0F CB */ { 0, &BX_CPU_C::BSWAP_EBX }, - /* 0F CC */ { 0, &BX_CPU_C::BSWAP_ESP }, - /* 0F CD */ { 0, &BX_CPU_C::BSWAP_EBP }, - /* 0F CE */ { 0, &BX_CPU_C::BSWAP_ESI }, - /* 0F CF */ { 0, &BX_CPU_C::BSWAP_EDI }, + /* 0F C8 */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CA */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CB */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CC */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CD */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CE */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CF */ { 0, &BX_CPU_C::BSWAP_ERX }, /* 0F D0 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd0 }, /* 0F D1 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd1 }, /* 0F D2 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd2 }, @@ -1460,14 +1460,14 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = { /* 0F C5 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 }, /* 0F C6 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 }, /* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfoG9 }, - /* 0F C8 */ { 0, &BX_CPU_C::BSWAP_EAX }, - /* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ECX }, - /* 0F CA */ { 0, &BX_CPU_C::BSWAP_EDX }, - /* 0F CB */ { 0, &BX_CPU_C::BSWAP_EBX }, - /* 0F CC */ { 0, &BX_CPU_C::BSWAP_ESP }, - /* 0F CD */ { 0, &BX_CPU_C::BSWAP_EBP }, - /* 0F CE */ { 0, &BX_CPU_C::BSWAP_ESI }, - /* 0F CF */ { 0, &BX_CPU_C::BSWAP_EDI }, + /* 0F C8 */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CA */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CB */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CC */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CD */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CE */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CF */ { 0, &BX_CPU_C::BSWAP_ERX }, /* 0F D0 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd0 }, /* 0F D1 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd1 }, /* 0F D2 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd2 }, diff --git a/bochs/cpu/fetchdecode64.cc b/bochs/cpu/fetchdecode64.cc index 9f69a23d0..76c7bbbbb 100644 --- a/bochs/cpu/fetchdecode64.cc +++ b/bochs/cpu/fetchdecode64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: fetchdecode64.cc,v 1.93 2006-05-07 18:27:36 sshwarts Exp $ +// $Id: fetchdecode64.cc,v 1.94 2006-05-07 18:58:47 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -1025,14 +1025,14 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = { /* 0F C5 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 }, /* 0F C6 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 }, /* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfo64G9 }, - /* 0F C8 */ { 0, &BX_CPU_C::BSWAP_EAX }, - /* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ECX }, - /* 0F CA */ { 0, &BX_CPU_C::BSWAP_EDX }, - /* 0F CB */ { 0, &BX_CPU_C::BSWAP_EBX }, - /* 0F CC */ { 0, &BX_CPU_C::BSWAP_ESP }, - /* 0F CD */ { 0, &BX_CPU_C::BSWAP_EBP }, - /* 0F CE */ { 0, &BX_CPU_C::BSWAP_ESI }, - /* 0F CF */ { 0, &BX_CPU_C::BSWAP_EDI }, + /* 0F C8 */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CA */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CB */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CC */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CD */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CE */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CF */ { 0, &BX_CPU_C::BSWAP_ERX }, /* 0F D0 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd0 }, /* 0F D1 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd1 }, /* 0F D2 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd2 }, @@ -1554,14 +1554,14 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = { /* 0F C5 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 }, /* 0F C6 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 }, /* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfo64G9 }, - /* 0F C8 */ { 0, &BX_CPU_C::BSWAP_EAX }, - /* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ECX }, - /* 0F CA */ { 0, &BX_CPU_C::BSWAP_EDX }, - /* 0F CB */ { 0, &BX_CPU_C::BSWAP_EBX }, - /* 0F CC */ { 0, &BX_CPU_C::BSWAP_ESP }, - /* 0F CD */ { 0, &BX_CPU_C::BSWAP_EBP }, - /* 0F CE */ { 0, &BX_CPU_C::BSWAP_ESI }, - /* 0F CF */ { 0, &BX_CPU_C::BSWAP_EDI }, + /* 0F C8 */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F C9 */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CA */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CB */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CC */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CD */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CE */ { 0, &BX_CPU_C::BSWAP_ERX }, + /* 0F CF */ { 0, &BX_CPU_C::BSWAP_ERX }, /* 0F D0 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd0 }, /* 0F D1 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd1 }, /* 0F D2 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd2 }, @@ -2083,14 +2083,14 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = { /* 0F C5 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc5 }, /* 0F C6 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fc6 }, /* 0F C7 */ { BxAnother | BxGroup9, NULL, BxOpcodeInfo64G9q }, - /* 0F C8 */ { 0, &BX_CPU_C::BSWAP_RAX }, - /* 0F C9 */ { 0, &BX_CPU_C::BSWAP_RCX }, - /* 0F CA */ { 0, &BX_CPU_C::BSWAP_RDX }, - /* 0F CB */ { 0, &BX_CPU_C::BSWAP_RBX }, - /* 0F CC */ { 0, &BX_CPU_C::BSWAP_RSP }, - /* 0F CD */ { 0, &BX_CPU_C::BSWAP_RBP }, - /* 0F CE */ { 0, &BX_CPU_C::BSWAP_RSI }, - /* 0F CF */ { 0, &BX_CPU_C::BSWAP_RDI }, + /* 0F C8 */ { 0, &BX_CPU_C::BSWAP_RRX }, + /* 0F C9 */ { 0, &BX_CPU_C::BSWAP_RRX }, + /* 0F CA */ { 0, &BX_CPU_C::BSWAP_RRX }, + /* 0F CB */ { 0, &BX_CPU_C::BSWAP_RRX }, + /* 0F CC */ { 0, &BX_CPU_C::BSWAP_RRX }, + /* 0F CD */ { 0, &BX_CPU_C::BSWAP_RRX }, + /* 0F CE */ { 0, &BX_CPU_C::BSWAP_RRX }, + /* 0F CF */ { 0, &BX_CPU_C::BSWAP_RRX }, /* 0F D0 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd0 }, /* 0F D1 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd1 }, /* 0F D2 */ { BxAnother | BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fd2 },