Preliminary implemntation of SMM save statei
Fixed fetchModeMask for load32bitOsStack
This commit is contained in:
Stanislav Shwartsman
parent
c7d142200f
commit
da3d26d7f4
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: arith32.cc,v 1.48 2006-03-26 18:58:00 sshwarts Exp $
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// $Id: arith32.cc,v 1.49 2006-03-27 18:02:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -440,13 +440,13 @@ void BX_CPU_C::CDQ(bxInstruction_c *i)
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void BX_CPU_C::CMPXCHG_XBTS(bxInstruction_c *i)
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{
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BX_INFO(("CMPXCHG_XBTS:"));
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BX_INFO(("CMPXCHG_XBTS: Generate #UD exception"));
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UndefinedOpcode(i);
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}
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void BX_CPU_C::CMPXCHG_IBTS(bxInstruction_c *i)
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{
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BX_INFO(("CMPXCHG_IBTS:"));
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BX_INFO(("CMPXCHG_IBTS: Generate #UD exception"));
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UndefinedOpcode(i);
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.272 2006-03-26 18:58:00 sshwarts Exp $
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// $Id: cpu.h,v 1.273 2006-03-27 18:02:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1233,9 +1233,9 @@ public: // for now...
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#if BX_SUPPORT_ICACHE
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bxICache_c iCache BX_CPP_AlignN(32);
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Bit32u fetchModeMask;
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Bit32u updateFetchModeMask(void);
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#endif
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struct {
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bx_address rm_addr; // The address offset after resolution.
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Bit32u paddress1; // physical address after translation of 1st len1 bytes of data
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@ -2742,6 +2742,8 @@ public: // for now...
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BX_CPP_AttrNoReturn();
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#endif
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BX_SMF bx_bool smram_write(bx_phy_address a20addr);
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BX_SMF void smram_save_state(void);
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BX_SMF bx_bool smram_restore_state(void);
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BX_SMF int int_number(bx_segment_reg_t *seg);
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BX_SMF void CR3_change(bx_address value) BX_CPP_AttrRegparmN(1);
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BX_SMF void pagingCR0Changed(Bit32u oldCR0, Bit32u newCR0) BX_CPP_AttrRegparmN(2);
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@ -2927,18 +2929,18 @@ public: // for now...
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BX_SMF void SetCR0(Bit32u val_32);
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#if BX_CPU_LEVEL >= 4
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BX_SMF void SetCR4(Bit32u val_32);
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BX_SMF bx_bool SetCR4(Bit32u val_32);
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#endif
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};
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#if BX_SUPPORT_ICACHE
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BX_CPP_INLINE Bit32u createFetchModeMask(BX_CPU_C *cpu)
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BX_CPP_INLINE Bit32u BX_CPU_C::updateFetchModeMask(void)
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{
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return (cpu->sregs[BX_SEG_REG_CS].cache.u.segment.d_b << 31)
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return (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b << 31)
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#if BX_SUPPORT_X86_64
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| ((cpu->cpu_mode == BX_MODE_LONG_64)<<30)
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| ((BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)<<30)
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#endif
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| (1<<29); // iCache code.
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}
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@ -1,5 +1,5 @@
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////////////////////////////////////////////////////////////////////////
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// $Id: ctrl_xfer_pro.cc,v 1.52 2006-03-06 22:02:52 sshwarts Exp $
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// $Id: ctrl_xfer_pro.cc,v 1.53 2006-03-27 18:02:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -118,7 +118,7 @@ BX_CPU_C::load_cs(bx_selector_t *selector, bx_descriptor_t *descriptor, Bit8u cp
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#endif
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#if BX_SUPPORT_ICACHE
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BX_CPU_THIS_PTR fetchModeMask = createFetchModeMask(BX_CPU_THIS);
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BX_CPU_THIS_PTR updateFetchModeMask();
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#endif
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// Loading CS will invalidate the EIP fetch window.
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: debugstuff.cc,v 1.60 2006-03-06 22:02:53 sshwarts Exp $
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// $Id: debugstuff.cc,v 1.61 2006-03-27 18:02:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -719,7 +719,7 @@ bx_bool BX_CPU_C::dbg_set_cpu(bx_dbg_cpu_t *cpu)
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit;
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#if BX_SUPPORT_ICACHE
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BX_CPU_THIS_PTR fetchModeMask = createFetchModeMask(BX_CPU_THIS);
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BX_CPU_THIS_PTR updateFetchModeMask();
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#endif
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// SS:
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: init.cc,v 1.94 2006-03-16 20:24:09 sshwarts Exp $
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// $Id: init.cc,v 1.95 2006-03-27 18:02:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -511,7 +511,7 @@ void BX_CPU_C::reset(unsigned source)
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#endif
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#if BX_SUPPORT_ICACHE
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BX_CPU_THIS_PTR fetchModeMask = createFetchModeMask(BX_CPU_THIS);
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BX_CPU_THIS_PTR updateFetchModeMask();
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#endif
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/* DS (Data Segment) and descriptor cache */
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.142 2006-03-22 20:47:11 sshwarts Exp $
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// $Id: proc_ctrl.cc,v 1.143 2006-03-27 18:02:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -591,10 +591,6 @@ void BX_CPU_C::MOV_CdRd(bxInstruction_c *i)
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switch (i->nnn()) {
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case 0: // CR0 (MSW)
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// BX_INFO(("MOV_CdRd:CR0: R32 = %08x @CS:EIP %04x:%04x ",
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// (unsigned) val_32,
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// (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
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// (unsigned) EIP));
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SetCR0(val_32);
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break;
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@ -616,9 +612,10 @@ void BX_CPU_C::MOV_CdRd(bxInstruction_c *i)
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BX_PANIC(("MOV_CdRd: write to CR4 of 0x%08x on 386", val_32));
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UndefinedOpcode(i);
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#else
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// Protected mode: #GP(0) if attempt to write a 1 to
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// any reserved bit of CR4
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SetCR4(val_32);
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// Protected mode: #GP(0) if attempt to write a 1 to
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// any reserved bit of CR4
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if (! SetCR4(val_32))
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exception(BX_GP_EXCEPTION, 0, 0);
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#endif
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break;
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default:
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@ -724,10 +721,6 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
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switch (i->nnn()) {
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case 0: // CR0 (MSW)
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// BX_INFO(("MOV_CqRq:CR0: R64 = %08x @CS:EIP %04x:%04x ",
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// (unsigned) val_64,
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// (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
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// (unsigned) EIP));
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SetCR0(val_64);
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break;
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case 1: /* CR1 */
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@ -748,7 +741,8 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
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// any reserved bit of CR4
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BX_DEBUG(("MOV_CqRq: write to CR4 of %08x:%08x",
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(Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF)));
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SetCR4(val_64);
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if (! SetCR4(val_64))
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exception(BX_GP_EXCEPTION, 0, 0);
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break;
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#if BX_SUPPORT_APIC
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case 8: // CR8
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@ -1142,7 +1136,7 @@ void BX_CPU_C::LOADALL(bxInstruction_c *i)
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}
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#if BX_SUPPORT_ICACHE
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BX_CPU_THIS_PTR fetchModeMask = createFetchModeMask(BX_CPU_THIS);
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BX_CPU_THIS_PTR updateFetchModeMask();
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#endif
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/* ES */
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@ -1327,9 +1321,6 @@ void BX_CPU_C::SetCR0(Bit32u val_32)
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BX_CPU_THIS_PTR msr.lma = 1;
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BX_DEBUG(("Enter Compatibility Mode"));
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BX_CPU_THIS_PTR cpu_mode = BX_MODE_LONG_COMPAT;
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//#if BX_EXTERNAL_DEBUGGER
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//trap_debugger(0);
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//#endif
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}
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}
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else if (prev_pg==1 && BX_CPU_THIS_PTR cr0.pg==0) {
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@ -1346,9 +1337,6 @@ void BX_CPU_C::SetCR0(Bit32u val_32)
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BX_DEBUG(("Enter Real Mode"));
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BX_CPU_THIS_PTR cpu_mode = BX_MODE_IA32_REAL;
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}
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//#if BX_EXTERNAL_DEBUGGER
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//trap_debugger(0);
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//#endif
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}
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}
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#endif // #if BX_SUPPORT_X86_64
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@ -1359,7 +1347,7 @@ void BX_CPU_C::SetCR0(Bit32u val_32)
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}
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#if BX_CPU_LEVEL >= 4
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void BX_CPU_C::SetCR4(Bit32u val_32)
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bx_bool BX_CPU_C::SetCR4(Bit32u val_32)
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{
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Bit32u oldCR4 = BX_CPU_THIS_PTR cr4.getRegister();
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Bit32u allowMask = 0;
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@ -1415,24 +1403,25 @@ void BX_CPU_C::SetCR4(Bit32u val_32)
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#endif
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#if BX_SUPPORT_X86_64
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// need to GPF #0 if LME=1 and PAE=0
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// need to GPF #0 if LME=1 and PAE=0
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if ((BX_CPU_THIS_PTR msr.lme)
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&& (!(val_32 >> 5) & 1)
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&& (BX_CPU_THIS_PTR cr4.get_PAE()))
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{
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exception(BX_GP_EXCEPTION, 0, 0);
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return 0;
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}
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#endif
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// Need to GPF if trying to set undefined bits.
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if (val_32 & ~allowMask) {
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BX_INFO(("#GP(0): SetCR4: Write of 0x%08x not supported (allowMask=0x%x)",
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val_32, allowMask));
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exception(BX_GP_EXCEPTION, 0, 0);
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BX_INFO(("#GP(0): SetCR4: Write of 0x%08x not supported (allowMask=0x%x)", val_32, allowMask));
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return 0;
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}
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val_32 &= allowMask; // Screen out unsupported bits. (not needed, for good measure)
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BX_CPU_THIS_PTR cr4.setRegister(val_32);
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pagingCR4Changed(oldCR4, BX_CPU_THIS_PTR cr4.getRegister());
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return 1;
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}
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#endif
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@ -1856,7 +1845,7 @@ void BX_CPU_C::SYSENTER (bxInstruction_c *i)
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; // available for use by system
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#if BX_SUPPORT_ICACHE
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BX_CPU_THIS_PTR fetchModeMask = createFetchModeMask(BX_CPU_THIS);
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BX_CPU_THIS_PTR updateFetchModeMask();
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#endif
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value = (BX_CPU_THIS_PTR msr.sysenter_cs_msr + 8) & BX_SELECTOR_RPL_MASK;
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@ -1916,7 +1905,7 @@ void BX_CPU_C::SYSEXIT (bxInstruction_c *i)
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; // available for use by system
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#if BX_SUPPORT_ICACHE
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BX_CPU_THIS_PTR fetchModeMask = createFetchModeMask(BX_CPU_THIS);
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BX_CPU_THIS_PTR updateFetchModeMask();
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#endif
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value = (BX_CPU_THIS_PTR msr.sysenter_cs_msr + 24) | 3;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: segment_ctrl_pro.cc,v 1.55 2006-03-22 20:47:11 sshwarts Exp $
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// $Id: segment_ctrl_pro.cc,v 1.56 2006-03-27 18:02:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -223,7 +223,7 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
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if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS]) {
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seg->cache.u.segment.executable = 1; /* code segment */
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#if BX_SUPPORT_ICACHE
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BX_CPU_THIS_PTR fetchModeMask = createFetchModeMask(BX_CPU_THIS);
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BX_CPU_THIS_PTR updateFetchModeMask();
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#endif
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invalidate_prefetch_q();
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}
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248
bochs/cpu/smm.cc
248
bochs/cpu/smm.cc
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: smm.cc,v 1.7 2006-03-26 18:58:01 sshwarts Exp $
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// $Id: smm.cc,v 1.8 2006-03-27 18:02:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2006 Stanislav Shwartsman
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@ -53,6 +53,9 @@ void BX_CPU_C::enter_system_management_mode(void)
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{
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invalidate_prefetch_q();
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// save processor state to the SMRAM
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BX_CPU_THIS_PTR smram_save_state();
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// all status flags at known values, use BX_CPU_THIS_PTR eflags structure
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BX_CPU_THIS_PTR lf_flags_status = 0x000000;
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@ -86,7 +89,7 @@ void BX_CPU_C::enter_system_management_mode(void)
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#endif
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#if BX_SUPPORT_ICACHE
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BX_CPU_THIS_PTR fetchModeMask = createFetchModeMask(BX_CPU_THIS);
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BX_CPU_THIS_PTR updateFetchModeMask();
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#endif
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/* DS (Data Segment) and descriptor cache */
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@ -150,4 +153,245 @@ bx_bool BX_CPU_C::smram_write(bx_phy_address a20addr)
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return 1; // for now
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}
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#define SMRAM_TRANSLATE(addr) (((0x8000 - (addr)) >> 2) - 1)
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#if BX_SUPPORT_X86_64
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void BX_CPU_C::smram_save_state(void)
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{
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Bit32u saved_state[256], i;
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// reset reserved bits
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for(i=0;i<256;i++) saved_state[i] = 0;
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saved_state[SMRAM_TRANSLATE(0x7ff8)] = BX_CPU_THIS_PTR cr0.val32;
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saved_state[SMRAM_TRANSLATE(0x7ff4)] = BX_CPU_THIS_PTR cr3 >> 32;
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saved_state[SMRAM_TRANSLATE(0x7ff0)] = BX_CPU_THIS_PTR cr3 & 0xffffffff;
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saved_state[SMRAM_TRANSLATE(0x7fe8)] = read_eflags();
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saved_state[SMRAM_TRANSLATE(0x7fe0)] = BX_CPU_THIS_PTR get_EFER();
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saved_state[SMRAM_TRANSLATE(0x7fdc)] = RIP >> 32;
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saved_state[SMRAM_TRANSLATE(0x7fd8)] = RIP & 0xffffffff;
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saved_state[SMRAM_TRANSLATE(0x7fd0)] = BX_CPU_THIS_PTR dr6;
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saved_state[SMRAM_TRANSLATE(0x7fc8)] = BX_CPU_THIS_PTR dr7;
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saved_state[SMRAM_TRANSLATE(0x7fc4)] = BX_CPU_THIS_PTR tr.selector.value;
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saved_state[SMRAM_TRANSLATE(0x7fc0)] = BX_CPU_THIS_PTR ldtr.selector.value;
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saved_state[SMRAM_TRANSLATE(0x7fbc)] =
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value;
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saved_state[SMRAM_TRANSLATE(0x7fb8)] =
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value;
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saved_state[SMRAM_TRANSLATE(0x7fb4)] =
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value;
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saved_state[SMRAM_TRANSLATE(0x7fb0)] =
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
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saved_state[SMRAM_TRANSLATE(0x7fac)] =
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
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saved_state[SMRAM_TRANSLATE(0x7fa8)] =
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value;
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/* base+7fa4 is I/O MISC (4 byte) */
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/* base+7f9c is I/O MEM ADDRESS (8 byte) */
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saved_state[SMRAM_TRANSLATE(0x7f98)] = RDI >> 32;
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saved_state[SMRAM_TRANSLATE(0x7f94)] = RDI & 0xffffffff;
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saved_state[SMRAM_TRANSLATE(0x7f90)] = RSI >> 32;
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saved_state[SMRAM_TRANSLATE(0x7f8c)] = RSI & 0xffffffff;
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saved_state[SMRAM_TRANSLATE(0x7f88)] = RBP >> 32;
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saved_state[SMRAM_TRANSLATE(0x7f84)] = RBP & 0xffffffff;
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saved_state[SMRAM_TRANSLATE(0x7f80)] = RSP >> 32;
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saved_state[SMRAM_TRANSLATE(0x7f7c)] = RSP & 0xffffffff;
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saved_state[SMRAM_TRANSLATE(0x7f78)] = RBX >> 32;
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saved_state[SMRAM_TRANSLATE(0x7f74)] = RBX & 0xffffffff;
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saved_state[SMRAM_TRANSLATE(0x7f70)] = RDX >> 32;
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saved_state[SMRAM_TRANSLATE(0x7f6c)] = RDX & 0xffffffff;
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saved_state[SMRAM_TRANSLATE(0x7f68)] = RCX >> 32;
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saved_state[SMRAM_TRANSLATE(0x7f64)] = RCX & 0xffffffff;
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saved_state[SMRAM_TRANSLATE(0x7f60)] = RAX >> 32;
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saved_state[SMRAM_TRANSLATE(0x7f5c)] = RAX & 0xffffffff;
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||||
saved_state[SMRAM_TRANSLATE(0x7f58)] = R8 >> 32;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f54)] = R8 & 0xffffffff;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f50)] = R9 >> 32;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f4c)] = R9 & 0xffffffff;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f48)] = R10 >> 32;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f44)] = R10 & 0xffffffff;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f40)] = R11 >> 32;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f3c)] = R11 & 0xffffffff;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f38)] = R12 >> 32;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f34)] = R12 & 0xffffffff;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f30)] = R13 >> 32;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f2c)] = R13 & 0xffffffff;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f28)] = R14 >> 32;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f24)] = R14 & 0xffffffff;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f20)] = R15 >> 32;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f1c)] = R15 & 0xffffffff;
|
||||
/* base+0x7f1c to base+0x7f04 is reserved */
|
||||
/* base+0x7f02 is Auto HALT restart field (2 byte) */
|
||||
/* base+0x7f00 is I/O restart field (2 byte) */
|
||||
/* base+0x7efc is SMM Revision Identifier field */
|
||||
saved_state[SMRAM_TRANSLATE(0x7ef8)] = BX_CPU_THIS_PTR smbase;
|
||||
/* base+0x7ff4 to base+0x7fa8 is reserved */
|
||||
/* base+0x7fa4 is LDT Info (4 byte) */
|
||||
saved_state[SMRAM_TRANSLATE(0x7fa0)] =
|
||||
BX_CPU_THIS_PTR ldtr.cache.u.segment.limit;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f9c)] =
|
||||
BX_CPU_THIS_PTR ldtr.cache.u.segment.base & 0xffffffff;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f98)] = BX_CPU_THIS_PTR idtr.limit;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f94)] = BX_CPU_THIS_PTR idtr.base & 0xffffffff;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f90)] = BX_CPU_THIS_PTR gdtr.limit;
|
||||
saved_state[SMRAM_TRANSLATE(0x7f8c)] = BX_CPU_THIS_PTR gdtr.base & 0xffffffff;
|
||||
/* base+0x7e80 to base+0x7e44 is reserved */
|
||||
saved_state[SMRAM_TRANSLATE(0x7e40)] = BX_CPU_THIS_PTR cr4.getRegister();
|
||||
/* base+0x7e3c to base+0x7df0 is reserved */
|
||||
/* base+0x7de8 is I/O RIP (8 bytes) */
|
||||
/* base+0x7de4 to base+0x7ddc is reserved */
|
||||
saved_state[SMRAM_TRANSLATE(0x7dd8)] = BX_CPU_THIS_PTR idtr.base >> 32;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fd4)] =
|
||||
BX_CPU_THIS_PTR ldtr.cache.u.segment.base >> 32;
|
||||
saved_state[SMRAM_TRANSLATE(0x7dd0)] = BX_CPU_THIS_PTR gdtr.base >> 32;
|
||||
/* base+0x7dcc to base+0x7c00 is reserved */
|
||||
|
||||
bx_phy_address base = (BX_CPU_THIS_PTR smbase + 0x8000);
|
||||
base += 0x8000;
|
||||
|
||||
// could be optimized with writing of only non-reserved bytes
|
||||
for(i=0;i<256;i++) {
|
||||
base -= 4;
|
||||
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, base, 4, &saved_state[i]);
|
||||
}
|
||||
}
|
||||
|
||||
bx_bool BX_CPU_C::smram_restore_state(void)
|
||||
{
|
||||
Bit32u saved_state[256], i;
|
||||
|
||||
// reset reserved bits
|
||||
for(i=0;i<256;i++) saved_state[i] = 0;
|
||||
|
||||
bx_phy_address base = (BX_CPU_THIS_PTR smbase + 0x8000);
|
||||
base += 0x8000;
|
||||
|
||||
// could be optimized with reading of only non-reserved bytes
|
||||
for(i=0;i<256;i++) {
|
||||
base -= 4;
|
||||
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, base, 4, &saved_state[i]);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#else /* BX_SUPPORT_X86_64 == 0 */
|
||||
|
||||
void BX_CPU_C::smram_save_state(void)
|
||||
{
|
||||
Bit32u saved_state[128], i;
|
||||
|
||||
// reset reserved bits
|
||||
for(i=0;i<128;i++) saved_state[i] = 0;
|
||||
|
||||
saved_state[SMRAM_TRANSLATE(0x7ffc)] = BX_CPU_THIS_PTR cr0.val32;
|
||||
saved_state[SMRAM_TRANSLATE(0x7ff8)] = BX_CPU_THIS_PTR cr3;
|
||||
saved_state[SMRAM_TRANSLATE(0x7ff4)] = read_eflags();
|
||||
saved_state[SMRAM_TRANSLATE(0x7ff0)] = EIP;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fec)] = EDI;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fe8)] = ESI;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fe4)] = EBP;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fe0)] = ESP;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fdc)] = EBX;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fd8)] = EDX;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fd4)] = ECX;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fd0)] = EAX;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fcc)] = BX_CPU_THIS_PTR dr6;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fc8)] = BX_CPU_THIS_PTR dr7;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fc4)] = BX_CPU_THIS_PTR tr.selector.value;
|
||||
/* base+0x7fc0 is reserved field */
|
||||
saved_state[SMRAM_TRANSLATE(0x7fbc)] =
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fb8)] =
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fb4)] =
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fb0)] =
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fac)] =
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
|
||||
saved_state[SMRAM_TRANSLATE(0x7fa8)] =
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value;
|
||||
/* base+0x7fa4 is I/O state field */
|
||||
/* base+0x7fa0 is I/O Memory Address field */
|
||||
/* base+0x7f9c to base+0x7f04 is reserved */
|
||||
/* base+0x7f02 is Auto HALT restart field (2 byte) */
|
||||
/* base+0x7f00 is I/O restart field (2 byte) */
|
||||
/* base+0x7efc is SMM Revision Identifier field */
|
||||
saved_state[SMRAM_TRANSLATE(0x7ef8)] = BX_CPU_THIS_PTR smbase;
|
||||
/* base+0x7ef4 to base+0x7e00 is reserved */
|
||||
|
||||
bx_phy_address base = (BX_CPU_THIS_PTR smbase + 0x8000);
|
||||
base += 0x8000;
|
||||
|
||||
// could be optimized with writing of only non-reserved bytes
|
||||
for(i=0;i<128;i++) {
|
||||
base -= 4;
|
||||
BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, base, 4, &saved_state[i]);
|
||||
}
|
||||
}
|
||||
|
||||
bx_bool BX_CPU_C::smram_restore_state(void)
|
||||
{
|
||||
Bit32u saved_state[128], i;
|
||||
|
||||
// reset reserved bits
|
||||
for(i=0;i<128;i++) saved_state[i] = 0;
|
||||
|
||||
bx_phy_address base = (BX_CPU_THIS_PTR smbase + 0x8000);
|
||||
base += 0x8000;
|
||||
|
||||
// could be optimized with reading of only non-reserved bytes
|
||||
for(i=0;i<128;i++) {
|
||||
base -= 4;
|
||||
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, base, 4, &saved_state[i]);
|
||||
}
|
||||
|
||||
setCR0(saved_state[SMRAM_TRANSLATE(0x7ffc)]);
|
||||
CR3_change(saved_state[SMRAM_TRANSLATE(0x7ff8)]);
|
||||
setEFlags(saved_state[SMRAM_TRANSLATE(0x7ff4)]);
|
||||
|
||||
EIP = saved_state[SMRAM_TRANSLATE(0x7ff0)];
|
||||
EDI = saved_state[SMRAM_TRANSLATE(0x7fec)];
|
||||
ESI = saved_state[SMRAM_TRANSLATE(0x7fe8)];
|
||||
EBP = saved_state[SMRAM_TRANSLATE(0x7fe4)];
|
||||
ESP = saved_state[SMRAM_TRANSLATE(0x7fe0)];
|
||||
EBX = saved_state[SMRAM_TRANSLATE(0x7fdc)];
|
||||
EDX = saved_state[SMRAM_TRANSLATE(0x7fd8)];
|
||||
ECX = saved_state[SMRAM_TRANSLATE(0x7fd4)];
|
||||
EAX = saved_state[SMRAM_TRANSLATE(0x7fd0)];
|
||||
|
||||
BX_CPU_THIS_PTR dr6 = saved_state[SMRAM_TRANSLATE(0x7fcc)];
|
||||
BX_CPU_THIS_PTR dr7 = saved_state[SMRAM_TRANSLATE(0x7fc8)];
|
||||
|
||||
// saved_state[SMRAM_TRANSLATE(0x7fc4)] = BX_CPU_THIS_PTR tr.selector.value;
|
||||
// /* base+0x7fc0 is reserved field */
|
||||
// saved_state[SMRAM_TRANSLATE(0x7fbc)] =
|
||||
// BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value;
|
||||
// saved_state[SMRAM_TRANSLATE(0x7fb8)] =
|
||||
// BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value;
|
||||
// saved_state[SMRAM_TRANSLATE(0x7fb4)] =
|
||||
// BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value;
|
||||
// saved_state[SMRAM_TRANSLATE(0x7fb0)] =
|
||||
// BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
|
||||
// saved_state[SMRAM_TRANSLATE(0x7fac)] =
|
||||
// BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
|
||||
// saved_state[SMRAM_TRANSLATE(0x7fa8)] =
|
||||
// BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value;
|
||||
|
||||
/* base+0x7fa4 is I/O state field */
|
||||
/* base+0x7fa0 is I/O Memory Address field */
|
||||
/* base+0x7f9c to base+0x7f04 is reserved */
|
||||
/* base+0x7f02 is Auto HALT restart field (2 byte) */
|
||||
/* base+0x7f00 is I/O restart field (2 byte) */
|
||||
/* base+0x7efc is SMM Revision Identifier field */
|
||||
BX_CPU_THIS_PTR smbase = saved_state[SMRAM_TRANSLATE(0x7ef8)];
|
||||
/* base+0x7ef4 to base+0x7e00 is reserved */
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif /* BX_SUPPORT_X86_64 */
|
||||
|
||||
#endif /* BX_CPU_LEVEL >= 3 */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: tasking.cc,v 1.31 2006-03-06 22:03:04 sshwarts Exp $
|
||||
// $Id: tasking.cc,v 1.32 2006-03-27 18:02:07 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -608,8 +608,8 @@ void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
|
||||
goto post_exception;
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_ICACHE // update instruction cache
|
||||
BX_CPU_THIS_PTR fetchModeMask = createFetchModeMask(BX_CPU_THIS);
|
||||
#if BX_SUPPORT_ICACHE
|
||||
BX_CPU_THIS_PTR updateFetchModeMask();
|
||||
#endif
|
||||
|
||||
// SS
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: vm8086.cc,v 1.25 2006-03-06 22:03:04 sshwarts Exp $
|
||||
// $Id: vm8086.cc,v 1.26 2006-03-27 18:02:07 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -254,7 +254,7 @@ void BX_CPU_C::init_v8086_mode(void)
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl = 3;
|
||||
|
||||
#if BX_SUPPORT_ICACHE // update instruction cache
|
||||
BX_CPU_THIS_PTR fetchModeMask = createFetchModeMask(BX_CPU_THIS);
|
||||
BX_CPU_THIS_PTR updateFetchModeMask();
|
||||
#endif
|
||||
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: load32bitOShack.cc,v 1.20 2006-03-06 22:02:48 sshwarts Exp $
|
||||
// $Id: load32bitOShack.cc,v 1.21 2006-03-27 18:02:06 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -245,6 +245,10 @@ void bx_load_null_kernel_hack(void)
|
||||
BX_CPU(0)->sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; // page gran
|
||||
BX_CPU(0)->sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1; // 32bit
|
||||
|
||||
#if BX_SUPPORT_ICACHE
|
||||
BX_CPU(0)->updateFetchModeMask();
|
||||
#endif
|
||||
|
||||
// DS deltas
|
||||
BX_CPU(0)->sregs[BX_SEG_REG_DS].cache.u.segment.base = 0x00000000;
|
||||
BX_CPU(0)->sregs[BX_SEG_REG_DS].cache.u.segment.limit = 0xFFFFF;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: memory.h,v 1.35 2006-03-26 22:15:07 sshwarts Exp $
|
||||
// $Id: memory.h,v 1.36 2006-03-27 18:02:07 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -92,6 +92,7 @@ public:
|
||||
BX_MEM_SMF void init_memory(int memsize);
|
||||
BX_MEM_SMF void enable_smram(bx_bool enable, bx_bool restricted);
|
||||
BX_MEM_SMF void disable_smram(void);
|
||||
BX_MEM_SMF bx_bool is_smram_accessible(void);
|
||||
BX_MEM_SMF void readPhysicalPage(BX_CPU_C *cpu, Bit32u addr,
|
||||
unsigned len, void *data) BX_CPP_AttrRegparmN(3);
|
||||
BX_MEM_SMF void writePhysicalPage(BX_CPU_C *cpu, Bit32u addr,
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: misc_mem.cc,v 1.85 2006-03-26 22:15:07 sshwarts Exp $
|
||||
// $Id: misc_mem.cc,v 1.86 2006-03-27 18:02:07 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2002 MandrakeSoft S.A.
|
||||
@ -94,7 +94,7 @@ void BX_MEM_C::init_memory(int memsize)
|
||||
{
|
||||
int idx;
|
||||
|
||||
BX_DEBUG(("Init $Id: misc_mem.cc,v 1.85 2006-03-26 22:15:07 sshwarts Exp $"));
|
||||
BX_DEBUG(("Init $Id: misc_mem.cc,v 1.86 2006-03-27 18:02:07 sshwarts Exp $"));
|
||||
// you can pass 0 if memory has been allocated already through
|
||||
// the constructor, or the desired size of memory if it hasn't
|
||||
|
||||
@ -751,16 +751,23 @@ BX_MEM_C::unregisterMemoryHandlers(memory_handler_t read_handler, memory_handler
|
||||
return ret;
|
||||
}
|
||||
|
||||
BX_MEM_SMF void BX_MEM_C::enable_smram(bx_bool enable, bx_bool restricted)
|
||||
void BX_MEM_C::enable_smram(bx_bool enable, bx_bool restricted)
|
||||
{
|
||||
BX_MEM_THIS smram_available = 1;
|
||||
BX_MEM_THIS smram_enable = (enable > 0);
|
||||
BX_MEM_THIS smram_restricted = (restricted > 0);
|
||||
}
|
||||
|
||||
BX_MEM_SMF void BX_MEM_C::disable_smram(void)
|
||||
void BX_MEM_C::disable_smram(void)
|
||||
{
|
||||
BX_MEM_THIS smram_available = 0;
|
||||
BX_MEM_THIS smram_enable = 0;
|
||||
BX_MEM_THIS smram_restricted = 0;
|
||||
}
|
||||
|
||||
// check if SMRAM is aavailable for CPU data accesses
|
||||
bx_bool BX_MEM_C::is_smram_accessible(void)
|
||||
{
|
||||
return(BX_MEM_THIS smram_available) &&
|
||||
(BX_MEM_THIS smram_enable || !BX_MEM_THIS smram_restricted);
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user