Implement SMRAM conrol register in i440fx chipset and all its functionality in memory class
This commit is contained in:
Stanislav Shwartsman
parent
f3ac069c90
commit
c7d142200f
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: devices.cc,v 1.95 2006-03-14 18:11:22 sshwarts Exp $
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// $Id: devices.cc,v 1.96 2006-03-26 22:15:05 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -105,7 +105,7 @@ void bx_devices_c::init(BX_MEM_C *newmem)
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{
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unsigned i;
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BX_DEBUG(("Init $Id: devices.cc,v 1.95 2006-03-14 18:11:22 sshwarts Exp $"));
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BX_DEBUG(("Init $Id: devices.cc,v 1.96 2006-03-26 22:15:05 sshwarts Exp $"));
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mem = newmem;
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/* set no-default handlers, will be overwritten by the real default handler */
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@ -316,6 +316,7 @@ void bx_devices_c::init(BX_MEM_C *newmem)
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void bx_devices_c::reset(unsigned type)
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{
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mem->disable_smram();
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pluginUnmapped->reset(type);
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#if BX_SUPPORT_PCI
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if (SIM->get_param_bool(BXPN_I440FX_SUPPORT)->get ()) {
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: pci.cc,v 1.46 2006-03-07 21:11:19 sshwarts Exp $
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// $Id: pci.cc,v 1.47 2006-03-26 22:15:06 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -61,7 +61,6 @@ bx_pci_bridge_c::bx_pci_bridge_c()
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bx_pci_bridge_c::~bx_pci_bridge_c()
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{
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// nothing for now
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BX_DEBUG(("Exit."));
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}
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void bx_pci_bridge_c::init(void)
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@ -146,6 +145,7 @@ bx_pci_bridge_c::reset(unsigned type)
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BX_PCI_THIS s.i440fx.pci_conf[0x58] = 0x10;
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for (i=0x59; i<0x60; i++)
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BX_PCI_THIS s.i440fx.pci_conf[i] = 0x00;
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BX_PCI_THIS s.i440fx.pci_conf[0x72] = 0x02;
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}
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// static IO port read callback handler
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@ -291,6 +291,9 @@ void bx_pci_bridge_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io
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case 0x06:
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case 0x0c:
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break;
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case 0x72:
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smram_control(value); // SMRAM conrol register
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break;
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default:
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BX_PCI_THIS s.i440fx.pci_conf[address+i] = value8;
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BX_DEBUG(("440FX PMC write register 0x%02x value 0x%02x", address+i, value8));
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@ -299,6 +302,62 @@ void bx_pci_bridge_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io
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}
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}
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void bx_pci_bridge_c::smram_control(Bit8u value8)
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{
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//
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// From i440FX chipset manual:
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//
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// [7:7] Reserved.
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// [6:6] SMM Space Open (DOPEN), when DOPEN=1 and DLCK=0, SMM space DRAM
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// became visible even CPU not indicte SMM mode access. This is
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// indended to help BIOS to initialize SMM space.
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// [5:5] SMM Space Closed (DCLS), when DCLS=1, SMM space is not accessible
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// for data references, even if CPU indicates SMM mode access. Code
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// references may still access SMM space DRAM.
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// [4:4] SMM Space Locked (DLCK), when DLCK=1, DOPEN is set to 0 and
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// both DLCK and DOPEN became R/O. DLCK can only be cleared by
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// a power-on reset.
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// [3:3] SMRAM Enable (SMRAME)
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// [2:0] SMM space base segment, program the location of SMM space
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// reserved.
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//
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// SMRAM space access cycles:
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// | SMRAME | DLCK | DCLS | DOPEN | CPU_SMM | | Code | Data |
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// ------------------------------------------ ---------------
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// | 0 | X | X | X | X | -> | PCI | PCI |
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// | 1 | 0 | X | 0 | 0 | -> | PCI | PCI |
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// | 1 | 0 | 0 | 0 | 1 | -> | DRAM | DRAM |
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// | 1 | 0 | 0 | 1 | X | -> | DRAM | DRAM |
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// | 1 | 1 | 0 | X | 1 | -> | DRAM | DRAM |
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// | 1 | 0 | 1 | 0 | 1 | -> | DRAM | PCI |
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// | 1 | 0 | 1 | 1 | X | -> | ---- | ---- |
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// | 1 | 1 | X | X | 0 | -> | PCI | PCI |
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// | 1 | 1 | 1 | X | 1 | -> | DRAM | PCI |
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// ------------------------------------------ ---------------
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value8 = (value8 & 0x78) | 0x2; // ignore reserved bits
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if (BX_PCI_THIS s.i440fx.pci_conf[0x72] & 0x10)
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{
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value8 &= 0xbf; // set DOPEN=0, DLCK=1
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value8 |= 0x10;
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}
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if ((value8 & 0x08) == 0) {
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bx_devices.mem->disable_smram();
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}
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else {
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bx_bool DOPEN = (value8 & 0x40) > 0, DCLS = (value8 & 0x20) > 0;
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if(DOPEN && DCLS) BX_PANIC(("SMRAM control: DOPEN not mutually exclusive with DCLS !"));
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bx_devices.mem->enable_smram(DOPEN, DCLS);
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}
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BX_INFO(("setting SMRAM control register to 0x%02x", value8));
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BX_PCI_THIS s.i440fx.pci_conf[0x72] = value8;
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}
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Bit8u bx_pci_bridge_c::rd_memType(Bit32u addr)
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{
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switch ((addr & 0xFC000) >> 12) {
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: pci.h,v 1.24 2006-03-07 21:11:19 sshwarts Exp $
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// $Id: pci.h,v 1.25 2006-03-26 22:15:06 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -90,6 +90,8 @@ private:
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bx_def440fx_t i440fx;
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} s;
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void smram_control(Bit8u value);
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static Bit32u read_handler(void *this_ptr, Bit32u address, unsigned io_len);
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static void write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len);
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#if !BX_USE_PCI_SMF
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: memory.cc,v 1.51 2006-03-26 18:58:01 sshwarts Exp $
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// $Id: memory.cc,v 1.52 2006-03-26 22:15:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -78,9 +78,10 @@ BX_MEM_C::writePhysicalPage(BX_CPU_C *cpu, Bit32u addr, unsigned len, void *data
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}
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#endif
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if ((a20addr & 0xfffe0000) == 0x000a0000) {
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// SMMRAM memory space
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if (BX_MEM_THIS smram_enabled > 1 || cpu->smm_mode())
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if ((a20addr & 0xfffe0000) == 0x000a0000 && (BX_MEM_THIS smram_available))
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{
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// SMRAM memory space
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if (BX_MEM_THIS smram_enable || (cpu->smm_mode() && !BX_MEM_THIS smram_restricted))
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goto mem_write;
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}
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}
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@ -235,9 +236,10 @@ BX_MEM_C::readPhysicalPage(BX_CPU_C *cpu, Bit32u addr, unsigned len, void *data)
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}
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#endif
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if ((a20addr & 0xfffe0000) == 0x000a0000) {
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// SMMRAM memory space
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if (BX_MEM_THIS smram_enabled > 1 || cpu->smm_mode())
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if ((a20addr & 0xfffe0000) == 0x000a0000 && (BX_MEM_THIS smram_available))
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{
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// SMRAM memory space
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if (BX_MEM_THIS smram_enable || (cpu->smm_mode() && !BX_MEM_THIS smram_restricted))
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goto mem_read;
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}
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: memory.h,v 1.34 2006-03-26 19:39:37 sshwarts Exp $
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// $Id: memory.h,v 1.35 2006-03-26 22:15:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -68,7 +68,9 @@ private:
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struct memory_handler_struct **memory_handlers;
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bx_bool rom_present[65];
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bx_bool pci_enabled;
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unsigned smram_enabled;
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bx_bool smram_available;
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bx_bool smram_enable;
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bx_bool smram_restricted;
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public:
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Bit8u *actual_vector;
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@ -88,7 +90,7 @@ public:
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~BX_MEM_C();
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BX_MEM_SMF void alloc_vector_aligned (size_t bytes, size_t alignment) BX_CPP_AttrRegparmN(2);
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BX_MEM_SMF void init_memory(int memsize);
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BX_MEM_SMF void enable_smram(bx_bool code_only);
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BX_MEM_SMF void enable_smram(bx_bool enable, bx_bool restricted);
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BX_MEM_SMF void disable_smram(void);
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BX_MEM_SMF void readPhysicalPage(BX_CPU_C *cpu, Bit32u addr,
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unsigned len, void *data) BX_CPP_AttrRegparmN(3);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: misc_mem.cc,v 1.84 2006-03-26 19:48:54 sshwarts Exp $
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// $Id: misc_mem.cc,v 1.85 2006-03-26 22:15:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -94,7 +94,7 @@ void BX_MEM_C::init_memory(int memsize)
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{
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int idx;
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BX_DEBUG(("Init $Id: misc_mem.cc,v 1.84 2006-03-26 19:48:54 sshwarts Exp $"));
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BX_DEBUG(("Init $Id: misc_mem.cc,v 1.85 2006-03-26 22:15:07 sshwarts Exp $"));
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// you can pass 0 if memory has been allocated already through
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// the constructor, or the desired size of memory if it hasn't
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@ -115,7 +115,9 @@ void BX_MEM_C::init_memory(int memsize)
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BX_INFO(("%.2fMB", (float)(BX_MEM_THIS megabytes)));
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}
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BX_MEM_THIS pci_enabled = SIM->get_param_bool(BXPN_I440FX_SUPPORT)->get();
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BX_MEM_THIS smram_enabled = 0;
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BX_MEM_THIS smram_available = 0;
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BX_MEM_THIS smram_enable = 0;
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BX_MEM_THIS smram_restricted = 0;
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#if BX_DEBUGGER
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if (megabytes > BX_MAX_DIRTY_PAGE_TABLE_MEGS) {
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@ -437,7 +439,7 @@ bx_bool BX_MEM_C::dbg_fetch_mem(Bit32u addr, unsigned len, Bit8u *buf)
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for (; len>0; len--) {
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// Reading standard PCI/ISA Video Mem / SMMRAM
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if ((addr & 0xfffe0000) == 0x000a0000) {
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if (BX_MEM_THIS smram_enabled)
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if (BX_MEM_THIS smram_enable)
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*buf = vector[addr];
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else
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*buf = DEV_vga_mem_read(addr);
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@ -503,7 +505,7 @@ bx_bool BX_MEM_C::dbg_set_mem(Bit32u addr, unsigned len, Bit8u *buf)
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for (; len>0; len--) {
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// Write to standard PCI/ISA Video Mem / SMMRAM
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if ((a20Addr & 0xfffe0000) == 0x000a0000) {
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if (BX_MEM_THIS smram_enabled)
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if (BX_MEM_THIS smram_enable)
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vector[addr] = *buf;
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else
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DEV_vga_mem_write(addr, *buf);
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@ -581,11 +583,12 @@ Bit8u *BX_MEM_C::getHostMemAddr(BX_CPU_C *cpu, Bit32u a20Addr, unsigned op, unsi
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return(NULL); // Vetoed! APIC address space
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#endif
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// allow direct access to SMMRAM memory space for code and veto data
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// allow direct access to SMRAM memory space for code and veto data
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if (access_type == CODE_ACCESS) {
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// reading from SMMRAM memory space
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if ((a20Addr & 0xfffe0000) == 0x000a0000) {
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if (BX_MEM_THIS smram_enabled || cpu->smm_mode())
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// reading from SMRAM memory space
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if ((a20Addr & 0xfffe0000) == 0x000a0000 && (BX_MEM_THIS smram_available))
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{
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if (BX_MEM_THIS smram_enable || cpu->smm_mode())
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return (Bit8u *) & vector[a20Addr];
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}
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}
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@ -748,12 +751,16 @@ BX_MEM_C::unregisterMemoryHandlers(memory_handler_t read_handler, memory_handler
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return ret;
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}
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BX_MEM_SMF void BX_MEM_C::enable_smram(bx_bool code_only)
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BX_MEM_SMF void BX_MEM_C::enable_smram(bx_bool enable, bx_bool restricted)
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{
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BX_MEM_THIS smram_enabled = code_only ? 1 : 2;
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BX_MEM_THIS smram_available = 1;
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BX_MEM_THIS smram_enable = (enable > 0);
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BX_MEM_THIS smram_restricted = (restricted > 0);
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}
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BX_MEM_SMF void BX_MEM_C::disable_smram(void)
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{
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BX_MEM_THIS smram_enabled = 0;
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BX_MEM_THIS smram_available = 0;
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BX_MEM_THIS smram_enable = 0;
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BX_MEM_THIS smram_restricted = 0;
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}
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