separate APIC from CPU
This commit is contained in:
Stanislav Shwartsman
parent
8559551001
commit
79f46df971
147
bochs/cpu/apic.h
Normal file
147
bochs/cpu/apic.h
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#ifndef BX_CPU_APIC_H
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# define BX_CPU_APIC_H 1
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typedef enum {
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APIC_TYPE_NONE,
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APIC_TYPE_IOAPIC,
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APIC_TYPE_LOCAL_APIC
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} bx_apic_type_t;
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#define APIC_BASE_ADDR 0xfee00000 // default APIC address
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#if BX_SUPPORT_APIC
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class BOCHSAPI bx_generic_apic_c : public logfunctions {
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protected:
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Bit32u base_addr;
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Bit8u id;
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#define APIC_UNKNOWN_ID 0xff
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#define APIC_VERSION_ID 0x00170011 // same version as 82093 IOAPIC
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public:
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bx_generic_apic_c ();
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virtual ~bx_generic_apic_c ();
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virtual void init ();
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virtual void hwreset () { }
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Bit32u get_base (void) const { return base_addr; }
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void set_base (Bit32u newbase);
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void set_id (Bit8u newid);
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Bit8u get_id () const { return id; }
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static void reset_all_ids ();
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virtual char *get_name();
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bx_bool is_selected (Bit32u addr, Bit32u len);
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void read (Bit32u addr, void *data, unsigned len);
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virtual void read_aligned(Bit32u address, Bit32u *data, unsigned len);
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virtual void write(Bit32u address, Bit32u *value, unsigned len);
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virtual void startup_msg (Bit32u vector);
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// on local APIC, trigger means deliver to the CPU.
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// on I/O APIC, trigger means direct to another APIC according to table.
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virtual void trigger_irq (unsigned num, unsigned from);
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virtual void untrigger_irq (unsigned num, unsigned from);
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virtual Bit32u get_delivery_bitmask (Bit8u dest, Bit8u dest_mode);
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virtual bx_bool deliver (Bit8u destination, Bit8u dest_mode, Bit8u delivery_mode, Bit8u vector, Bit8u polarity, Bit8u trig_mode);
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virtual bx_bool match_logical_addr (Bit8u address);
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virtual bx_apic_type_t get_type ();
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virtual void set_arb_id (int newid); // only implemented on local apics
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};
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class BOCHSAPI bx_local_apic_c : public bx_generic_apic_c {
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#define BX_LOCAL_APIC_MAX_INTS 256
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// TMR=trigger mode register. Cleared for edge-triggered interrupts
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// and set for level-triggered interrupts. If set, local APIC must send
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// EOI message to all other APICs. EOI's are not implemented.
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Bit8u tmr[BX_LOCAL_APIC_MAX_INTS];
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// IRR=interrupt request register. When an interrupt is triggered by
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// the I/O APIC or another processor, it sets a bit in irr. The bit is
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// cleared when the interrupt is acknowledged by the processor.
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Bit8u irr[BX_LOCAL_APIC_MAX_INTS];
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// ISR=in-service register. When an IRR bit is cleared, the corresponding
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// bit in ISR is set. The ISR bit is cleared when
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Bit8u isr[BX_LOCAL_APIC_MAX_INTS];
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Bit32u arb_id, arb_priority, task_priority, log_dest, dest_format, spurious_vec;
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Bit32u lvt[6];
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#define APIC_LVT_TIMER 0
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#define APIC_LVT_THERMAL 1
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#define APIC_LVT_PERFORM 2
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#define APIC_LVT_LINT0 3
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#define APIC_LVT_LINT1 4
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#define APIC_LVT_ERROR 5
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Bit32u timer_initial, timer_current, timer_divconf;
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bx_bool timer_active; // internal state, not accessible from bus
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Bit32u timer_divide_counter, timer_divide_factor;
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Bit32u icr_high, icr_low;
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Bit32u err_status;
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#define APIC_ERR_ILLEGAL_ADDR 0x80
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#define APIC_ERR_RX_ILLEGAL_VEC 0x40
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#define APIC_ERR_TX_ILLEGAL_VEC 0x20
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#define APIC_ERR_RX_ACCEPT_ERR 0x08
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#define APIC_ERR_TX_ACCEPT_ERR 0x04
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#define APIC_ERR_RX_CHECKSUM 0x02
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#define APIC_ERR_TX_CHECKSUM 0x01
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int timer_handle; // KPL
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Bit64u ticksInitial; // System ticks count when APIC timer is started.
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public:
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bx_bool INTR;
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bx_local_apic_c(BX_CPU_C *mycpu);
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virtual ~bx_local_apic_c(void);
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BX_CPU_C *cpu;
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virtual void hwreset ();
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virtual void init ();
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BX_CPU_C *get_cpu (Bit8u id);
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void set_id (Bit8u newid); // redefine to set cpu->name
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virtual char *get_name();
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virtual void write (Bit32u addr, Bit32u *data, unsigned len);
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virtual void read_aligned(Bit32u address, Bit32u *data, unsigned len);
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virtual void startup_msg (Bit32u vector);
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// on local APIC, trigger means raise the CPU's INTR line. For now
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// I also have to raise pc_system.INTR but that should be replaced
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// with the cpu-specific INTR signals.
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virtual void trigger_irq (unsigned num, unsigned from);
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virtual void untrigger_irq (unsigned num, unsigned from);
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Bit8u acknowledge_int (); // only the local CPU should call this
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int highest_priority_int (Bit8u *array);
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void service_local_apic ();
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void print_status ();
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virtual bx_bool match_logical_addr (Bit8u address);
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virtual bx_bool is_local_apic () const { return true; }
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virtual bx_apic_type_t get_type () const { return APIC_TYPE_LOCAL_APIC; }
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virtual Bit32u get_delivery_bitmask (Bit8u dest, Bit8u dest_mode);
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virtual bx_bool deliver (Bit8u destination, Bit8u dest_mode, Bit8u delivery_mode, Bit8u vector, Bit8u polarity, Bit8u trig_mode);
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Bit8u get_ppr ();
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Bit8u get_apr ();
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static void periodic_smf(void *); // KPL
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void periodic(void); // KPL
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void set_divide_configuration (Bit32u value);
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virtual void update_msr_apicbase(Bit32u newaddr);
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virtual void set_arb_id (int newid);
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};
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#define APIC_MAX_ID 16
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extern bx_generic_apic_c *apic_index[APIC_MAX_ID];
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#endif // if BX_SUPPORT_APIC
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#endif
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132
bochs/cpu/cpu.h
132
bochs/cpu/cpu.h
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.142 2003-08-17 18:15:04 akrisak Exp $
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// $Id: cpu.h,v 1.143 2003-08-17 18:55:16 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1066,8 +1066,6 @@ typedef struct {
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#endif
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#if BX_USE_TLB
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typedef bx_ptr_equiv_t bx_hostpageaddr_t;
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@ -1172,131 +1170,11 @@ typedef struct {
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#endif // #if BX_SUPPORT_X86_64
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typedef enum {
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APIC_TYPE_NONE,
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APIC_TYPE_IOAPIC,
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APIC_TYPE_LOCAL_APIC
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} bx_apic_type_t;
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#define APIC_BASE_ADDR 0xfee00000 // default APIC address
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#if BX_SUPPORT_APIC
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class BOCHSAPI bx_generic_apic_c : public logfunctions {
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protected:
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Bit32u base_addr;
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Bit8u id;
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#define APIC_UNKNOWN_ID 0xff
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#define APIC_VERSION_ID 0x00170011 // same version as 82093 IOAPIC
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public:
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bx_generic_apic_c ();
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virtual ~bx_generic_apic_c ();
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virtual void init ();
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virtual void hwreset () { }
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Bit32u get_base (void) { return base_addr; }
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void set_base (Bit32u newbase);
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void set_id (Bit8u newid);
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Bit8u get_id () { return id; }
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static void reset_all_ids ();
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virtual char *get_name();
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bx_bool is_selected (Bit32u addr, Bit32u len);
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void read (Bit32u addr, void *data, unsigned len);
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virtual void read_aligned(Bit32u address, Bit32u *data, unsigned len);
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virtual void write(Bit32u address, Bit32u *value, unsigned len);
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virtual void startup_msg (Bit32u vector);
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// on local APIC, trigger means deliver to the CPU.
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// on I/O APIC, trigger means direct to another APIC according to table.
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virtual void trigger_irq (unsigned num, unsigned from);
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virtual void untrigger_irq (unsigned num, unsigned from);
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virtual Bit32u get_delivery_bitmask (Bit8u dest, Bit8u dest_mode);
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virtual bx_bool deliver (Bit8u destination, Bit8u dest_mode, Bit8u delivery_mode, Bit8u vector, Bit8u polarity, Bit8u trig_mode);
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virtual bx_bool match_logical_addr (Bit8u address);
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virtual bx_apic_type_t get_type ();
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virtual void set_arb_id (int newid); // only implemented on local apics
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};
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class BOCHSAPI bx_local_apic_c : public bx_generic_apic_c {
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#define BX_LOCAL_APIC_MAX_INTS 256
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// TMR=trigger mode register. Cleared for edge-triggered interrupts
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// and set for level-triggered interrupts. If set, local APIC must send
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// EOI message to all other APICs. EOI's are not implemented.
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Bit8u tmr[BX_LOCAL_APIC_MAX_INTS];
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// IRR=interrupt request register. When an interrupt is triggered by
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// the I/O APIC or another processor, it sets a bit in irr. The bit is
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// cleared when the interrupt is acknowledged by the processor.
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Bit8u irr[BX_LOCAL_APIC_MAX_INTS];
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// ISR=in-service register. When an IRR bit is cleared, the corresponding
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// bit in ISR is set. The ISR bit is cleared when
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Bit8u isr[BX_LOCAL_APIC_MAX_INTS];
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Bit32u arb_id, arb_priority, task_priority, log_dest, dest_format, spurious_vec;
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Bit32u lvt[6];
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#define APIC_LVT_TIMER 0
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#define APIC_LVT_THERMAL 1
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#define APIC_LVT_PERFORM 2
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#define APIC_LVT_LINT0 3
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#define APIC_LVT_LINT1 4
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#define APIC_LVT_ERROR 5
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Bit32u timer_initial, timer_current, timer_divconf;
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bx_bool timer_active; // internal state, not accessible from bus
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Bit32u timer_divide_counter, timer_divide_factor;
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Bit32u icr_high, icr_low;
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Bit32u err_status;
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#define APIC_ERR_ILLEGAL_ADDR 0x80
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#define APIC_ERR_RX_ILLEGAL_VEC 0x40
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#define APIC_ERR_TX_ILLEGAL_VEC 0x20
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#define APIC_ERR_RX_ACCEPT_ERR 0x08
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#define APIC_ERR_TX_ACCEPT_ERR 0x04
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#define APIC_ERR_RX_CHECKSUM 0x02
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#define APIC_ERR_TX_CHECKSUM 0x01
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int timer_handle; // KPL
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Bit64u ticksInitial; // System ticks count when APIC timer is started.
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public:
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bx_bool INTR;
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bx_local_apic_c(BX_CPU_C *mycpu);
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virtual ~bx_local_apic_c(void);
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BX_CPU_C *cpu;
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virtual void hwreset ();
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virtual void init ();
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BX_CPU_C *get_cpu (Bit8u id);
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void set_id (Bit8u newid); // redefine to set cpu->name
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virtual char *get_name();
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virtual void write (Bit32u addr, Bit32u *data, unsigned len);
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virtual void read_aligned(Bit32u address, Bit32u *data, unsigned len);
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virtual void startup_msg (Bit32u vector);
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// on local APIC, trigger means raise the CPU's INTR line. For now
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// I also have to raise pc_system.INTR but that should be replaced
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// with the cpu-specific INTR signals.
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virtual void trigger_irq (unsigned num, unsigned from);
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virtual void untrigger_irq (unsigned num, unsigned from);
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Bit8u acknowledge_int (); // only the local CPU should call this
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int highest_priority_int (Bit8u *array);
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void service_local_apic ();
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void print_status ();
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virtual bx_bool match_logical_addr (Bit8u address);
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virtual bx_bool is_local_apic () { return true; }
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virtual bx_apic_type_t get_type () { return APIC_TYPE_LOCAL_APIC; }
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virtual Bit32u get_delivery_bitmask (Bit8u dest, Bit8u dest_mode);
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virtual bx_bool deliver (Bit8u destination, Bit8u dest_mode, Bit8u delivery_mode, Bit8u vector, Bit8u polarity, Bit8u trig_mode);
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Bit8u get_ppr ();
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Bit8u get_apr ();
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static void periodic_smf(void *); // KPL
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void periodic(void); // KPL
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void set_divide_configuration (Bit32u value);
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virtual void update_msr_apicbase(Bit32u newaddr);
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virtual void set_arb_id (int newid);
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};
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#define APIC_MAX_ID 16
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extern bx_generic_apic_c *apic_index[APIC_MAX_ID];
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#endif // if BX_SUPPORT_APIC
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typedef void (*BxDTShim_t)(void);
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#include "cpu/apic.h"
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class BX_MEM_C;
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#if BX_SUPPORT_FPU
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#if BX_SUPPORT_FPU || BX_SUPPORT_MMX
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#include "cpu/i387.h"
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#endif
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@ -1304,6 +1182,10 @@ class BX_MEM_C;
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#include "cpu/xmm.h"
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#endif
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#if BX_DYNAMIC_TRANSLATION
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typedef void (*BxDTShim_t)(void);
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#endif
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class BOCHSAPI BX_CPU_C : public logfunctions {
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public: // for now...
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