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Add NIL register and simplify more BxResolve work

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This commit is contained in:
Stanislav Shwartsman 2008-03-29 09:34:35 +00:00
parent b745be68ef
commit e48b398bee
6 changed files with 70 additions and 100 deletions
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32
bochs/cpu/cpu.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.437 2008-03-25 16:46:39 sshwarts Exp $
// $Id: cpu.h,v 1.438 2008-03-29 09:34:32 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -93,6 +93,10 @@
#define BX_32BIT_REG_EIP BX_GENERAL_REGISTERS
#define BX_64BIT_REG_RIP BX_GENERAL_REGISTERS
#define BX_16BIT_REG_NIL (BX_GENERAL_REGISTERS+1)
#define BX_32BIT_REG_NIL (BX_GENERAL_REGISTERS+1)
#define BX_64BIT_REG_NIL (BX_GENERAL_REGISTERS+1)
#if defined(NEED_CPU_REG_SHORTCUTS)
/* WARNING:
@ -725,16 +729,18 @@ public: // for now...
cpuid_function_t cpuid_ext_function[MAX_EXT_CPUID_FUNCTION];
// General register set
// eax: accumulator
// ebx: base
// ecx: count
// edx: data
// ebp: base pointer
// esi: source index
// edi: destination index
// rax: accumulator
// rbx: base
// rcx: count
// rdx: data
// rbp: base pointer
// rsi: source index
// rdi: destination index
// esp: stack pointer
// eip: instruction pointer
bx_gen_reg_t gen_reg[BX_GENERAL_REGISTERS+1];
// r8..r15 x86-64 extended registers
// rip: instruction pointer
// nil: null register
bx_gen_reg_t gen_reg[BX_GENERAL_REGISTERS+2];
/* 31|30|29|28| 27|26|25|24| 23|22|21|20| 19|18|17|16
* ==|==|=====| ==|==|==|==| ==|==|==|==| ==|==|==|==
@ -2757,17 +2763,13 @@ public: // for now...
BX_SMF void BxResolve16Rm6(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void BxResolve16Rm7(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void BxResolve32Disp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void BxResolve32Base(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void BxResolve32BaseIndex(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void BxResolve32DispIndex(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#if BX_SUPPORT_X86_64
BX_SMF void BxResolve64Disp(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void BxResolve64Base(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void BxResolve64BaseIndex(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void BxResolve64DispIndex(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif // #if BX_SUPPORT_X86_64
#endif
// <TAG-CLASS-CPU-END>
#if BX_DEBUGGER

53
bochs/cpu/fetchdecode.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.cc,v 1.172 2008-03-22 21:29:39 sshwarts Exp $
// $Id: fetchdecode.cc,v 1.173 2008-03-29 09:34:33 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -2598,26 +2598,25 @@ fetch_b1:
i->setModRM(b2);
i->metaData.metaData1 = rm;
i->setSibBase(rm); // initialize with rm to use BxResolve32Base
i->metaData.metaData5 = nnn;
// initialize displ32 with zero to include cases with no diplacement
i->modRMForm.displ32u = 0;
if (mod == 0xc0) { // mod == 11b
i->assertModC0();
goto modrm_done;
}
i->setSibBase(rm); // initialize with rm to use BxResolve32Base
// initialize displ32 with zero to include cases with no diplacement
i->modRMForm.displ32u = 0;
if (i->as32L()) {
// 32-bit addressing modes; note that mod==11b handled above
if (rm != 4) { // no s-i-b byte
i->ResolveModrm = &BX_CPU_C::BxResolve32Base;
if (mod == 0x00) { // mod == 00b
if (BX_NULL_SEG_REG(i->seg()))
i->setSeg(BX_SEG_REG_DS);
if (BX_NULL_SEG_REG(i->seg())) i->setSeg(BX_SEG_REG_DS);
if (rm == 5) {
i->ResolveModrm = &BX_CPU_C::BxResolve32Disp;
i->setSibBase(BX_64BIT_REG_NIL);
get_32bit_displ:
if ((ilen+3) < remain) {
i->modRMForm.displ32u = FetchDWORD(iptr);
@ -2668,10 +2667,7 @@ get_8bit_displ:
if (BX_NULL_SEG_REG(i->seg()))
i->setSeg(sreg_mod0_base32[base]);
if (base == 0x05) {
if (index == 4)
i->ResolveModrm = &BX_CPU_C::BxResolve32Disp;
else
i->ResolveModrm = &BX_CPU_C::BxResolve32DispIndex;
i->setSibBase(BX_64BIT_REG_NIL);
goto get_32bit_displ;
}
// mod==00b, rm==4, base!=5
@ -2687,8 +2683,8 @@ get_8bit_displ:
}
else {
// 16-bit addressing modes, mod==11b handled above
i->ResolveModrm = Resolve16Rm[rm];
if (mod == 0x00) { // mod == 00b
i->ResolveModrm = Resolve16Rm[rm];
if (BX_NULL_SEG_REG(i->seg()))
i->setSeg(sreg_mod00_rm16[rm]);
if (rm == 0x06) {
@ -2704,7 +2700,6 @@ get_16bit_displ:
}
goto modrm_done;
}
i->ResolveModrm = Resolve16Rm[rm];
if (BX_NULL_SEG_REG(i->seg()))
i->setSeg(sreg_mod01or10_rm16[rm]);
if (mod == 0x40) { // mod == 01b
@ -2740,31 +2735,31 @@ modrm_done:
switch(Group) {
case BxGroupN:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn]);
break;
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn]);
break;
case BxRMGroup:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[rm]);
break;
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[rm]);
break;
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
case Bx3ByteOp:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[b3]);
break;
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[b3]);
break;
#endif
case BxPrefixSSE:
/* For SSE opcodes look into another 4 entries table
/* For SSE opcodes look into another 4 entries table
with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3) */
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix]);
break;
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix]);
break;
#if BX_SUPPORT_FPU
case BxFPEscape:
{
int index = (b1-0xD8)*64 + (0x3f & b2);
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[index]);
}
break;
{
int index = (b1-0xD8)*64 + (0x3f & b2);
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[index]);
}
break;
#endif
default:
BX_PANIC(("fetchdecode: Unknown opcode group"));
BX_PANIC(("fetchdecode: Unknown opcode group"));
}
/* get additional attributes from group table */

50
bochs/cpu/fetchdecode64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode64.cc,v 1.179 2008-03-22 21:29:39 sshwarts Exp $
// $Id: fetchdecode64.cc,v 1.180 2008-03-29 09:34:34 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -3534,17 +3534,17 @@ fetch_b1:
i->setModRM(b2);
i->metaData.metaData1 = rm;
i->setSibBase(rm); // initialize with rm to use BxResolve32Base
i->metaData.metaData5 = nnn;
// initialize displ32 with zero to include cases with no diplacement
i->modRMForm.displ32u = 0;
if (mod == 0xc0) { // mod == 11b
i->assertModC0();
goto modrm_done;
}
i->setSibBase(rm); // initialize with rm to use BxResolve32Base
// initialize displ32 with zero to include cases with no diplacement
i->modRMForm.displ32u = 0;
if (i->as64L()) {
// 64-bit addressing modes; note that mod==11b handled above
if ((rm & 0x7) != 4) { // no s-i-b byte
@ -3604,10 +3604,7 @@ get_8bit_displ:
if (BX_NULL_SEG_REG(i->seg()))
i->setSeg(sreg_mod0_base32[base]);
if ((base & 0x7) == 5) {
if (index == 4)
i->ResolveModrm = &BX_CPU_C::BxResolve64Disp;
else
i->ResolveModrm = &BX_CPU_C::BxResolve64DispIndex;
i->setSibBase(BX_64BIT_REG_NIL);
goto get_32bit_displ;
}
// mod==00b, rm==4, base!=5
@ -3665,10 +3662,7 @@ get_8bit_displ:
if (BX_NULL_SEG_REG(i->seg()))
i->setSeg(sreg_mod0_base32[base]);
if ((base & 0x7) == 5) {
if (index == 4)
i->ResolveModrm = &BX_CPU_C::BxResolve32Disp;
else
i->ResolveModrm = &BX_CPU_C::BxResolve32DispIndex;
i->setSibBase(BX_32BIT_REG_NIL);
goto get_32bit_displ;
}
// mod==00b, rm==4, base!=5
@ -3703,29 +3697,29 @@ modrm_done:
switch(Group) {
case BxGroupN:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn & 0x7]);
break;
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn & 0x7]);
break;
case BxRMGroup:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[rm & 0x7]);
break;
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[rm & 0x7]);
break;
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
case Bx3ByteOp:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[b3]);
break;
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[b3]);
break;
#endif
case BxPrefixSSE:
/* For SSE opcodes look into another 4 entries table
/* For SSE opcodes look into another 4 entries table
with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3) */
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix]);
break;
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix]);
break;
case BxFPEscape:
{
int index = (b1-0xD8)*64 + (0x3f & b2);
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[index]);
}
break;
{
int index = (b1-0xD8)*64 + (0x3f & b2);
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[index]);
}
break;
default:
BX_PANIC(("fetchdecode: Unknown opcode group"));
BX_PANIC(("fetchdecode: Unknown opcode group"));
}
/* get additional attributes from group table */

5
bochs/cpu/init.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: init.cc,v 1.156 2008-03-24 22:13:04 sshwarts Exp $
// $Id: init.cc,v 1.157 2008-03-29 09:34:35 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -713,6 +713,9 @@ void BX_CPU_C::reset(unsigned source)
ESP = 0;
#endif
// initialize NIL register
BX_WRITE_32BIT_REGZ(BX_32BIT_REG_NIL, 0);
// status and control flags register set
BX_CPU_THIS_PTR setEFlags(0x2); // Bit1 is always set

14
bochs/cpu/resolve32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: resolve32.cc,v 1.16 2008-01-29 17:13:09 sshwarts Exp $
// $Id: resolve32.cc,v 1.17 2008-03-29 09:34:35 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -30,24 +30,12 @@
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
void BX_CPP_AttrRegparmN(1)
BX_CPU_C::BxResolve32Disp(bxInstruction_c *i)
{
RMAddr(i) = i->displ32u();
}
void BX_CPP_AttrRegparmN(1)
BX_CPU_C::BxResolve32Base(bxInstruction_c *i)
{
RMAddr(i) = BX_READ_32BIT_REG(i->sibBase()) + i->displ32u();
}
void BX_CPP_AttrRegparmN(1)
BX_CPU_C::BxResolve32DispIndex(bxInstruction_c *i)
{
RMAddr(i) = i->displ32u() + (BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale());
}
void BX_CPP_AttrRegparmN(1)
BX_CPU_C::BxResolve32BaseIndex(bxInstruction_c *i)
{

16
bochs/cpu/resolve64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: resolve64.cc,v 1.18 2008-02-15 19:03:54 sshwarts Exp $
// $Id: resolve64.cc,v 1.19 2008-03-29 09:34:35 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -32,18 +32,6 @@
#if BX_SUPPORT_X86_64
void BX_CPP_AttrRegparmN(1)
BX_CPU_C::BxResolve64DispIndex(bxInstruction_c *i)
{
RMAddr(i) = (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u();
}
void BX_CPP_AttrRegparmN(1)
BX_CPU_C::BxResolve64Disp(bxInstruction_c *i)
{
RMAddr(i) = (Bit32s) i->displ32u();
}
void BX_CPP_AttrRegparmN(1)
BX_CPU_C::BxResolve64Base(bxInstruction_c *i)
{
@ -56,4 +44,4 @@ BX_CPU_C::BxResolve64BaseIndex(bxInstruction_c *i)
RMAddr(i) = BX_READ_64BIT_REG(i->sibBase()) + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u();
}
#endif /* if BX_SUPPORT_X86_64 */
#endif