Removed BX_USE_TLB - TLB is always used, only Guest2HostTLB is optional feature
Use Guest2HostTLB in prefetch code for IFETCHES - speedup above 3%
This commit is contained in:
Stanislav Shwartsman
parent
c8d8eb8e52
commit
90f1973bef
@ -108,31 +108,6 @@
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#define SIGALRM 14
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#endif
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// Paging Options:
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// ---------------
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// Support Paging mechanism.
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// 0 = don't support paging at all (DOS & Minix don't require it)
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// 1 = support paging. (Most other OS's require paging)
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// Use Translation Lookaside Buffer (TLB) for caching
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// paging translations. This will make paging mode
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// more efficient. If you're OS doesn't use paging,
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// then you won't need either.
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// 1 = Use a TLB for effiency
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// 0 = don't use a TLB, walk the page tables for every access
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// BX_TLB_SIZE: Number of entries in TLB
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// BX_TLB_INDEX_OF(lpf): This macro is passed the linear page frame
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// (top 20 bits of the linear address. It must map these bits to
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// one of the TLB cache slots, given the size of BX_TLB_SIZE.
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// There will be a many-to-one mapping to each TLB cache slot.
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// When there are collisions, the old entry is overwritten with
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// one for the newest access.
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#define BX_USE_TLB 1
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#define BX_TLB_SIZE 1024
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#define BX_TLB_MASK ((BX_TLB_SIZE-1) << 12)
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#define BX_TLB_INDEX_OF(lpf, len) ((((unsigned)(lpf) + (len)) & BX_TLB_MASK) >> 12)
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// Compile in support for DMA & FLOPPY IO. You'll need this
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// if you plan to use the floppy drive emulation. But if
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// you're environment doesn't require it, you can change
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.215 2008-03-31 18:53:08 sshwarts Exp $
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// $Id: cpu.cc,v 1.216 2008-04-05 20:41:00 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -635,20 +635,36 @@ void BX_CPU_C::prefetch(void)
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}
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}
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if (BX_CPU_THIS_PTR cr0.get_PG()) {
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// aligned block guaranteed to be all in one page, same A20 address
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pAddr = itranslate_linear(laddr, CPL);
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pAddr = A20ADDR(pAddr);
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}
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else
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{
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pAddr = A20ADDR(laddr);
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bx_address lpf = LPFOf(laddr);
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unsigned TLB_index = BX_TLB_INDEX_OF(lpf, 0);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
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Bit8u *fetchPtr = 0;
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if (tlbEntry->lpf == lpf) { // always have permissions for CODE access
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pAddr = A20ADDR(tlbEntry->ppf | PAGE_OFFSET(laddr));
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#if BX_SupportGuest2HostTLB
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fetchPtr = (Bit8u*) (tlbEntry->hostPageAddr);
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#endif
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}
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else {
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if (BX_CPU_THIS_PTR cr0.get_PG()) {
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pAddr = translate_linear(laddr, CPL, BX_READ, CODE_ACCESS);
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pAddr = A20ADDR(pAddr);
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}
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else {
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pAddr = A20ADDR(laddr);
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}
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}
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BX_CPU_THIS_PTR pAddrA20Page = pAddr & 0xfffff000;
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BX_CPU_THIS_PTR eipFetchPtr =
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BX_CPU_THIS_PTR mem->getHostMemAddr(BX_CPU_THIS,
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BX_CPU_THIS_PTR pAddrA20Page, BX_READ, CODE_ACCESS);
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if (fetchPtr) {
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BX_CPU_THIS_PTR eipFetchPtr = fetchPtr;
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}
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else {
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BX_CPU_THIS_PTR eipFetchPtr = BX_CPU_THIS_PTR mem->getHostMemAddr(BX_CPU_THIS,
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BX_CPU_THIS_PTR pAddrA20Page, BX_READ, CODE_ACCESS);
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}
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// Sanity checks
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if (! BX_CPU_THIS_PTR eipFetchPtr) {
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.447 2008-04-05 19:08:01 sshwarts Exp $
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// $Id: cpu.h,v 1.448 2008-04-05 20:41:00 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -588,7 +588,18 @@ struct cpuid_function_t {
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#include "icache.h"
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#endif
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#if BX_USE_TLB
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// BX_TLB_SIZE: Number of entries in TLB
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// BX_TLB_INDEX_OF(lpf): This macro is passed the linear page frame
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// (top 20 bits of the linear address. It must map these bits to
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// one of the TLB cache slots, given the size of BX_TLB_SIZE.
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// There will be a many-to-one mapping to each TLB cache slot.
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// When there are collisions, the old entry is overwritten with
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// one for the newest access.
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#define BX_TLB_SIZE 1024
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#define BX_TLB_MASK ((BX_TLB_SIZE-1) << 12)
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#define BX_TLB_INDEX_OF(lpf, len) ((((unsigned)(lpf) + (len)) & BX_TLB_MASK) >> 12)
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typedef bx_ptr_equiv_t bx_hostpageaddr_t;
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typedef struct {
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@ -597,7 +608,6 @@ typedef struct {
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Bit32u accessBits; // Page Table Address for updating A & D bits
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bx_hostpageaddr_t hostPageAddr;
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} bx_TLB_entry;
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#endif
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// general purpose register
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#if BX_SUPPORT_X86_64
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@ -899,8 +909,6 @@ public: // for now...
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Bit8u trace;
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// for paging
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#if BX_USE_TLB
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struct {
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bx_TLB_entry entry[BX_TLB_SIZE] BX_CPP_AlignN(16);
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} TLB;
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@ -912,10 +920,7 @@ public: // for now...
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#define LPF_MASK 0xfffff000
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#endif
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#define LPFOf(laddr) ((laddr) & LPF_MASK)
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#endif // #if BX_USE_TLB
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#define LPFOf(laddr) ((laddr) & LPF_MASK)
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#define PAGE_OFFSET(laddr) ((Bit32u)(laddr) & 0xfff)
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// An instruction cache. Each entry should be exactly 32 bytes, and
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@ -2899,10 +2904,7 @@ public: // for now...
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// linear address for translate_linear expected to be canonical !
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BX_SMF bx_phy_address translate_linear(bx_address laddr, unsigned curr_pl, unsigned rw, unsigned access_type);
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BX_SMF BX_CPP_INLINE bx_phy_address itranslate_linear(bx_address laddr, unsigned curr_pl)
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{
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return translate_linear(laddr, curr_pl, BX_READ, CODE_ACCESS);
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}
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BX_SMF BX_CPP_INLINE bx_phy_address dtranslate_linear(bx_address laddr, unsigned curr_pl, unsigned rw)
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{
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return translate_linear(laddr, curr_pl, rw, DATA_ACCESS);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: init.cc,v 1.161 2008-04-03 17:56:59 sshwarts Exp $
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// $Id: init.cc,v 1.162 2008-04-05 20:41:00 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -937,9 +937,7 @@ void BX_CPU_C::reset(unsigned source)
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BX_CPU_THIS_PTR EXT = 0;
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#if BX_USE_TLB
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TLB_init();
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#endif
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// invalidate the prefetch queue
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BX_CPU_THIS_PTR eipPageBias = 0;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: paging.cc,v 1.115 2008-03-31 20:56:27 sshwarts Exp $
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// $Id: paging.cc,v 1.116 2008-04-05 20:41:00 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -472,10 +472,8 @@ void BX_CPU_C::TLB_init(void)
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{
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unsigned i, wp, us_combined, rw_combined, us_current, rw_current;
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#if BX_USE_TLB
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for (i=0; i<BX_TLB_SIZE; i++)
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BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY;
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#endif
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//
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// Setup privilege check matrix.
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@ -519,7 +517,6 @@ void BX_CPU_C::TLB_flush(bx_bool invalidateGlobal)
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InstrTLB_Increment(tlbNonGlobalFlushes);
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#endif
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#if BX_USE_TLB
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for (unsigned i=0; i<BX_TLB_SIZE; i++) {
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// To be conscious of the native cache line usage, only
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// write to (invalidate) entries which need it.
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@ -534,16 +531,13 @@ void BX_CPU_C::TLB_flush(bx_bool invalidateGlobal)
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}
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}
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}
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#endif // #if BX_USE_TLB
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}
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void BX_CPU_C::TLB_invlpg(bx_address laddr)
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{
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#if BX_USE_TLB
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unsigned TLB_index = BX_TLB_INDEX_OF(laddr, 0);
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BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = BX_INVALID_TLB_ENTRY;
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InstrTLB_Increment(tlbEntryFlushes); // A TLB entry flush occurred.
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#endif
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::INVLPG(bxInstruction_c* i)
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@ -556,14 +550,11 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::INVLPG(bxInstruction_c* i)
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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#if BX_USE_TLB
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BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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bx_address laddr = BX_CPU_THIS_PTR get_segment_base(i->seg()) + RMAddr(i);
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BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_INVLPG, laddr);
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TLB_invlpg(laddr);
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InstrTLB_Increment(tlbEntryInvlpg);
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#endif
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#else
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// not supported on < 486
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BX_INFO(("INVLPG: required i486, use --enable-cpu=4 option"));
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@ -617,7 +608,6 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
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bx_bool isWrite = (rw >= BX_WRITE); // write or r-m-w
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unsigned pl = (curr_pl == 3);
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#if BX_USE_TLB
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InstrTLB_Increment(tlbLookups);
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InstrTLB_Stats();
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@ -625,7 +615,8 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
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unsigned TLB_index = BX_TLB_INDEX_OF(lpf, 0);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
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if (tlbEntry->lpf == lpf)
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// already looked up TLB for code access
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if (access_type != CODE_ACCESS && tlbEntry->lpf == lpf)
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{
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paddress = tlbEntry->ppf | poffset;
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accessBits = tlbEntry->accessBits;
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@ -640,7 +631,6 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
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}
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InstrTLB_Increment(tlbMisses);
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#endif
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#if BX_SUPPORT_PAE
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if (BX_CPU_THIS_PTR cr4.get_PAE())
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@ -968,10 +958,8 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
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// Calculate physical memory address and fill in TLB cache entry
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paddress = ppf | poffset;
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#if BX_USE_TLB
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BX_CPU_THIS_PTR TLB.entry[TLB_index].lpf = lpf;
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BX_CPU_THIS_PTR TLB.entry[TLB_index].ppf = ppf;
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#endif
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// b3: Write User OK
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// b2: Write Sys OK
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@ -1001,7 +989,6 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
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accessBits |= combined_access & TLB_GlobalPage; // Global bit
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#endif
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#if BX_USE_TLB
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#if BX_SupportGuest2HostTLB
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// Attempt to get a host pointer to this physical page. Put that
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// pointer in the TLB cache. Note if the request is vetoed, NULL
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@ -1016,7 +1003,6 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
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}
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#endif
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BX_CPU_THIS_PTR TLB.entry[TLB_index].accessBits = accessBits;
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#endif
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return paddress;
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}
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@ -1033,7 +1019,6 @@ bx_bool BX_CPU_C::dbg_xlate_linear2phy(bx_address laddr, bx_phy_address *phy)
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bx_phy_address paddress;
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// see if page is in the TLB first
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#if BX_USE_TLB
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bx_address lpf = LPFOf(laddr);
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unsigned TLB_index = BX_TLB_INDEX_OF(lpf, 0);
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bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
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@ -1043,7 +1028,6 @@ bx_bool BX_CPU_C::dbg_xlate_linear2phy(bx_address laddr, bx_phy_address *phy)
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*phy = paddress;
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return 1;
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}
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#endif
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bx_phy_address pt_address = BX_CPU_THIS_PTR cr3_masked;
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bx_address offset_mask = 0xfff;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: main.cc,v 1.376 2008-03-29 21:01:23 sshwarts Exp $
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// $Id: main.cc,v 1.377 2008-04-05 20:41:00 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -977,7 +977,6 @@ void bx_init_hardware()
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BX_INFO((" APIC support: %s",BX_SUPPORT_APIC?"yes":"no"));
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BX_INFO(("CPU configuration"));
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BX_INFO((" level: %d",BX_CPU_LEVEL));
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BX_INFO((" TLB enabled: %s",BX_USE_TLB?"yes":"no"));
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#if BX_SUPPORT_SMP
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BX_INFO((" SMP support: yes, quantum=%d", SIM->get_param_num(BXPN_SMP_QUANTUM)->get()));
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#else
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