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1. Fixed bug in FSUB instruction 

2. Fixed bug

[ 989478 ] I-Cache and undefined Instruktions

The L4 microkernel uses an undefined instruction to
trap for a special requests into the kernel (LOCK NOP).
The handler fixes this up and gives the user a special
code page with syscall stubs. If you're not using the
I-Cache optimization everthing works find on bochs. But
if you enable the I-Cache (--enable-icache), then the
undefined opcode exception is thrown only once for ever
virtual address it occurs. See the demodisk of the
L4KA::pistachio
(http://www.l4ka.org/projects/pistachio/download.php).
In this case the pingpong benchmark of this demo is of
interest. Everything runs fine until the program tries
to spawn a new task for its measurements. This new task
shares the code of the creating program. But the new
task stops executing at the undefined instruction
explained above and no exception is thrown.
This commit is contained in:
Stanislav Shwartsman 2004-07-29 20:15:19 +00:00
parent f1a0f56d55
commit f9bd2b74be
15 changed files with 92 additions and 106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
bochs/config.h.in
View File

@ -729,10 +729,10 @@ typedef
#define BX_SupportRepeatSpeedups 0
#define BX_SupportGlobalPages 0
#define BX_SupportPAE 0
#define BX_SupportICache 0
#define BX_SupportHostAsms 0
#define BX_SupportHostAsmsFpu 0
#define BX_SUPPORT_ICACHE 0
// if 1, don't do gpf on MSRs that we don't implement
#define BX_IGNORE_BAD_MSR 0

4
bochs/configure vendored
View File

@ -33013,12 +33013,12 @@ fi
if test "$speedup_iCache" = 1; then
cat >>confdefs.h <<\_ACEOF
#define BX_SupportICache 1
#define BX_SUPPORT_ICACHE 1
_ACEOF
else
cat >>confdefs.h <<\_ACEOF
#define BX_SupportICache 0
#define BX_SUPPORT_ICACHE 0
_ACEOF
fi

6
bochs/configure.in
View File

@ -2,7 +2,7 @@ dnl // Process this file with autoconf to produce a configure script.
AC_PREREQ(2.50)
AC_INIT(bochs.h)
AC_REVISION([[$Id: configure.in,v 1.256 2004-07-15 19:57:31 sshwarts Exp $]])
AC_REVISION([[$Id: configure.in,v 1.257 2004-07-29 20:15:16 sshwarts Exp $]])
AC_CONFIG_HEADER(config.h)
AC_CONFIG_HEADER(ltdlconf.h)
@ -1293,9 +1293,9 @@ else
fi
if test "$speedup_iCache" = 1; then
AC_DEFINE(BX_SupportICache, 1)
AC_DEFINE(BX_SUPPORT_ICACHE, 1)
else
AC_DEFINE(BX_SupportICache, 0)
AC_DEFINE(BX_SUPPORT_ICACHE, 0)
fi
if test "$speedup_host_specific_asms" = 1; then

50
bochs/cpu/access.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: access.cc,v 1.43 2004-06-18 14:11:06 sshwarts Exp $
// $Id: access.cc,v 1.44 2004-07-29 20:15:17 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -324,19 +324,19 @@ accessOK:
hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf>>12];
#endif
// Current write access has privilege.
if (hostPageAddr
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
&& (*pageStamp & ICacheWriteStampMask)
#endif
) {
*hostAddr = *data;
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
(*pageStamp)--;
#endif
return;
@ -391,19 +391,19 @@ accessOK:
hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf>>12];
#endif
// Current write access has privilege.
if (hostPageAddr
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
&& (*pageStamp & ICacheWriteStampMask)
#endif
) {
WriteHostWordToLittleEndian(hostAddr, *data);
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
(*pageStamp)--;
#endif
return;
@ -459,19 +459,19 @@ accessOK:
hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf>>12];
#endif
// Current write access has privilege.
if (hostPageAddr
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
&& (*pageStamp & ICacheWriteStampMask)
#endif
) {
WriteHostDWordToLittleEndian(hostAddr, *data);
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
(*pageStamp)--;
#endif
return;
@ -691,20 +691,20 @@ accessOK:
hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf>>12];
#endif
// Current write access has privilege.
if (hostPageAddr
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
&& (*pageStamp & ICacheWriteStampMask)
#endif
) {
*data = *hostAddr;
BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr;
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
(*pageStamp)--;
#endif
return;
@ -762,20 +762,20 @@ accessOK:
hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf>>12];
#endif
// Current write access has privilege.
if (hostPageAddr
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
&& (*pageStamp & ICacheWriteStampMask)
#endif
) {
ReadHostWordFromLittleEndian(hostAddr, *data);
BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr;
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
(*pageStamp)--;
#endif
return;
@ -831,20 +831,20 @@ accessOK:
hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf>>12];
#endif
// Current write access has privilege.
if (hostPageAddr
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
&& (*pageStamp & ICacheWriteStampMask)
#endif
) {
ReadHostDWordFromLittleEndian(hostAddr, *data);
BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr;
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
(*pageStamp)--;
#endif
return;
@ -977,19 +977,19 @@ accessOK:
hostAddr = (Bit64u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf>>12];
#endif
// Current write access has privilege.
if (hostPageAddr
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
&& (*pageStamp & ICacheWriteStampMask)
#endif
) {
WriteHostQWordToLittleEndian(hostAddr, *data);
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
(*pageStamp)--;
#endif
return;
@ -1134,20 +1134,20 @@ accessOK:
hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
BX_CPU_THIS_PTR TLB.entry[tlbIndex].ppf>>12];
#endif
// Current write access has privilege.
if (hostPageAddr
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
&& (*pageStamp & ICacheWriteStampMask)
#endif
) {
ReadHostQWordFromLittleEndian(hostAddr, *data);
BX_CPU_THIS_PTR address_xlation.pages = (bx_ptr_equiv_t) hostAddr;
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
(*pageStamp)--;
#endif
return;

91
bochs/cpu/cpu.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.84 2004-06-19 15:20:07 sshwarts Exp $
// $Id: cpu.cc,v 1.85 2004-07-29 20:15:17 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -188,29 +188,27 @@ printf("CPU_LOOP %d\n", bx_guard.special_unwind_stack);
#endif
{
bx_address eipBiased;
Bit8u *fetchPtr;
bx_address eipBiased = RIP + BX_CPU_THIS_PTR eipPageBias;
eipBiased = RIP + BX_CPU_THIS_PTR eipPageBias;
if ( eipBiased >= BX_CPU_THIS_PTR eipPageWindowSize ) {
if (eipBiased >= BX_CPU_THIS_PTR eipPageWindowSize) {
prefetch();
eipBiased = RIP + BX_CPU_THIS_PTR eipPageBias;
}
}
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
unsigned iCacheHash;
Bit32u pAddr, pageWriteStamp;
pAddr = BX_CPU_THIS_PTR pAddrA20Page + eipBiased;
iCacheHash = BX_CPU_THIS_PTR iCache.hash( pAddr );
iCacheHash = BX_CPU_THIS_PTR iCache.hash(pAddr);
i = & BX_CPU_THIS_PTR iCache.entry[iCacheHash].i;
pageWriteStamp = BX_CPU_THIS_PTR iCache.pageWriteStampTable[pAddr>>12];
if ( (BX_CPU_THIS_PTR iCache.entry[iCacheHash].pAddr == pAddr) &&
(BX_CPU_THIS_PTR iCache.entry[iCacheHash].writeStamp == pageWriteStamp) ) {
if ((BX_CPU_THIS_PTR iCache.entry[iCacheHash].pAddr == pAddr) &&
(BX_CPU_THIS_PTR iCache.entry[iCacheHash].writeStamp == pageWriteStamp))
{
// iCache hit. Instruction is already decoded and stored in
// the instruction cache.
BxExecutePtr_tR resolveModRM = i->ResolveModrm; // Get as soon as possible for speculation.
@ -228,67 +226,63 @@ printf("CPU_LOOP %d\n", bx_guard.special_unwind_stack);
else
#endif
{
// iCache miss. No validated instruction with matching fetch parameters
// is in the iCache. Or we're not compiling iCache support in, in which
// iCache miss. No validated instruction with matching fetch parameters
// is in the iCache. Or we're not compiling iCache support in, in which
// case we always have an iCache miss. :^)
bx_address remainingInPage;
unsigned maxFetch;
Bit32u fetchModeMask;
remainingInPage = (BX_CPU_THIS_PTR eipPageWindowSize - eipBiased);
maxFetch = 15;
if (remainingInPage < 15)
maxFetch = remainingInPage;
unsigned maxFetch = 15;
if (remainingInPage < 15) maxFetch = remainingInPage;
fetchPtr = BX_CPU_THIS_PTR eipFetchPtr + eipBiased;
#if BX_SupportICache
// In the case where the page is marked ICacheWriteStampInvalid, all
// counter bits will be high, being eqivalent to ICacheWriteStampMax.
// In the case where the page is marked as possibly having associated
// iCache entries, we need to leave the counter as-is, unless we're
// willing to dump all iCache entries which can hash to this page.
// Therefore, in either case, we can keep the counter as-is and
// replace the fetch mode bits.
fetchModeMask = BX_CPU_THIS_PTR iCache.fetchModeMask;
pageWriteStamp &= 0x1fffffff; // Clear out old fetch mode bits.
pageWriteStamp |= fetchModeMask; // Add in new ones.
BX_CPU_THIS_PTR iCache.pageWriteStampTable[pAddr>>12] = pageWriteStamp;
BX_CPU_THIS_PTR iCache.entry[iCacheHash].pAddr = pAddr;
BX_CPU_THIS_PTR iCache.entry[iCacheHash].writeStamp = pageWriteStamp;
#if BX_SUPPORT_ICACHE
// The entry will be marked valid if fetchdecode will succeed
BX_CPU_THIS_PTR iCache.entry[iCacheHash].writeStamp =
ICacheWriteStampInvalid;
#endif
#if BX_SUPPORT_X86_64
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
ret = fetchDecode64(fetchPtr, i, maxFetch);
}
else
#endif
{
ret = fetchDecode(fetchPtr, i, maxFetch);
}
BxExecutePtr_tR resolveModRM = i->ResolveModrm; // Get function pointers early.
if (ret==0) {
#if BX_SupportICache
// Invalidate entry, since fetch-decode failed with partial updates
// to the i-> structure.
BX_CPU_THIS_PTR iCache.entry[iCacheHash].writeStamp =
ICacheWriteStampInvalid;
i = &iStorage;
#if BX_SUPPORT_ICACHE
BX_INFO((" ... fetchdecode returned zero, leave entry invalid"));
i = &iStorage; // Leave entry invalid
#endif
boundaryFetch(i);
resolveModRM = i->ResolveModrm; // Get function pointers as early
resolveModRM = i->ResolveModrm;
}
#if BX_INSTRUMENTATION
else
{
#if BX_SUPPORT_ICACHE
// In the case where the page is marked ICacheWriteStampInvalid, all
// counter bits will be high, being eqivalent to ICacheWriteStampMax.
// In the case where the page is marked as possibly having associated
// iCache entries, we need to leave the counter as-is, unless we're
// willing to dump all iCache entries which can hash to this page.
// Therefore, in either case, we can keep the counter as-is and
// replace the fetch mode bits.
Bit32u fetchModeMask = BX_CPU_THIS_PTR iCache.fetchModeMask;
pageWriteStamp &= 0x1fffffff; // Clear out old fetch mode bits.
pageWriteStamp |= fetchModeMask; // Add in new ones.
BX_CPU_THIS_PTR iCache.pageWriteStampTable[pAddr>>12] = pageWriteStamp;
BX_CPU_THIS_PTR iCache.entry[iCacheHash].pAddr = pAddr;
BX_CPU_THIS_PTR iCache.entry[iCacheHash].writeStamp = pageWriteStamp;
#endif
#if BX_INSTRUMENTATION
// An instruction was either fetched, or found in the iCache.
BX_INSTR_OPCODE(BX_CPU_ID, fetchPtr, i->ilen(),
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b);
}
#endif
}
execute = i->execute; // fetch as soon as possible for speculation.
if (resolveModRM) {
if (resolveModRM){
BX_CPU_CALL_METHODR(resolveModRM, (i));
}
}
@ -791,7 +785,7 @@ BX_CPU_C::prefetch(void)
}
}
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
Bit32u pageWriteStamp;
Bit32u fetchModeMask;
Bit32u phyPageIndex;
@ -882,7 +876,6 @@ BX_CPU_C::ask (int level, const char *prefix, const char *fmt, va_list ap)
vsprintf (buf1, fmt, ap);
printf ("%s %s\n", prefix, buf1);
trap_debugger(1);
//this->logfunctions::ask(level,prefix,fmt,ap);
}
void

8
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.166 2004-07-15 19:45:33 sshwarts Exp $
// $Id: cpu.h,v 1.167 2004-07-29 20:15:17 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -996,7 +996,7 @@ typedef void (BX_CPU_C::*BxExecutePtr_tR)(bxInstruction_c *) BX_CPP_AttrRegparmN
// ========== iCache =============================================
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
#define BxICacheEntries (32 * 1024) // Must be a power of 2.
// bit31: 1=CS is 32/64-bit, 0=CS is 16-bit.
@ -1422,7 +1422,7 @@ union {
// An instruction cache. Each entry should be exactly 32 bytes, and
// this structure should be aligned on a 32-byte boundary to be friendly
// with the host cache lines.
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
bxICache_c iCache BX_CPP_AlignN(32);
#endif
@ -2961,7 +2961,7 @@ union {
};
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
BX_CPP_INLINE void bxICache_c::decWriteStamp(BX_CPU_C *cpu, Bit32u a20Addr) {
// Increment page write stamp, so iCache entries with older stamps

6
bochs/cpu/init.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: init.cc,v 1.52 2004-06-18 14:11:06 sshwarts Exp $
// $Id: init.cc,v 1.53 2004-07-29 20:15:18 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -168,7 +168,7 @@ cpu_param_handler (bx_param_c *param, int set, Bit64s val)
void BX_CPU_C::init(BX_MEM_C *addrspace)
{
BX_DEBUG(( "Init $Id: init.cc,v 1.52 2004-06-18 14:11:06 sshwarts Exp $"));
BX_DEBUG(( "Init $Id: init.cc,v 1.53 2004-07-29 20:15:18 sshwarts Exp $"));
// BX_CPU_C constructor
BX_CPU_THIS_PTR set_INTR (0);
#if BX_SUPPORT_APIC
@ -459,7 +459,7 @@ void BX_CPU_C::init(BX_MEM_C *addrspace)
}
#endif
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
iCache.alloc(mem->len);
iCache.fetchModeMask = 0; // KPL: fixme!!!
#endif

8
bochs/cpu/segment_ctrl_pro.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: segment_ctrl_pro.cc,v 1.27 2004-05-10 21:05:50 sshwarts Exp $
// $Id: segment_ctrl_pro.cc,v 1.28 2004-07-29 20:15:18 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -51,7 +51,7 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
seg->cache.segment = 1; /* regular segment */
if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS]) {
seg->cache.u.segment.executable = 1; /* code segment */
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR iCache.fetchModeMask =
BX_CPU_THIS_PTR iCache.createFetchModeMask(BX_CPU_THIS);
#endif
@ -334,7 +334,7 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0;
#endif
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR iCache.fetchModeMask =
BX_CPU_THIS_PTR iCache.createFetchModeMask(BX_CPU_THIS);
#endif
@ -555,7 +555,7 @@ BX_CPU_C::load_cs(bx_selector_t *selector, bx_descriptor_t *descriptor,
}
#endif
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR iCache.fetchModeMask =
BX_CPU_THIS_PTR iCache.createFetchModeMask(BX_CPU_THIS);
#endif

2
bochs/fpu/fpu_load_store.cc
View File

@ -29,9 +29,7 @@
extern float_status_t FPU_pre_exception_handling(Bit16u control_word);
#if BX_SUPPORT_FPU
#include "softfloatx80.h"
#endif
void BX_CPU_C::FLD_STi(bxInstruction_c *i)
{

3
bochs/fpu/fpu_misc.cc
View File

@ -27,10 +27,7 @@
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_FPU
#include "softfloatx80.h"
#endif
/* D9 C8 */
void BX_CPU_C::FXCH_STi(bxInstruction_c *i)

2
bochs/fpu/fpu_trans.cc
View File

@ -27,10 +27,8 @@
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_FPU
#include "softfloatx80.h"
#include "softfloat-specialize.h"
#endif
extern float_status_t FPU_pre_exception_handling(Bit16u control_word);

2
bochs/fpu/softfloat.cc
View File

@ -2387,7 +2387,7 @@ static floatx80 addFloatx80Sigs(floatx80 a, floatx80 b, int zSign, float_status_
if (bExp == 0x7FFF) {
if ((Bit64u) (bSig<<1)) return propagateFloatx80NaN(a, b, status);
if (aSig && (aExp == 0)) float_raise(status, float_flag_denormal);
return b;
return packFloatx80(zSign, 0x7FFF, BX_CONST64(0x8000000000000000));
}
if (aExp == 0) {
if (aSig == 0) {

4
bochs/main.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: main.cc,v 1.278 2004-06-19 15:20:06 sshwarts Exp $
// $Id: main.cc,v 1.279 2004-07-29 20:15:16 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -831,7 +831,7 @@ bx_init_hardware()
BX_INFO(("Optimization configuration"));
BX_INFO((" Guest2HostTLB support: %s",BX_SupportGuest2HostTLB?"yes":"no"));
BX_INFO((" RepeatSpeedups support: %s",BX_SupportRepeatSpeedups?"yes":"no"));
BX_INFO((" Icache support: %s",BX_SupportICache?"yes":"no"));
BX_INFO((" Icache support: %s",BX_SUPPORT_ICACHE?"yes":"no"));
BX_INFO((" Host Asm support: %s",BX_SupportHostAsms?"yes":"no"));
// set up memory and CPU objects

4
bochs/memory/memory.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: memory.cc,v 1.31 2004-07-18 19:40:51 vruppert Exp $
// $Id: memory.cc,v 1.32 2004-07-29 20:15:18 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -65,7 +65,7 @@ BX_MEM_C::writePhysicalPage(BX_CPU_C *cpu, Bit32u addr, unsigned len, void *data
}
#endif
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
if (a20addr < BX_MEM_THIS len)
cpu->iCache.decWriteStamp(cpu, a20addr);
#endif

6
bochs/memory/misc_mem.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: misc_mem.cc,v 1.44 2004-06-19 15:20:15 sshwarts Exp $
// $Id: misc_mem.cc,v 1.45 2004-07-29 20:15:19 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -131,7 +131,7 @@ BX_MEM_C::~BX_MEM_C(void)
void
BX_MEM_C::init_memory(int memsize)
{
BX_DEBUG(("Init $Id: misc_mem.cc,v 1.44 2004-06-19 15:20:15 sshwarts Exp $"));
BX_DEBUG(("Init $Id: misc_mem.cc,v 1.45 2004-07-29 20:15:19 sshwarts Exp $"));
// you can pass 0 if memory has been allocated already through
// the constructor, or the desired size of memory if it hasn't
// BX_INFO(("%.2fMB", (float)(BX_MEM_THIS megabytes) ));
@ -396,7 +396,7 @@ BX_MEM_C::getHostMemAddr(BX_CPU_C *cpu, Bit32u a20Addr, unsigned op)
return(NULL); // Vetoed! ROMs
#endif
#if BX_SupportICache
#if BX_SUPPORT_ICACHE
cpu->iCache.decWriteStamp(cpu, a20Addr);
#endif