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Trace cache optimization merged

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This commit is contained in:
Stanislav Shwartsman 2007-12-09 18:36:05 +00:00
parent ee465a7714
commit adda3befd3
12 changed files with 1034 additions and 746 deletions
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13
bochs/CHANGES
View File

@ -1,14 +1,14 @@
-------------------------------------------------------------------------
Changes for coming 2.3.6 release:
Brief summary :
+ More than 20% emulation speedup vs Bochs 2.3.5 release!
+ More than 25% emulation speedup vs Bochs 2.3.5 release!
- Thanks to Darek Mihocka (http://www.emulators.com)
for providing patches and ideas that made the
speedup possible!
+ Up to 40% speedup vs Bochs 2.3.5 release with trace cache optimization!
- Lots of bugfixes in cpu emulation
- Bochs bechmarking support
- Added emulation of Intel SSE4.2 instruction set
@ -28,6 +28,10 @@ Detailed change log :
- Removed hostasm optimizations, after Bochs rebenchmarking it was found
that the feature bringing no speedup or even sometimes slowes down
the emulation !
- Merged trace cache optimization patch, the trace cache optimization
is enabled by default when configure with --enable-all-optimizations
option, to disable trace cache optimization configure with
--disable-trace-cache
- Many minor bugfixes in CPU emulation (both ia32 and x86-64)
- Bochs Internal Debugger and Disassember
@ -57,8 +61,6 @@ Detailed change log :
--cpu-level >= 4 (like in real hardware)
- SF patches applied
[1791000] 15h 8600h is reading the wrong stack frame by Sebastian
[1841421] pic: keep slave_pic.INT and master_pic.IRQ_in bit 2 in sync by Russ Cox
[1841420] give segment numbers in exception logs by Russ Cox
[1801696] Allow Intel builds on Mac OS X
@ -79,6 +81,9 @@ Detailed change log :
[1799877] Fix for parallel build (make -j2) by Robert Millan
- these S.F. bugs were closed
[1837354] website bug: View the Source link broken
[1801268] Reset from real mode no longer working
[1843250] Using forward slashes gives invalid filename
[1823446] BIOS bug, local APIC #0 not detected
[1801285] Niclist.exe broken
[1364472] breakpoints sometimes don't work

5
bochs/bochs.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: bochs.h,v 1.216 2007-11-22 17:30:40 sshwarts Exp $
// $Id: bochs.h,v 1.217 2007-12-09 18:36:00 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -200,8 +200,11 @@ void print_tree(bx_param_c *node, int level = 0);
#if BX_SUPPORT_SMP
# define BX_TICK1_IF_SINGLE_PROCESSOR() \
if (BX_SMP_PROCESSORS == 1) BX_TICK1()
# define BX_TICKN_IF_SINGLE_PROCESSOR() \
if (BX_SMP_PROCESSORS == 1) BX_TICKN(n)
#else
# define BX_TICK1_IF_SINGLE_PROCESSOR() BX_TICK1()
# define BX_TICKN_IF_SINGLE_PROCESSOR() BX_TICKN(n)
#endif
// you can't use static member functions on the CPU, if there are going

5
bochs/config.h.in
View File

@ -730,6 +730,11 @@ typedef
#define BX_SupportHostAsms 0
#define BX_SUPPORT_ICACHE 0
#define BX_SUPPORT_TRACE_CACHE 0
#if (BX_SUPPORT_TRACE_CACHE && BX_SUPPORT_ICACHE==0)
#error Trace cache optimizatin cannot be compiled without iCache!
#endif
// if 1, don't do gpf on MSRs that we don't implement
#define BX_IGNORE_BAD_MSR 0

107
bochs/configure vendored
View File

@ -1,5 +1,5 @@
#! /bin/sh
# From configure.in Id: configure.in,v 1.352 2007/11/26 20:38:39 sshwarts Exp .
# From configure.in Id: configure.in,v 1.353 2007/12/01 16:45:15 sshwarts Exp .
# Guess values for system-dependent variables and create Makefiles.
# Generated by GNU Autoconf 2.60.
#
@ -1554,6 +1554,7 @@ Optional Features:
--enable-mtrr support for MTRRs
--enable-guest2host-tlb support guest to host addr TLB for speed
--enable-repeat-speedups support repeated IO and mem copy speedups
--enable-trace-cache support instruction trace cache
--enable-icache support instruction cache
--enable-fast-function-calls support for fast function calls (gcc on x86 only)
--enable-host-specific-asms support for host specific inline assembly
@ -4503,7 +4504,7 @@ ia64-*-hpux*)
;;
*-*-irix6*)
# Find out which ABI we are using.
echo '#line 4506 "configure"' > conftest.$ac_ext
echo '#line 4507 "configure"' > conftest.$ac_ext
if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
(eval $ac_compile) 2>&5
ac_status=$?
@ -6869,11 +6870,11 @@ else
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:6872: $lt_compile\"" >&5)
(eval echo "\"\$as_me:6873: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
echo "$as_me:6876: \$? = $ac_status" >&5
echo "$as_me:6877: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings
@ -7102,11 +7103,11 @@ else
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:7105: $lt_compile\"" >&5)
(eval echo "\"\$as_me:7106: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
echo "$as_me:7109: \$? = $ac_status" >&5
echo "$as_me:7110: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings
@ -7169,11 +7170,11 @@ else
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:7172: $lt_compile\"" >&5)
(eval echo "\"\$as_me:7173: $lt_compile\"" >&5)
(eval "$lt_compile" 2>out/conftest.err)
ac_status=$?
cat out/conftest.err >&5
echo "$as_me:7176: \$? = $ac_status" >&5
echo "$as_me:7177: \$? = $ac_status" >&5
if (exit $ac_status) && test -s out/conftest2.$ac_objext
then
# The compiler can only warn and ignore the option if not recognized
@ -9442,7 +9443,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
#line 9445 "configure"
#line 9446 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@ -9540,7 +9541,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
#line 9543 "configure"
#line 9544 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@ -11747,11 +11748,11 @@ else
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:11750: $lt_compile\"" >&5)
(eval echo "\"\$as_me:11751: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
echo "$as_me:11754: \$? = $ac_status" >&5
echo "$as_me:11755: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings
@ -11814,11 +11815,11 @@ else
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:11817: $lt_compile\"" >&5)
(eval echo "\"\$as_me:11818: $lt_compile\"" >&5)
(eval "$lt_compile" 2>out/conftest.err)
ac_status=$?
cat out/conftest.err >&5
echo "$as_me:11821: \$? = $ac_status" >&5
echo "$as_me:11822: \$? = $ac_status" >&5
if (exit $ac_status) && test -s out/conftest2.$ac_objext
then
# The compiler can only warn and ignore the option if not recognized
@ -13236,7 +13237,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
#line 13239 "configure"
#line 13240 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@ -13334,7 +13335,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
#line 13337 "configure"
#line 13338 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@ -14157,11 +14158,11 @@ else
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:14160: $lt_compile\"" >&5)
(eval echo "\"\$as_me:14161: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
echo "$as_me:14164: \$? = $ac_status" >&5
echo "$as_me:14165: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings
@ -14224,11 +14225,11 @@ else
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:14227: $lt_compile\"" >&5)
(eval echo "\"\$as_me:14228: $lt_compile\"" >&5)
(eval "$lt_compile" 2>out/conftest.err)
ac_status=$?
cat out/conftest.err >&5
echo "$as_me:14231: \$? = $ac_status" >&5
echo "$as_me:14232: \$? = $ac_status" >&5
if (exit $ac_status) && test -s out/conftest2.$ac_objext
then
# The compiler can only warn and ignore the option if not recognized
@ -16267,11 +16268,11 @@ else
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:16270: $lt_compile\"" >&5)
(eval echo "\"\$as_me:16271: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
echo "$as_me:16274: \$? = $ac_status" >&5
echo "$as_me:16275: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings
@ -16500,11 +16501,11 @@ else
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:16503: $lt_compile\"" >&5)
(eval echo "\"\$as_me:16504: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
echo "$as_me:16507: \$? = $ac_status" >&5
echo "$as_me:16508: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings
@ -16567,11 +16568,11 @@ else
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:16570: $lt_compile\"" >&5)
(eval echo "\"\$as_me:16571: $lt_compile\"" >&5)
(eval "$lt_compile" 2>out/conftest.err)
ac_status=$?
cat out/conftest.err >&5
echo "$as_me:16574: \$? = $ac_status" >&5
echo "$as_me:16575: \$? = $ac_status" >&5
if (exit $ac_status) && test -s out/conftest2.$ac_objext
then
# The compiler can only warn and ignore the option if not recognized
@ -18840,7 +18841,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
#line 18843 "configure"
#line 18844 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@ -18938,7 +18939,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
#line 18941 "configure"
#line 18942 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@ -21319,7 +21320,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
#line 21322 "configure"
#line 21323 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@ -37926,6 +37927,35 @@ echo "${ECHO_T}no" >&6; }
fi
{ echo "$as_me:$LINENO: checking for instruction trace cache support" >&5
echo $ECHO_N "checking for instruction trace cache support... $ECHO_C" >&6; }
# Check whether --enable-trace-cache was given.
if test "${enable_trace_cache+set}" = set; then
enableval=$enable_trace_cache; if test "$enableval" = yes; then
{ echo "$as_me:$LINENO: result: yes" >&5
echo "${ECHO_T}yes" >&6; }
speedup_TraceCache=1
else
{ echo "$as_me:$LINENO: result: no" >&5
echo "${ECHO_T}no" >&6; }
speedup_TraceCache=0
fi
else
if test "$speedup_TraceCache " = 1; then
{ echo "$as_me:$LINENO: result: yes" >&5
echo "${ECHO_T}yes" >&6; }
speedup_TraceCache=1
else
{ echo "$as_me:$LINENO: result: no" >&5
echo "${ECHO_T}no" >&6; }
speedup_TraceCache=0
fi
fi
{ echo "$as_me:$LINENO: checking for instruction cache support" >&5
echo $ECHO_N "checking for instruction cache support... $ECHO_C" >&6; }
# Check whether --enable-icache was given.
@ -38324,9 +38354,16 @@ if test "$speedups_all" = 1; then
speedup_guest2host_tlb=1
speedup_repeat=1
speedup_iCache=1
speedup_TraceCache=1
speedup_fastcall=1
fi
if test "$speedup_iCache" = 0 -a "$speedup_TraceCache" = 1; then
{ { echo "$as_me:$LINENO: error: iCache is required to compile with trace cache optimization" >&5
echo "$as_me: error: iCache is required to compile with trace cache optimization" >&2;}
{ (exit 1); exit 1; }; }
fi
if test "$speedup_guest2host_tlb" = 1; then
cat >>confdefs.h <<\_ACEOF
#define BX_SupportGuest2HostTLB 1
@ -38387,6 +38424,18 @@ _ACEOF
fi
if test "$speedup_TraceCache" = 1; then
cat >>confdefs.h <<\_ACEOF
#define BX_SUPPORT_TRACE_CACHE 1
_ACEOF
else
cat >>confdefs.h <<\_ACEOF
#define BX_SUPPORT_TRACE_CACHE 0
_ACEOF
fi
READLINE_LIB=""
rl_without_curses_ok=no

34
bochs/configure.in
View File

@ -2,7 +2,7 @@ dnl // Process this file with autoconf to produce a configure script.
AC_PREREQ(2.50)
AC_INIT(bochs.h)
AC_REVISION([[$Id: configure.in,v 1.353 2007-12-01 16:45:15 sshwarts Exp $]])
AC_REVISION([[$Id: configure.in,v 1.354 2007-12-09 18:36:00 sshwarts Exp $]])
AC_CONFIG_HEADER(config.h)
AC_CONFIG_HEADER(ltdlconf.h)
@ -1001,6 +1001,27 @@ AC_ARG_ENABLE(repeat-speedups,
]
)
AC_MSG_CHECKING(for instruction trace cache support)
AC_ARG_ENABLE(trace-cache,
[ --enable-trace-cache support instruction trace cache],
[if test "$enableval" = yes; then
AC_MSG_RESULT(yes)
speedup_TraceCache=1
else
AC_MSG_RESULT(no)
speedup_TraceCache=0
fi],
[
if test "$speedup_TraceCache " = 1; then
AC_MSG_RESULT(yes)
speedup_TraceCache=1
else
AC_MSG_RESULT(no)
speedup_TraceCache=0
fi
]
)
AC_MSG_CHECKING(for instruction cache support)
AC_ARG_ENABLE(icache,
[ --enable-icache support instruction cache],
@ -1254,9 +1275,14 @@ if test "$speedups_all" = 1; then
speedup_guest2host_tlb=1
speedup_repeat=1
speedup_iCache=1
speedup_TraceCache=1
speedup_fastcall=1
fi
if test "$speedup_iCache" = 0 -a "$speedup_TraceCache" = 1; then
AC_MSG_ERROR([iCache is required to compile with trace cache optimization])
fi
if test "$speedup_guest2host_tlb" = 1; then
AC_DEFINE(BX_SupportGuest2HostTLB, 1)
else
@ -1287,6 +1313,12 @@ else
AC_DEFINE(BX_FAST_FUNC_CALL, 0)
fi
if test "$speedup_TraceCache" = 1; then
AC_DEFINE(BX_SUPPORT_TRACE_CACHE, 1)
else
AC_DEFINE(BX_SUPPORT_TRACE_CACHE, 0)
fi
READLINE_LIB=""
rl_without_curses_ok=no

202
bochs/cpu/cpu.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.187 2007-12-08 09:26:13 sshwarts Exp $
// $Id: cpu.cc,v 1.188 2007-12-09 18:36:03 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -62,16 +62,20 @@ void flushICaches(void)
#if InstrumentICACHE
static Bit32u iCacheLookups=0;
static Bit32u iCacheMisses=0;
static Bit32u iCacheMergeTraces=0;
static Bit32u iCacheLength[BX_MAX_TRACE_LENGTH+1];
#define InstrICache_StatsMask 0xfffffff
#define InstrICache_Stats() {\
if ((iCacheLookups & InstrICache_StatsMask) == 0) { \
BX_INFO(("ICACHE lookups: %u, misses: %u, hit rate = %6.2f%% ", \
BX_INFO(("ICACHE lookups: %u, misses: %u, merges: %u, hit rate = %6.2f%% ", \
(unsigned) iCacheLookups, \
(unsigned) iCacheMisses, \
(unsigned) iCacheMergeTraces, \
(iCacheLookups-iCacheMisses) * 100.0 / iCacheLookups)); \
iCacheLookups = iCacheMisses = 0; \
iCacheLookups = iCacheMisses = iCacheMergeTraces = 0; \
for (int i=0;i<=BX_MAX_TRACE_LENGTH;i++) iCacheLength[i] = 0; \
} \
}
#define InstrICache_Increment(v) (v)++
@ -89,7 +93,118 @@ static Bit32u iCacheMisses=0;
#define RCX ECX
#endif
BX_CPP_INLINE bxInstruction_c* BX_CPU_C::fetchInstruction(bxInstruction_c *iStorage, bx_address eipBiased)
#if BX_SUPPORT_TRACE_CACHE
bxICacheEntry_c* BX_CPU_C::fetchInstructionTrace(bxInstruction_c *iStorage, bx_address eipBiased)
{
bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrA20Page + eipBiased;
unsigned iCacheHash = BX_CPU_THIS_PTR iCache.hash(pAddr);
bxICacheEntry_c *trace = &(BX_CPU_THIS_PTR iCache.entry[iCacheHash]);
Bit32u pageWriteStamp = *(BX_CPU_THIS_PTR currPageWriteStampPtr);
InstrICache_Increment(iCacheLookups);
InstrICache_Stats();
if ((trace->pAddr == pAddr) &&
(trace->writeStamp == pageWriteStamp))
{
return trace; // We are lucky - trace cache hit !
}
// We are not so lucky, but let's be optimistic - try to build trace from
// incoming instruction bytes stream !
trace->pAddr = pAddr;
trace->writeStamp = ICacheWriteStampInvalid;
trace->ilen = 0;
InstrICache_Increment(iCacheMisses);
bx_address remainingInPage = (BX_CPU_THIS_PTR eipPageWindowSize - eipBiased);
unsigned maxFetch = 15;
if (remainingInPage < 15) maxFetch = remainingInPage;
Bit8u *fetchPtr = BX_CPU_THIS_PTR eipFetchPtr + eipBiased;
unsigned ret;
// We could include in trace maximum BX_MAX_TRACE_LEN instructions
unsigned max_length = BX_MAX_TRACE_LENGTH;
if ((pageWriteStamp & ICacheWriteStampMask) != ICacheWriteStampStart)
max_length = 1; // seems like the entry has SMC ping-pong problem
bxInstruction_c *i = trace->i;
for (unsigned len=0;len<max_length;len++)
{
#if BX_SUPPORT_X86_64
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
ret = fetchDecode64(fetchPtr, i, maxFetch);
else
#endif
ret = fetchDecode32(fetchPtr, i, maxFetch);
if (ret==0) {
// Fetching instruction on segment/page boundary
if (len > 0) {
// The trace is already valid, it has several instructions inside,
// in this case just drop the boundary instruction and stop
// tracing.
break;
}
// First instruction is boundary fetch, return iStorage and leave
// the trace cache entry invalid (do not cache the instruction)
boundaryFetch(fetchPtr, remainingInPage, iStorage);
return 0;
}
// add instruction to the trace ...
unsigned iLen = i->ilen();
trace->writeStamp = pageWriteStamp;
trace->ilen++;
if (i->getStopTraceAttr()) break;
// ... and continue to the next instruction
remainingInPage -= iLen;
if (remainingInPage == 0) break;
if (remainingInPage < 15) maxFetch = remainingInPage;
fetchPtr += iLen;
pAddr += iLen;
i++;
if (mergeTraces(trace, i, pAddr)) break;
}
InstrICache_Increment(iCacheLength[trace->ilen-1]);
return trace;
}
bx_bool BX_CPU_C::mergeTraces(bxICacheEntry_c *trace, bxInstruction_c *i, bx_phy_address pAddr)
{
bxICacheEntry_c *e = &(BX_CPU_THIS_PTR iCache.entry[BX_CPU_THIS_PTR iCache.hash(pAddr)]);
if ((e->pAddr == pAddr) && (e->writeStamp == trace->writeStamp))
{
// We are lucky - another trace hit !
InstrICache_Increment(iCacheMergeTraces);
// determine max amount of instruction to take from another trace
unsigned max_length = e->ilen;
if (max_length + trace->ilen > BX_MAX_TRACE_LENGTH)
max_length = BX_MAX_TRACE_LENGTH - trace->ilen;
if(max_length == 0) return 0;
memcpy(i, e->i, sizeof(bxInstruction_c)*max_length);
trace->ilen += max_length;
BX_ASSERT(trace->ilen <= BX_MAX_TRACE_LENGTH);
return 1;
}
return 0;
}
#else
bxInstruction_c* BX_CPU_C::fetchInstruction(bxInstruction_c *iStorage, bx_address eipBiased)
{
unsigned ret;
bxInstruction_c *i = iStorage;
@ -161,6 +276,8 @@ BX_CPP_INLINE bxInstruction_c* BX_CPU_C::fetchInstruction(bxInstruction_c *iStor
return i;
}
#endif
// The CHECK_MAX_INSTRUCTIONS macro allows cpu_loop to execute a few
// instructions and then return so that the other processors have a chance to
// run. This is used by bochs internal debugger or when simulating
@ -241,47 +358,68 @@ void BX_CPU_C::cpu_loop(Bit32u max_instr_count)
eipBiased = RIP + BX_CPU_THIS_PTR eipPageBias;
}
// fetch and decode next instruction
#if BX_SUPPORT_TRACE_CACHE == 0
// fetch and decode single instruction
bxInstruction_c *i = fetchInstruction(&iStorage, eipBiased);
#else
unsigned n, length = 1;
bxInstruction_c *i = &iStorage;
bxICacheEntry_c *trace = fetchInstructionTrace(&iStorage, eipBiased);
if (trace) {
i = trace->i; // execute from first instruction in trace
length = trace->ilen;
}
Bit32u currPageWriteStamp = *(BX_CPU_THIS_PTR currPageWriteStampPtr);
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
for (n=0; n < length; n++, i++) {
#endif
// An instruction will have been fetched using either the normal case,
// or the boundary fetch (across pages), by this point.
BX_INSTR_FETCH_DECODE_COMPLETED(BX_CPU_ID, i);
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
// An instruction will have been fetched using either the normal case,
// or the boundary fetch (across pages), by this point.
BX_INSTR_FETCH_DECODE_COMPLETED(BX_CPU_ID, i);
#if BX_DEBUGGER || BX_EXTERNAL_DEBUGGER || BX_GDBSTUB
if (dbg_instruction_prolog()) return;
if (dbg_instruction_prolog()) return;
#endif
#if BX_DISASM
if (BX_CPU_THIS_PTR trace) {
// print the instruction that is about to be executed
if (BX_CPU_THIS_PTR trace) {
// print the instruction that is about to be executed
#if BX_DEBUGGER
bx_dbg_disassemble_current(BX_CPU_ID, 1); // only one cpu, print time stamp
bx_dbg_disassemble_current(BX_CPU_ID, 1); // only one cpu, print time stamp
#else
debug_disasm_instruction(BX_CPU_THIS_PTR prev_rip);
debug_disasm_instruction(BX_CPU_THIS_PTR prev_rip);
#endif
}
#endif
// decoding instruction compeleted -> continue with execution
BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID, i);
RIP += i->ilen();
BX_CPU_CALL_METHOD(i->execute, (i)); // might iterate repeat instruction
BX_CPU_THIS_PTR prev_rip = RIP; // commit new RIP
BX_INSTR_AFTER_EXECUTION(BX_CPU_ID, i);
BX_TICK1_IF_SINGLE_PROCESSOR();
// inform instrumentation about new instruction
BX_INSTR_NEW_INSTRUCTION(BX_CPU_ID);
// note instructions generating exceptions never reach this point
#if BX_DEBUGGER || BX_EXTERNAL_DEBUGGER || BX_GDBSTUB
if (dbg_instruction_epilog()) return;
#endif
CHECK_MAX_INSTRUCTIONS(max_instr_count);
#if BX_SUPPORT_TRACE_CACHE
if (currPageWriteStamp != *(BX_CPU_THIS_PTR currPageWriteStampPtr))
break; // probably it is self modifying code ...
if (BX_CPU_THIS_PTR async_event) break;
}
#endif
// decoding instruction compeleted -> continue with execution
BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID, i);
RIP += i->ilen();
BX_CPU_CALL_METHOD(i->execute, (i)); // might iterate repeat instruction
BX_CPU_THIS_PTR prev_rip = RIP; // commit new RIP
BX_INSTR_AFTER_EXECUTION(BX_CPU_ID, i);
BX_TICK1_IF_SINGLE_PROCESSOR();
// inform instrumentation about new instruction
BX_INSTR_NEW_INSTRUCTION(BX_CPU_ID);
// note instructions generating exceptions never reach this point
#if BX_DEBUGGER || BX_EXTERNAL_DEBUGGER || BX_GDBSTUB
if (dbg_instruction_epilog()) return;
#endif
CHECK_MAX_INSTRUCTIONS(max_instr_count);
} // while (1)
}

31
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.385 2007-12-09 17:40:23 sshwarts Exp $
// $Id: cpu.h,v 1.386 2007-12-09 18:36:04 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -612,9 +612,10 @@ public:
void (BX_CPU_C::*execute)(bxInstruction_c *);
#endif
// 31..28 (unused)
// 27..19 b1 (9bits of opcode; 1byte-op=0..255, 2byte-op=256..511
// 31..29 (unused)
// 28..20 b1 (9bits of opcode; 1byte-op=0..255, 2byte-op=256..511
// (leave this one on top so no mask is needed)
// 19..19 stop trace (used with trace cache)
// 18..18 mod==c0 (modrm)
// 17..16 repUsed (0=none, 2=0xF2, 3=0xF3).
Bit16u metaInfo3;
@ -841,13 +842,22 @@ public:
metaInfo3 = (metaInfo3 & ~3) | (value);
}
#if BX_SUPPORT_TRACE_CACHE
BX_CPP_INLINE void setStopTraceAttr(void) {
metaInfo3 |= (1<<3);
}
BX_CPP_INLINE unsigned getStopTraceAttr(void) {
return metaInfo3 & (1<<3);
}
#endif
// Note this is the highest field, and thus needs no masking.
// DON'T PUT ANY FIELDS HIGHER THAN THIS ONE WITHOUT ADDING A MASK.
BX_CPP_INLINE unsigned b1(void) {
return metaInfo3 >> 3;
return metaInfo3 >> 4;
}
BX_CPP_INLINE void setB1(unsigned b1) {
metaInfo3 = (metaInfo3 & ~(0x1ff << 3)) | ((b1 & 0x1ff) << 3);
metaInfo3 = (metaInfo3 & ~(0x1ff << 4)) | ((b1 & 0x1ff) << 4);
}
};
// <TAG-CLASS-INSTRUCTION-END>
@ -2926,7 +2936,12 @@ public: // for now...
#if BX_SUPPORT_X86_64
BX_SMF unsigned fetchDecode64(Bit8u *, bxInstruction_c *, unsigned);
#endif
#if BX_SUPPORT_TRACE_CACHE
BX_SMF bxICacheEntry_c* fetchInstructionTrace(bxInstruction_c *, bx_address);
BX_SMF bx_bool mergeTraces(bxICacheEntry_c *trace, bxInstruction_c *i, bx_phy_address pAddr);
#else
BX_SMF bxInstruction_c* fetchInstruction(bxInstruction_c *, bx_address);
#endif
BX_SMF void UndefinedOpcode(bxInstruction_c *);
BX_SMF void BxError(bxInstruction_c *i);
@ -3727,6 +3742,12 @@ IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
#define BxLockable 0x0100 // bit 8
#define Bx3ByteOpcode 0x0200 // bit 9
#if BX_SUPPORT_TRACE_CACHE
#define BxTraceEnd 0x2000 // bit 13
#else
#define BxTraceEnd 0
#endif
#define BxGroup1 BxGroupN
#define BxGroup2 BxGroupN
#define BxGroup3 BxGroupN

567
bochs/cpu/fetchdecode.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.cc,v 1.145 2007-12-07 09:38:41 sshwarts Exp $
// $Id: fetchdecode.cc,v 1.146 2007-12-09 18:36:04 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -207,7 +207,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 14 /wr */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
/* 15 /wr */ { BxImmediate_Iv, &BX_CPU_C::ADC_AXIw },
/* 16 /wr */ { 0, &BX_CPU_C::PUSH16_SS },
/* 17 /wr */ { 0, &BX_CPU_C::POP16_SS },
/* 17 /wr */ { BxTraceEnd, &BX_CPU_C::POP16_SS }, // async_event = 1
/* 18 /wr */ { 0, &BX_CPU_C::SBB_EbGbR },
/* 19 /wr */ { 0, &BX_CPU_C::SBB_EwGwR },
/* 1A /wr */ { 0, &BX_CPU_C::SBB_GbEbR },
@ -296,22 +296,22 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 6D /wr */ { 0, &BX_CPU_C::REP_INSW_YwDX },
/* 6E /wr */ { 0, &BX_CPU_C::REP_OUTSB_DXXb },
/* 6F /wr */ { 0, &BX_CPU_C::REP_OUTSW_DXXw },
/* 70 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JO_Jw },
/* 71 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JNO_Jw },
/* 72 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JB_Jw },
/* 73 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JNB_Jw },
/* 74 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JZ_Jw },
/* 75 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JNZ_Jw },
/* 76 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JBE_Jw },
/* 77 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JNBE_Jw },
/* 78 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JS_Jw },
/* 79 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JNS_Jw },
/* 7A /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JP_Jw },
/* 7B /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JNP_Jw },
/* 7C /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JL_Jw },
/* 7D /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JNL_Jw },
/* 7E /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JLE_Jw },
/* 7F /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JNLE_Jw },
/* 70 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JO_Jw },
/* 71 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNO_Jw },
/* 72 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JB_Jw },
/* 73 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNB_Jw },
/* 74 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JZ_Jw },
/* 75 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNZ_Jw },
/* 76 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JBE_Jw },
/* 77 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNBE_Jw },
/* 78 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JS_Jw },
/* 79 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNS_Jw },
/* 7A /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JP_Jw },
/* 7B /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNP_Jw },
/* 7C /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JL_Jw },
/* 7D /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNL_Jw },
/* 7E /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JLE_Jw },
/* 7F /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNLE_Jw },
/* 80 /wr */ { BxGroup1 | BxImmediate_Ib, NULL, BxOpcodeInfoG1EbIbR },
/* 81 /wr */ { BxGroup1 | BxImmediate_Iv, NULL, BxOpcodeInfoG1EwR },
/* 82 /wr */ { BxGroup1 | BxImmediate_Ib, NULL, BxOpcodeInfoG1EbIbR },
@ -326,7 +326,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 8B /wr */ { 0, &BX_CPU_C::MOV_GwEwR },
/* 8C /wr */ { 0, &BX_CPU_C::MOV_EwSw },
/* 8D /wr */ { 0, &BX_CPU_C::BxError }, // LEA
/* 8E /wr */ { 0, &BX_CPU_C::MOV_SwEw },
/* 8E /wr */ { BxTraceEnd, &BX_CPU_C::MOV_SwEw }, // async_event = 1
/* 8F /wr */ { 0, &BX_CPU_C::POP_EwR },
/* 90 /wr */ { 0, &BX_CPU_C::NOP },
/* 91 /wr */ { 0, &BX_CPU_C::XCHG_RXAX },
@ -338,7 +338,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 97 /wr */ { 0, &BX_CPU_C::XCHG_RXAX },
/* 98 /wr */ { 0, &BX_CPU_C::CBW },
/* 99 /wr */ { 0, &BX_CPU_C::CWD },
/* 9A /wr */ { BxImmediate_IvIw, &BX_CPU_C::CALL16_Ap },
/* 9A /wr */ { BxImmediate_IvIw | BxTraceEnd, &BX_CPU_C::CALL16_Ap },
/* 9B /wr */ { 0, &BX_CPU_C::FWAIT },
/* 9C /wr */ { 0, &BX_CPU_C::PUSHF_Fw },
/* 9D /wr */ { 0, &BX_CPU_C::POPF_Fw },
@ -378,20 +378,20 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* BF /wr */ { BxImmediate_Iv, &BX_CPU_C::MOV_RXIw },
/* C0 /wr */ { BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfoG2Eb },
/* C1 /wr */ { BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfoG2Ew },
/* C2 /wr */ { BxImmediate_Iw, &BX_CPU_C::RETnear16_Iw },
/* C3 /wr */ { 0, &BX_CPU_C::RETnear16 },
/* C2 /wr */ { BxImmediate_Iw | BxTraceEnd, &BX_CPU_C::RETnear16_Iw },
/* C3 /wr */ { BxTraceEnd, &BX_CPU_C::RETnear16 },
/* C4 /wr */ { 0, &BX_CPU_C::BxError }, // LES
/* C5 /wr */ { 0, &BX_CPU_C::BxError }, // LDS
/* C6 /wr */ { BxImmediate_Ib, &BX_CPU_C::MOV_EbIbR },
/* C7 /wr */ { BxImmediate_Iv, &BX_CPU_C::MOV_EwIwR },
/* C8 /wr */ { BxImmediate_IwIb, &BX_CPU_C::ENTER16_IwIb },
/* C9 /wr */ { 0, &BX_CPU_C::LEAVE },
/* CA /wr */ { BxImmediate_Iw, &BX_CPU_C::RETfar16_Iw },
/* CB /wr */ { 0, &BX_CPU_C::RETfar16 },
/* CC /wr */ { 0, &BX_CPU_C::INT3 },
/* CD /wr */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
/* CE /wr */ { 0, &BX_CPU_C::INTO },
/* CF /wr */ { 0, &BX_CPU_C::IRET16 },
/* CA /wr */ { BxImmediate_Iw | BxTraceEnd, &BX_CPU_C::RETfar16_Iw },
/* CB /wr */ { BxTraceEnd, &BX_CPU_C::RETfar16 },
/* CC /wr */ { BxTraceEnd, &BX_CPU_C::INT3 },
/* CD /wr */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
/* CE /wr */ { BxTraceEnd, &BX_CPU_C::INTO },
/* CF /wr */ { BxTraceEnd, &BX_CPU_C::IRET16 },
/* D0 /wr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
/* D1 /wr */ { BxGroup2, NULL, BxOpcodeInfoG2Ew },
/* D2 /wr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
@ -420,27 +420,27 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* DE /wr */ { 0, &BX_CPU_C::FPU_ESC },
/* DF /wr */ { 0, &BX_CPU_C::FPU_ESC },
#endif
/* E0 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPNE_Jb },
/* E1 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPE_Jb },
/* E2 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::LOOP_Jb },
/* E3 /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JCXZ_Jb },
/* E0 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::LOOPNE_Jb },
/* E1 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::LOOPE_Jb },
/* E2 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::LOOP_Jb },
/* E3 /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JCXZ_Jb },
/* E4 /wr */ { BxImmediate_Ib, &BX_CPU_C::IN_ALIb },
/* E5 /wr */ { BxImmediate_Ib, &BX_CPU_C::IN_AXIb },
/* E6 /wr */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbAL },
/* E7 /wr */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbAX },
/* E8 /wr */ { BxImmediate_BrOff16, &BX_CPU_C::CALL_Jw },
/* E9 /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JMP_Jw },
/* EA /wr */ { BxImmediate_IvIw, &BX_CPU_C::JMP_Ap },
/* EB /wr */ { BxImmediate_BrOff8, &BX_CPU_C::JMP_Jw },
/* E8 /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::CALL_Jw },
/* E9 /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JMP_Jw },
/* EA /wr */ { BxImmediate_IvIw | BxTraceEnd, &BX_CPU_C::JMP_Ap },
/* EB /wr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JMP_Jw },
/* EC /wr */ { 0, &BX_CPU_C::IN_ALDX },
/* ED /wr */ { 0, &BX_CPU_C::IN_AXDX },
/* EE /wr */ { 0, &BX_CPU_C::OUT_DXAL },
/* EF /wr */ { 0, &BX_CPU_C::OUT_DXAX },
/* F0 /wr */ { BxPrefix, &BX_CPU_C::BxError }, // LOCK
/* F1 /wr */ { 0, &BX_CPU_C::INT1 },
/* F1 /wr */ { BxTraceEnd, &BX_CPU_C::INT1 },
/* F2 /wr */ { BxPrefix, &BX_CPU_C::BxError }, // REPNE/REPNZ
/* F3 /wr */ { BxPrefix, &BX_CPU_C::BxError }, // REP, REPE/REPZ
/* F4 /wr */ { 0, &BX_CPU_C::HLT },
/* F4 /wr */ { BxTraceEnd, &BX_CPU_C::HLT },
/* F5 /wr */ { 0, &BX_CPU_C::CMC },
/* F6 /wr */ { BxGroup3, NULL, BxOpcodeInfoG3EbR },
/* F7 /wr */ { BxGroup3, NULL, BxOpcodeInfoG3EwR },
@ -459,22 +459,22 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F 03 /wr */ { 0, &BX_CPU_C::LSL_GvEw },
/* 0F 04 /wr */ { 0, &BX_CPU_C::BxError },
#if BX_SUPPORT_X86_64
/* 0F 05 /wr */ { 0, &BX_CPU_C::SYSCALL },
/* 0F 05 /wr */ { BxTraceEnd, &BX_CPU_C::SYSCALL },
#elif BX_CPU_LEVEL == 2
/* 0F 05 /wr */ { 0, &BX_CPU_C::LOADALL },
/* 0F 05 /wr */ { BxTraceEnd, &BX_CPU_C::LOADALL },
#else
/* 0F 05 /wr */ { 0, &BX_CPU_C::BxError },
#endif
/* 0F 06 /wr */ { 0, &BX_CPU_C::CLTS },
#if BX_SUPPORT_X86_64
/* 0F 07 /wr */ { 0, &BX_CPU_C::SYSRET },
/* 0F 07 /wr */ { BxTraceEnd, &BX_CPU_C::SYSRET },
#else
/* 0F 07 /wr */ { 0, &BX_CPU_C::BxError },
#endif
/* 0F 08 /wr */ { 0, &BX_CPU_C::INVD },
/* 0F 09 /wr */ { 0, &BX_CPU_C::WBINVD },
/* 0F 08 /wr */ { BxTraceEnd, &BX_CPU_C::INVD },
/* 0F 09 /wr */ { BxTraceEnd, &BX_CPU_C::WBINVD },
/* 0F 0A /wr */ { 0, &BX_CPU_C::BxError },
/* 0F 0B /wr */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F 0B /wr */ { BxTraceEnd, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F 0C /wr */ { 0, &BX_CPU_C::BxError },
#if BX_SUPPORT_X86_64 || BX_SUPPORT_3DNOW
/* 0F 0D /wr */ { 0, &BX_CPU_C::NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
@ -516,11 +516,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
#endif
/* 0F 20 /wr */ { 0, &BX_CPU_C::MOV_RdCd },
/* 0F 21 /wr */ { 0, &BX_CPU_C::MOV_RdDd },
/* 0F 22 /wr */ { 0, &BX_CPU_C::MOV_CdRd },
/* 0F 23 /wr */ { 0, &BX_CPU_C::MOV_DdRd },
/* 0F 24 /wr */ { 0, &BX_CPU_C::MOV_RdTd },
/* 0F 22 /wr */ { BxTraceEnd, &BX_CPU_C::MOV_CdRd },
/* 0F 23 /wr */ { BxTraceEnd, &BX_CPU_C::MOV_DdRd },
/* 0F 24 /wr */ { BxTraceEnd, &BX_CPU_C::MOV_RdTd }, // not implemented
/* 0F 25 /wr */ { 0, &BX_CPU_C::BxError },
/* 0F 26 /wr */ { 0, &BX_CPU_C::MOV_TdRd },
/* 0F 26 /wr */ { BxTraceEnd, &BX_CPU_C::MOV_TdRd }, // not implemented
/* 0F 27 /wr */ { 0, &BX_CPU_C::BxError },
/* 0F 28 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f29 },
@ -534,8 +534,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F 31 /wr */ { 0, &BX_CPU_C::RDTSC },
/* 0F 32 /wr */ { 0, &BX_CPU_C::RDMSR },
/* 0F 33 /wr */ { 0, &BX_CPU_C::RDPMC },
/* 0F 34 /wr */ { 0, &BX_CPU_C::SYSENTER },
/* 0F 35 /wr */ { 0, &BX_CPU_C::SYSEXIT },
/* 0F 34 /wr */ { BxTraceEnd, &BX_CPU_C::SYSENTER },
/* 0F 35 /wr */ { BxTraceEnd, &BX_CPU_C::SYSEXIT },
/* 0F 36 /wr */ { 0, &BX_CPU_C::BxError },
/* 0F 37 /wr */ { 0, &BX_CPU_C::BxError },
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
@ -618,22 +618,22 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F 7D /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7d },
/* 0F 7E /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7e },
/* 0F 7F /wr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7f },
/* 0F 80 /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JO_Jw },
/* 0F 81 /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JNO_Jw },
/* 0F 82 /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JB_Jw },
/* 0F 83 /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JNB_Jw },
/* 0F 84 /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JZ_Jw },
/* 0F 85 /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JNZ_Jw },
/* 0F 86 /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JBE_Jw },
/* 0F 87 /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JNBE_Jw },
/* 0F 88 /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JS_Jw },
/* 0F 89 /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JNS_Jw },
/* 0F 8A /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JP_Jw },
/* 0F 8B /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JNP_Jw },
/* 0F 8C /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JL_Jw },
/* 0F 8D /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JNL_Jw },
/* 0F 8E /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JLE_Jw },
/* 0F 8F /wr */ { BxImmediate_BrOff16, &BX_CPU_C::JNLE_Jw },
/* 0F 80 /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JO_Jw },
/* 0F 81 /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNO_Jw },
/* 0F 82 /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JB_Jw },
/* 0F 83 /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNB_Jw },
/* 0F 84 /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JZ_Jw },
/* 0F 85 /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNZ_Jw },
/* 0F 86 /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JBE_Jw },
/* 0F 87 /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNBE_Jw },
/* 0F 88 /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JS_Jw },
/* 0F 89 /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNS_Jw },
/* 0F 8A /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JP_Jw },
/* 0F 8B /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNP_Jw },
/* 0F 8C /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JL_Jw },
/* 0F 8D /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNL_Jw },
/* 0F 8E /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JLE_Jw },
/* 0F 8F /wr */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNLE_Jw },
/* 0F 90 /wr */ { 0, &BX_CPU_C::SETO_Eb },
/* 0F 91 /wr */ { 0, &BX_CPU_C::SETNO_Eb },
/* 0F 92 /wr */ { 0, &BX_CPU_C::SETB_Eb },
@ -656,11 +656,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F A3 /wr */ { 0, &BX_CPU_C::BT_EwGwR },
/* 0F A4 /wr */ { BxImmediate_Ib, &BX_CPU_C::SHLD_EwGw },
/* 0F A5 /wr */ { 0, &BX_CPU_C::SHLD_EwGw },
/* 0F A6 /wr */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
/* 0F A7 /wr */ { 0, &BX_CPU_C::CMPXCHG_IBTS },
/* 0F A6 /wr */ { BxTraceEnd, &BX_CPU_C::CMPXCHG_XBTS }, // not implemented
/* 0F A7 /wr */ { BxTraceEnd, &BX_CPU_C::CMPXCHG_IBTS }, // not implemented
/* 0F A8 /wr */ { 0, &BX_CPU_C::PUSH16_GS },
/* 0F A9 /wr */ { 0, &BX_CPU_C::POP16_GS },
/* 0F AA /wr */ { 0, &BX_CPU_C::RSM },
/* 0F AA /wr */ { BxTraceEnd, &BX_CPU_C::RSM },
/* 0F AB /wr */ { 0, &BX_CPU_C::BTS_EwGwR },
/* 0F AC /wr */ { BxImmediate_Ib, &BX_CPU_C::SHRD_EwGw },
/* 0F AD /wr */ { 0, &BX_CPU_C::SHRD_EwGw },
@ -771,7 +771,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 14 /dr */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
/* 15 /dr */ { BxImmediate_Iv, &BX_CPU_C::ADC_EAXId },
/* 16 /dr */ { 0, &BX_CPU_C::PUSH32_SS },
/* 17 /dr */ { 0, &BX_CPU_C::POP32_SS },
/* 17 /dr */ { BxTraceEnd, &BX_CPU_C::POP32_SS }, // async_event = 1
/* 18 /dr */ { 0, &BX_CPU_C::SBB_EbGbR },
/* 19 /dr */ { 0, &BX_CPU_C::SBB_EdGdR },
/* 1A /dr */ { 0, &BX_CPU_C::SBB_GbEbR },
@ -860,22 +860,22 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 6D /dr */ { 0, &BX_CPU_C::REP_INSD_YdDX },
/* 6E /dr */ { 0, &BX_CPU_C::REP_OUTSB_DXXb },
/* 6F /dr */ { 0, &BX_CPU_C::REP_OUTSD_DXXd },
/* 70 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JO_Jd },
/* 71 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JNO_Jd },
/* 72 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JB_Jd },
/* 73 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JNB_Jd },
/* 74 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JZ_Jd },
/* 75 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JNZ_Jd },
/* 76 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JBE_Jd },
/* 77 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JNBE_Jd },
/* 78 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JS_Jd },
/* 79 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JNS_Jd },
/* 7A /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JP_Jd },
/* 7B /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JNP_Jd },
/* 7C /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JL_Jd },
/* 7D /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JNL_Jd },
/* 7E /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JLE_Jd },
/* 7F /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JNLE_Jd },
/* 70 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JO_Jd },
/* 71 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNO_Jd },
/* 72 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JB_Jd },
/* 73 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNB_Jd },
/* 74 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JZ_Jd },
/* 75 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNZ_Jd },
/* 76 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JBE_Jd },
/* 77 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNBE_Jd },
/* 78 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JS_Jd },
/* 79 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNS_Jd },
/* 7A /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JP_Jd },
/* 7B /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNP_Jd },
/* 7C /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JL_Jd },
/* 7D /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNL_Jd },
/* 7E /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JLE_Jd },
/* 7F /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNLE_Jd },
/* 80 /dr */ { BxGroup1 | BxImmediate_Ib, NULL, BxOpcodeInfoG1EbIbR },
/* 81 /dr */ { BxGroup1 | BxImmediate_Iv, NULL, BxOpcodeInfoG1EdR },
/* 82 /dr */ { BxGroup1 | BxImmediate_Ib, NULL, BxOpcodeInfoG1EbIbR },
@ -890,7 +890,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 8B /dr */ { 0, &BX_CPU_C::MOV_GdEdR },
/* 8C /dr */ { 0, &BX_CPU_C::MOV_EwSw },
/* 8D /dr */ { 0, &BX_CPU_C::BxError }, // LEA
/* 8E /dr */ { 0, &BX_CPU_C::MOV_SwEw },
/* 8E /dr */ { BxTraceEnd, &BX_CPU_C::MOV_SwEw }, // async_event = 1
/* 8F /dr */ { 0, &BX_CPU_C::POP_EdR },
/* 90 /dr */ { 0, &BX_CPU_C::NOP },
/* 91 /dr */ { 0, &BX_CPU_C::XCHG_ERXEAX },
@ -902,7 +902,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 97 /dr */ { 0, &BX_CPU_C::XCHG_ERXEAX },
/* 98 /dr */ { 0, &BX_CPU_C::CWDE },
/* 99 /dr */ { 0, &BX_CPU_C::CDQ },
/* 9A /dr */ { BxImmediate_IvIw, &BX_CPU_C::CALL32_Ap },
/* 9A /dr */ { BxImmediate_IvIw | BxTraceEnd, &BX_CPU_C::CALL32_Ap },
/* 9B /dr */ { 0, &BX_CPU_C::FWAIT },
/* 9C /dr */ { 0, &BX_CPU_C::PUSHF_Fd },
/* 9D /dr */ { 0, &BX_CPU_C::POPF_Fd },
@ -942,20 +942,20 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* BF /dr */ { BxImmediate_Iv, &BX_CPU_C::MOV_ERXId },
/* C0 /dr */ { BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfoG2Eb },
/* C1 /dr */ { BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfoG2Ed },
/* C2 /dr */ { BxImmediate_Iw, &BX_CPU_C::RETnear32_Iw },
/* C3 /dr */ { 0, &BX_CPU_C::RETnear32 },
/* C2 /dr */ { BxImmediate_Iw | BxTraceEnd, &BX_CPU_C::RETnear32_Iw },
/* C3 /dr */ { BxTraceEnd, &BX_CPU_C::RETnear32 },
/* C4 /dr */ { 0, &BX_CPU_C::BxError }, // LES
/* C5 /dr */ { 0, &BX_CPU_C::BxError }, // LDS
/* C6 /dr */ { BxImmediate_Ib, &BX_CPU_C::MOV_EbIbR },
/* C7 /dr */ { BxImmediate_Iv, &BX_CPU_C::MOV_EdIdR },
/* C8 /dr */ { BxImmediate_IwIb, &BX_CPU_C::ENTER32_IwIb },
/* C9 /dr */ { 0, &BX_CPU_C::LEAVE },
/* CA /dr */ { BxImmediate_Iw, &BX_CPU_C::RETfar32_Iw },
/* CB /dr */ { 0, &BX_CPU_C::RETfar32 },
/* CC /dr */ { 0, &BX_CPU_C::INT3 },
/* CD /dr */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
/* CE /dr */ { 0, &BX_CPU_C::INTO },
/* CF /dr */ { 0, &BX_CPU_C::IRET32 },
/* CA /dr */ { BxImmediate_Iw | BxTraceEnd, &BX_CPU_C::RETfar32_Iw },
/* CB /dr */ { BxTraceEnd, &BX_CPU_C::RETfar32 },
/* CC /dr */ { BxTraceEnd, &BX_CPU_C::INT3 },
/* CD /dr */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
/* CE /dr */ { BxTraceEnd, &BX_CPU_C::INTO },
/* CF /dr */ { BxTraceEnd, &BX_CPU_C::IRET32 },
/* D0 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
/* D1 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Ed },
/* D2 /dr */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
@ -984,27 +984,27 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* DE /dr */ { 0, &BX_CPU_C::FPU_ESC },
/* DF /dr */ { 0, &BX_CPU_C::FPU_ESC },
#endif
/* E0 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPNE_Jb },
/* E1 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPE_Jb },
/* E2 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::LOOP_Jb },
/* E3 /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JCXZ_Jb },
/* E0 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::LOOPNE_Jb },
/* E1 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::LOOPE_Jb },
/* E2 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::LOOP_Jb },
/* E3 /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JCXZ_Jb },
/* E4 /dr */ { BxImmediate_Ib, &BX_CPU_C::IN_ALIb },
/* E5 /dr */ { BxImmediate_Ib, &BX_CPU_C::IN_EAXIb },
/* E6 /dr */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbAL },
/* E7 /dr */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbEAX },
/* E8 /dr */ { BxImmediate_BrOff32, &BX_CPU_C::CALL_Jd },
/* E9 /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JMP_Jd },
/* EA /dr */ { BxImmediate_IvIw, &BX_CPU_C::JMP_Ap },
/* EB /dr */ { BxImmediate_BrOff8, &BX_CPU_C::JMP_Jd },
/* E8 /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::CALL_Jd },
/* E9 /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JMP_Jd },
/* EA /dr */ { BxImmediate_IvIw | BxTraceEnd, &BX_CPU_C::JMP_Ap },
/* EB /dr */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JMP_Jd },
/* EC /dr */ { 0, &BX_CPU_C::IN_ALDX },
/* ED /dr */ { 0, &BX_CPU_C::IN_EAXDX },
/* EE /dr */ { 0, &BX_CPU_C::OUT_DXAL },
/* EF /dr */ { 0, &BX_CPU_C::OUT_DXEAX },
/* F0 /dr */ { BxPrefix, &BX_CPU_C::BxError }, // LOCK:
/* F1 /dr */ { 0, &BX_CPU_C::INT1 },
/* F1 /dr */ { BxTraceEnd, &BX_CPU_C::INT1 },
/* F2 /dr */ { BxPrefix, &BX_CPU_C::BxError }, // REPNE/REPNZ
/* F3 /dr */ { BxPrefix, &BX_CPU_C::BxError }, // REP,REPE/REPZ
/* F4 /dr */ { 0, &BX_CPU_C::HLT },
/* F4 /dr */ { BxTraceEnd, &BX_CPU_C::HLT },
/* F5 /dr */ { 0, &BX_CPU_C::CMC },
/* F6 /dr */ { BxGroup3, NULL, BxOpcodeInfoG3EbR },
/* F7 /dr */ { BxGroup3, NULL, BxOpcodeInfoG3EdR },
@ -1023,22 +1023,22 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F 03 /dr */ { 0, &BX_CPU_C::LSL_GvEw },
/* 0F 04 /dr */ { 0, &BX_CPU_C::BxError },
#if BX_SUPPORT_X86_64
/* 0F 05 /dr */ { 0, &BX_CPU_C::SYSCALL },
/* 0F 05 /dr */ { BxTraceEnd, &BX_CPU_C::SYSCALL },
#elif BX_CPU_LEVEL == 2
/* 0F 05 /dr */ { 0, &BX_CPU_C::LOADALL },
/* 0F 05 /dr */ { BxTraceEnd, &BX_CPU_C::LOADALL },
#else
/* 0F 05 /dr */ { 0, &BX_CPU_C::BxError },
#endif
/* 0F 06 /dr */ { 0, &BX_CPU_C::CLTS },
#if BX_SUPPORT_X86_64
/* 0F 07 /dr */ { 0, &BX_CPU_C::SYSRET },
/* 0F 07 /dr */ { BxTraceEnd, &BX_CPU_C::SYSRET },
#else
/* 0F 07 /dr */ { 0, &BX_CPU_C::BxError },
#endif
/* 0F 08 /dr */ { 0, &BX_CPU_C::INVD },
/* 0F 09 /dr */ { 0, &BX_CPU_C::WBINVD },
/* 0F 08 /dr */ { BxTraceEnd, &BX_CPU_C::INVD },
/* 0F 09 /dr */ { BxTraceEnd, &BX_CPU_C::WBINVD },
/* 0F 0A /dr */ { 0, &BX_CPU_C::BxError },
/* 0F 0B /dr */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F 0B /dr */ { BxTraceEnd, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F 0C /dr */ { 0, &BX_CPU_C::BxError },
#if BX_SUPPORT_X86_64 || BX_SUPPORT_3DNOW
/* 0F 0D /dr */ { 0, &BX_CPU_C::NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
@ -1080,11 +1080,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
#endif
/* 0F 20 /dr */ { 0, &BX_CPU_C::MOV_RdCd },
/* 0F 21 /dr */ { 0, &BX_CPU_C::MOV_RdDd },
/* 0F 22 /dr */ { 0, &BX_CPU_C::MOV_CdRd },
/* 0F 23 /dr */ { 0, &BX_CPU_C::MOV_DdRd },
/* 0F 24 /dr */ { 0, &BX_CPU_C::MOV_RdTd },
/* 0F 22 /dr */ { BxTraceEnd, &BX_CPU_C::MOV_CdRd },
/* 0F 23 /dr */ { BxTraceEnd, &BX_CPU_C::MOV_DdRd },
/* 0F 24 /dr */ { BxTraceEnd, &BX_CPU_C::MOV_RdTd }, // not implemented
/* 0F 25 /dr */ { 0, &BX_CPU_C::BxError },
/* 0F 26 /dr */ { 0, &BX_CPU_C::MOV_TdRd },
/* 0F 26 /dr */ { BxTraceEnd, &BX_CPU_C::MOV_TdRd }, // not implemented
/* 0F 27 /dr */ { 0, &BX_CPU_C::BxError },
/* 0F 28 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f29 },
@ -1098,8 +1098,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F 31 /dr */ { 0, &BX_CPU_C::RDTSC },
/* 0F 32 /dr */ { 0, &BX_CPU_C::RDMSR },
/* 0F 33 /dr */ { 0, &BX_CPU_C::RDPMC },
/* 0F 34 /dr */ { 0, &BX_CPU_C::SYSENTER },
/* 0F 35 /dr */ { 0, &BX_CPU_C::SYSEXIT },
/* 0F 34 /dr */ { BxTraceEnd, &BX_CPU_C::SYSENTER },
/* 0F 35 /dr */ { BxTraceEnd, &BX_CPU_C::SYSEXIT },
/* 0F 36 /dr */ { 0, &BX_CPU_C::BxError },
/* 0F 37 /dr */ { 0, &BX_CPU_C::BxError },
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
@ -1182,22 +1182,22 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F 7D /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7d },
/* 0F 7E /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7e },
/* 0F 7F /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7f },
/* 0F 80 /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JO_Jd },
/* 0F 81 /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JNO_Jd },
/* 0F 82 /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JB_Jd },
/* 0F 83 /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JNB_Jd },
/* 0F 84 /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JZ_Jd },
/* 0F 85 /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JNZ_Jd },
/* 0F 86 /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JBE_Jd },
/* 0F 87 /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JNBE_Jd },
/* 0F 88 /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JS_Jd },
/* 0F 89 /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JNS_Jd },
/* 0F 8A /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JP_Jd },
/* 0F 8B /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JNP_Jd },
/* 0F 8C /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JL_Jd },
/* 0F 8D /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JNL_Jd },
/* 0F 8E /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JLE_Jd },
/* 0F 8F /dr */ { BxImmediate_BrOff32, &BX_CPU_C::JNLE_Jd },
/* 0F 80 /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JO_Jd },
/* 0F 81 /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNO_Jd },
/* 0F 82 /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JB_Jd },
/* 0F 83 /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNB_Jd },
/* 0F 84 /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JZ_Jd },
/* 0F 85 /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNZ_Jd },
/* 0F 86 /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JBE_Jd },
/* 0F 87 /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNBE_Jd },
/* 0F 88 /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JS_Jd },
/* 0F 89 /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNS_Jd },
/* 0F 8A /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JP_Jd },
/* 0F 8B /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNP_Jd },
/* 0F 8C /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JL_Jd },
/* 0F 8D /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNL_Jd },
/* 0F 8E /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JLE_Jd },
/* 0F 8F /dr */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNLE_Jd },
/* 0F 90 /dr */ { 0, &BX_CPU_C::SETO_Eb },
/* 0F 91 /dr */ { 0, &BX_CPU_C::SETNO_Eb },
/* 0F 92 /dr */ { 0, &BX_CPU_C::SETB_Eb },
@ -1220,11 +1220,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F A3 /dr */ { 0, &BX_CPU_C::BT_EdGdR },
/* 0F A4 /dr */ { BxImmediate_Ib, &BX_CPU_C::SHLD_EdGd },
/* 0F A5 /dr */ { 0, &BX_CPU_C::SHLD_EdGd },
/* 0F A6 /dr */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
/* 0F A7 /dr */ { 0, &BX_CPU_C::CMPXCHG_IBTS },
/* 0F A6 /dr */ { BxTraceEnd, &BX_CPU_C::CMPXCHG_XBTS }, // not implemented
/* 0F A7 /dr */ { BxTraceEnd, &BX_CPU_C::CMPXCHG_IBTS }, // not implemented
/* 0F A8 /dr */ { 0, &BX_CPU_C::PUSH32_GS },
/* 0F A9 /dr */ { 0, &BX_CPU_C::POP32_GS },
/* 0F AA /dr */ { 0, &BX_CPU_C::RSM },
/* 0F AA /dr */ { BxTraceEnd, &BX_CPU_C::RSM },
/* 0F AB /dr */ { 0, &BX_CPU_C::BTS_EdGdR },
/* 0F AC /dr */ { BxImmediate_Ib, &BX_CPU_C::SHRD_EdGd },
/* 0F AD /dr */ { 0, &BX_CPU_C::SHRD_EdGd },
@ -1239,7 +1239,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F B6 /dr */ { 0, &BX_CPU_C::MOVZX_GdEbR },
/* 0F B7 /dr */ { 0, &BX_CPU_C::MOVZX_GdEwR },
/* 0F B8 /dr */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fb8d },
/* 0F B9 /dr */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F B9 /dr */ { BxTraceEnd, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F BA /dr */ { BxGroup8, NULL, BxOpcodeInfoG8EdIbR },
/* 0F BB /dr */ { 0, &BX_CPU_C::BTC_EdGdR },
/* 0F BC /dr */ { 0, &BX_CPU_C::BSF_GdEd },
@ -1342,7 +1342,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 14 /wm */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
/* 15 /wm */ { BxImmediate_Iv, &BX_CPU_C::ADC_AXIw },
/* 16 /wm */ { 0, &BX_CPU_C::PUSH16_SS },
/* 17 /wm */ { 0, &BX_CPU_C::POP16_SS },
/* 17 /wm */ { BxTraceEnd, &BX_CPU_C::POP16_SS }, // async_event = 1
/* 18 /wm */ { BxLockable, &BX_CPU_C::SBB_EbGbM },
/* 19 /wm */ { BxLockable, &BX_CPU_C::SBB_EwGwM },
/* 1A /wm */ { 0, &BX_CPU_C::SBB_GbEbM },
@ -1431,22 +1431,22 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 6D /wm */ { 0, &BX_CPU_C::REP_INSW_YwDX },
/* 6E /wm */ { 0, &BX_CPU_C::REP_OUTSB_DXXb },
/* 6F /wm */ { 0, &BX_CPU_C::REP_OUTSW_DXXw },
/* 70 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JO_Jw },
/* 71 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JNO_Jw },
/* 72 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JB_Jw },
/* 73 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JNB_Jw },
/* 74 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JZ_Jw },
/* 75 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JNZ_Jw },
/* 76 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JBE_Jw },
/* 77 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JNBE_Jw },
/* 78 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JS_Jw },
/* 79 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JNS_Jw },
/* 7A /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JP_Jw },
/* 7B /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JNP_Jw },
/* 7C /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JL_Jw },
/* 7D /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JNL_Jw },
/* 7E /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JLE_Jw },
/* 7F /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JNLE_Jw },
/* 70 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JO_Jw },
/* 71 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNO_Jw },
/* 72 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JB_Jw },
/* 73 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNB_Jw },
/* 74 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JZ_Jw },
/* 75 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNZ_Jw },
/* 76 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JBE_Jw },
/* 77 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNBE_Jw },
/* 78 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JS_Jw },
/* 79 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNS_Jw },
/* 7A /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JP_Jw },
/* 7B /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNP_Jw },
/* 7C /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JL_Jw },
/* 7D /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNL_Jw },
/* 7E /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JLE_Jw },
/* 7F /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNLE_Jw },
/* 80 /wm */ { BxGroup1 | BxImmediate_Ib, NULL, BxOpcodeInfoG1EbIbM },
/* 81 /wm */ { BxGroup1 | BxImmediate_Iv, NULL, BxOpcodeInfoG1EwM },
/* 82 /wm */ { BxGroup1 | BxImmediate_Ib, NULL, BxOpcodeInfoG1EbIbM },
@ -1461,7 +1461,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 8B /wm */ { 0, &BX_CPU_C::MOV_GwEwM },
/* 8C /wm */ { 0, &BX_CPU_C::MOV_EwSw },
/* 8D /wm */ { 0, &BX_CPU_C::LEA_GwM },
/* 8E /wm */ { 0, &BX_CPU_C::MOV_SwEw },
/* 8E /wm */ { BxTraceEnd, &BX_CPU_C::MOV_SwEw }, // async_event = 1
/* 8F /wm */ { 0, &BX_CPU_C::POP_EwM },
/* 90 /wm */ { 0, &BX_CPU_C::NOP },
/* 91 /wm */ { 0, &BX_CPU_C::XCHG_RXAX },
@ -1473,7 +1473,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 97 /wm */ { 0, &BX_CPU_C::XCHG_RXAX },
/* 98 /wm */ { 0, &BX_CPU_C::CBW },
/* 99 /wm */ { 0, &BX_CPU_C::CWD },
/* 9A /wm */ { BxImmediate_IvIw, &BX_CPU_C::CALL16_Ap },
/* 9A /wm */ { BxImmediate_IvIw | BxTraceEnd, &BX_CPU_C::CALL16_Ap },
/* 9B /wm */ { 0, &BX_CPU_C::FWAIT },
/* 9C /wm */ { 0, &BX_CPU_C::PUSHF_Fw },
/* 9D /wm */ { 0, &BX_CPU_C::POPF_Fw },
@ -1513,20 +1513,20 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* BF /wm */ { BxImmediate_Iv, &BX_CPU_C::MOV_RXIw },
/* C0 /wm */ { BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfoG2Eb },
/* C1 /wm */ { BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfoG2Ew },
/* C2 /wm */ { BxImmediate_Iw, &BX_CPU_C::RETnear16_Iw },
/* C3 /wm */ { 0, &BX_CPU_C::RETnear16 },
/* C2 /wm */ { BxImmediate_Iw | BxTraceEnd, &BX_CPU_C::RETnear16_Iw },
/* C3 /wm */ { BxTraceEnd, &BX_CPU_C::RETnear16 },
/* C4 /wm */ { 0, &BX_CPU_C::LES_GwMp },
/* C5 /wm */ { 0, &BX_CPU_C::LDS_GwMp },
/* C6 /wm */ { BxImmediate_Ib, &BX_CPU_C::MOV_EbIbM },
/* C7 /wm */ { BxImmediate_Iv, &BX_CPU_C::MOV_EwIwM },
/* C8 /wm */ { BxImmediate_IwIb, &BX_CPU_C::ENTER16_IwIb },
/* C9 /wm */ { 0, &BX_CPU_C::LEAVE },
/* CA /wm */ { BxImmediate_Iw, &BX_CPU_C::RETfar16_Iw },
/* CB /wm */ { 0, &BX_CPU_C::RETfar16 },
/* CC /wm */ { 0, &BX_CPU_C::INT3 },
/* CD /wm */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
/* CE /wm */ { 0, &BX_CPU_C::INTO },
/* CF /wm */ { 0, &BX_CPU_C::IRET16 },
/* CA /wm */ { BxImmediate_Iw | BxTraceEnd, &BX_CPU_C::RETfar16_Iw },
/* CB /wm */ { BxTraceEnd, &BX_CPU_C::RETfar16 },
/* CC /wm */ { BxTraceEnd, &BX_CPU_C::INT3 },
/* CD /wm */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
/* CE /wm */ { BxTraceEnd, &BX_CPU_C::INTO },
/* CF /wm */ { BxTraceEnd, &BX_CPU_C::IRET16 },
/* D0 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
/* D1 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Ew },
/* D2 /wm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
@ -1555,27 +1555,27 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* DE /wm */ { 0, &BX_CPU_C::FPU_ESC },
/* DF /wm */ { 0, &BX_CPU_C::FPU_ESC },
#endif
/* E0 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPNE_Jb },
/* E1 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPE_Jb },
/* E2 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::LOOP_Jb },
/* E3 /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JCXZ_Jb },
/* E0 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::LOOPNE_Jb },
/* E1 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::LOOPE_Jb },
/* E2 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::LOOP_Jb },
/* E3 /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JCXZ_Jb },
/* E4 /wm */ { BxImmediate_Ib, &BX_CPU_C::IN_ALIb },
/* E5 /wm */ { BxImmediate_Ib, &BX_CPU_C::IN_AXIb },
/* E6 /wm */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbAL },
/* E7 /wm */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbAX },
/* E8 /wm */ { BxImmediate_BrOff16, &BX_CPU_C::CALL_Jw },
/* E9 /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JMP_Jw },
/* EA /wm */ { BxImmediate_IvIw, &BX_CPU_C::JMP_Ap },
/* EB /wm */ { BxImmediate_BrOff8, &BX_CPU_C::JMP_Jw },
/* E8 /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::CALL_Jw },
/* E9 /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JMP_Jw },
/* EA /wm */ { BxImmediate_IvIw | BxTraceEnd, &BX_CPU_C::JMP_Ap },
/* EB /wm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JMP_Jw },
/* EC /wm */ { 0, &BX_CPU_C::IN_ALDX },
/* ED /wm */ { 0, &BX_CPU_C::IN_AXDX },
/* EE /wm */ { 0, &BX_CPU_C::OUT_DXAL },
/* EF /wm */ { 0, &BX_CPU_C::OUT_DXAX },
/* F0 /wm */ { BxPrefix, &BX_CPU_C::BxError }, // LOCK
/* F1 /wm */ { 0, &BX_CPU_C::INT1 },
/* F1 /wm */ { BxTraceEnd, &BX_CPU_C::INT1 },
/* F2 /wm */ { BxPrefix, &BX_CPU_C::BxError }, // REPNE/REPNZ
/* F3 /wm */ { BxPrefix, &BX_CPU_C::BxError }, // REP, REPE/REPZ
/* F4 /wm */ { 0, &BX_CPU_C::HLT },
/* F4 /wm */ { BxTraceEnd, &BX_CPU_C::HLT },
/* F5 /wm */ { 0, &BX_CPU_C::CMC },
/* F6 /wm */ { BxGroup3, NULL, BxOpcodeInfoG3EbM },
/* F7 /wm */ { BxGroup3, NULL, BxOpcodeInfoG3EwM },
@ -1594,22 +1594,22 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F 03 /wm */ { 0, &BX_CPU_C::LSL_GvEw },
/* 0F 04 /wm */ { 0, &BX_CPU_C::BxError },
#if BX_SUPPORT_X86_64
/* 0F 05 /wm */ { 0, &BX_CPU_C::SYSCALL },
/* 0F 05 /wm */ { BxTraceEnd, &BX_CPU_C::SYSCALL },
#elif BX_CPU_LEVEL == 2
/* 0F 05 /wm */ { 0, &BX_CPU_C::LOADALL },
/* 0F 05 /wm */ { BxTraceEnd, &BX_CPU_C::LOADALL },
#else
/* 0F 05 /wm */ { 0, &BX_CPU_C::BxError },
#endif
/* 0F 06 /wm */ { 0, &BX_CPU_C::CLTS },
#if BX_SUPPORT_X86_64
/* 0F 07 /wm */ { 0, &BX_CPU_C::SYSRET },
/* 0F 07 /wm */ { BxTraceEnd, &BX_CPU_C::SYSRET },
#else
/* 0F 07 /wm */ { 0, &BX_CPU_C::BxError },
#endif
/* 0F 08 /wm */ { 0, &BX_CPU_C::INVD },
/* 0F 09 /wm */ { 0, &BX_CPU_C::WBINVD },
/* 0F 08 /wm */ { BxTraceEnd, &BX_CPU_C::INVD },
/* 0F 09 /wm */ { BxTraceEnd, &BX_CPU_C::WBINVD },
/* 0F 0A /wm */ { 0, &BX_CPU_C::BxError },
/* 0F 0B /wm */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F 0B /wm */ { BxTraceEnd, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F 0C /wm */ { 0, &BX_CPU_C::BxError },
#if BX_SUPPORT_X86_64 || BX_SUPPORT_3DNOW
/* 0F 0D /wm */ { 0, &BX_CPU_C::NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
@ -1651,11 +1651,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
#endif
/* 0F 20 /wm */ { 0, &BX_CPU_C::MOV_RdCd },
/* 0F 21 /wm */ { 0, &BX_CPU_C::MOV_RdDd },
/* 0F 22 /wm */ { 0, &BX_CPU_C::MOV_CdRd },
/* 0F 23 /wm */ { 0, &BX_CPU_C::MOV_DdRd },
/* 0F 24 /wm */ { 0, &BX_CPU_C::MOV_RdTd },
/* 0F 22 /wm */ { BxTraceEnd, &BX_CPU_C::MOV_CdRd },
/* 0F 23 /wm */ { BxTraceEnd, &BX_CPU_C::MOV_DdRd },
/* 0F 24 /wm */ { BxTraceEnd, &BX_CPU_C::MOV_RdTd }, // not implemented
/* 0F 25 /wm */ { 0, &BX_CPU_C::BxError },
/* 0F 26 /wm */ { 0, &BX_CPU_C::MOV_TdRd },
/* 0F 26 /wm */ { BxTraceEnd, &BX_CPU_C::MOV_TdRd }, // not implemented
/* 0F 27 /wm */ { 0, &BX_CPU_C::BxError },
/* 0F 28 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f29 },
@ -1669,8 +1669,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F 31 /wm */ { 0, &BX_CPU_C::RDTSC },
/* 0F 32 /wm */ { 0, &BX_CPU_C::RDMSR },
/* 0F 33 /wm */ { 0, &BX_CPU_C::RDPMC },
/* 0F 34 /wm */ { 0, &BX_CPU_C::SYSENTER },
/* 0F 35 /wm */ { 0, &BX_CPU_C::SYSEXIT },
/* 0F 34 /wm */ { BxTraceEnd, &BX_CPU_C::SYSENTER },
/* 0F 35 /wm */ { BxTraceEnd, &BX_CPU_C::SYSEXIT },
/* 0F 36 /wm */ { 0, &BX_CPU_C::BxError },
/* 0F 37 /wm */ { 0, &BX_CPU_C::BxError },
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
@ -1753,22 +1753,22 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F 7D /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7d },
/* 0F 7E /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7e },
/* 0F 7F /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7f },
/* 0F 80 /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JO_Jw },
/* 0F 81 /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JNO_Jw },
/* 0F 82 /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JB_Jw },
/* 0F 83 /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JNB_Jw },
/* 0F 84 /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JZ_Jw },
/* 0F 85 /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JNZ_Jw },
/* 0F 86 /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JBE_Jw },
/* 0F 87 /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JNBE_Jw },
/* 0F 88 /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JS_Jw },
/* 0F 89 /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JNS_Jw },
/* 0F 8A /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JP_Jw },
/* 0F 8B /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JNP_Jw },
/* 0F 8C /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JL_Jw },
/* 0F 8D /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JNL_Jw },
/* 0F 8E /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JLE_Jw },
/* 0F 8F /wm */ { BxImmediate_BrOff16, &BX_CPU_C::JNLE_Jw },
/* 0F 80 /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JO_Jw },
/* 0F 81 /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNO_Jw },
/* 0F 82 /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JB_Jw },
/* 0F 83 /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNB_Jw },
/* 0F 84 /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JZ_Jw },
/* 0F 85 /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNZ_Jw },
/* 0F 86 /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JBE_Jw },
/* 0F 87 /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNBE_Jw },
/* 0F 88 /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JS_Jw },
/* 0F 89 /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNS_Jw },
/* 0F 8A /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JP_Jw },
/* 0F 8B /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNP_Jw },
/* 0F 8C /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JL_Jw },
/* 0F 8D /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNL_Jw },
/* 0F 8E /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JLE_Jw },
/* 0F 8F /wm */ { BxImmediate_BrOff16 | BxTraceEnd, &BX_CPU_C::JNLE_Jw },
/* 0F 90 /wm */ { 0, &BX_CPU_C::SETO_Eb },
/* 0F 91 /wm */ { 0, &BX_CPU_C::SETNO_Eb },
/* 0F 92 /wm */ { 0, &BX_CPU_C::SETB_Eb },
@ -1791,11 +1791,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F A3 /wm */ { 0, &BX_CPU_C::BT_EwGwM },
/* 0F A4 /wm */ { BxImmediate_Ib, &BX_CPU_C::SHLD_EwGw },
/* 0F A5 /wm */ { 0, &BX_CPU_C::SHLD_EwGw },
/* 0F A6 /wm */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
/* 0F A7 /wm */ { 0, &BX_CPU_C::CMPXCHG_IBTS },
/* 0F A6 /wm */ { BxTraceEnd, &BX_CPU_C::CMPXCHG_XBTS }, // not implemented
/* 0F A7 /wm */ { BxTraceEnd, &BX_CPU_C::CMPXCHG_IBTS }, // not implemented
/* 0F A8 /wm */ { 0, &BX_CPU_C::PUSH16_GS },
/* 0F A9 /wm */ { 0, &BX_CPU_C::POP16_GS },
/* 0F AA /wm */ { 0, &BX_CPU_C::RSM },
/* 0F AA /wm */ { BxTraceEnd, &BX_CPU_C::RSM },
/* 0F AB /wm */ { BxLockable, &BX_CPU_C::BTS_EwGwM },
/* 0F AC /wm */ { BxImmediate_Ib, &BX_CPU_C::SHRD_EwGw },
/* 0F AD /wm */ { 0, &BX_CPU_C::SHRD_EwGw },
@ -1810,7 +1810,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F B6 /wm */ { 0, &BX_CPU_C::MOVZX_GwEbM },
/* 0F B7 /wm */ { 0, &BX_CPU_C::MOV_GwEwM }, // MOVZX_GwEw
/* 0F B8 /wm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fb8w },
/* 0F B9 /wm */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F B9 /wm */ { BxTraceEnd, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F BA /wm */ { BxGroup8, NULL, BxOpcodeInfoG8EwIbM },
/* 0F BB /wm */ { BxLockable, &BX_CPU_C::BTC_EwGwM },
/* 0F BC /wm */ { 0, &BX_CPU_C::BSF_GwEw },
@ -1906,7 +1906,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 14 /dm */ { BxImmediate_Ib, &BX_CPU_C::ADC_ALIb },
/* 15 /dm */ { BxImmediate_Iv, &BX_CPU_C::ADC_EAXId },
/* 16 /dm */ { 0, &BX_CPU_C::PUSH32_SS },
/* 17 /dm */ { 0, &BX_CPU_C::POP32_SS },
/* 17 /dm */ { BxTraceEnd, &BX_CPU_C::POP32_SS }, // async_event = 1
/* 18 /dm */ { BxLockable, &BX_CPU_C::SBB_EbGbM },
/* 19 /dm */ { BxLockable, &BX_CPU_C::SBB_EdGdM },
/* 1A /dm */ { 0, &BX_CPU_C::SBB_GbEbM },
@ -1995,22 +1995,22 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 6D /dm */ { 0, &BX_CPU_C::REP_INSD_YdDX },
/* 6E /dm */ { 0, &BX_CPU_C::REP_OUTSB_DXXb },
/* 6F /dm */ { 0, &BX_CPU_C::REP_OUTSD_DXXd },
/* 70 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JO_Jd },
/* 71 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JNO_Jd },
/* 72 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JB_Jd },
/* 73 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JNB_Jd },
/* 74 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JZ_Jd },
/* 75 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JNZ_Jd },
/* 76 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JBE_Jd },
/* 77 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JNBE_Jd },
/* 78 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JS_Jd },
/* 79 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JNS_Jd },
/* 7A /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JP_Jd },
/* 7B /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JNP_Jd },
/* 7C /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JL_Jd },
/* 7D /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JNL_Jd },
/* 7E /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JLE_Jd },
/* 7F /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JNLE_Jd },
/* 70 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JO_Jd },
/* 71 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNO_Jd },
/* 72 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JB_Jd },
/* 73 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNB_Jd },
/* 74 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JZ_Jd },
/* 75 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNZ_Jd },
/* 76 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JBE_Jd },
/* 77 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNBE_Jd },
/* 78 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JS_Jd },
/* 79 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNS_Jd },
/* 7A /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JP_Jd },
/* 7B /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNP_Jd },
/* 7C /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JL_Jd },
/* 7D /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNL_Jd },
/* 7E /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JLE_Jd },
/* 7F /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JNLE_Jd },
/* 80 /dm */ { BxGroup1 | BxImmediate_Ib, NULL, BxOpcodeInfoG1EbIbM },
/* 81 /dm */ { BxGroup1 | BxImmediate_Iv, NULL, BxOpcodeInfoG1EdM },
/* 82 /dm */ { BxGroup1 | BxImmediate_Ib, NULL, BxOpcodeInfoG1EbIbM },
@ -2025,7 +2025,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 8B /dm */ { 0, &BX_CPU_C::MOV_GdEdM },
/* 8C /dm */ { 0, &BX_CPU_C::MOV_EwSw },
/* 8D /dm */ { 0, &BX_CPU_C::LEA_GdM },
/* 8E /dm */ { 0, &BX_CPU_C::MOV_SwEw },
/* 8E /dm */ { BxTraceEnd, &BX_CPU_C::MOV_SwEw }, // async_event = 1
/* 8F /dm */ { 0, &BX_CPU_C::POP_EdM },
/* 90 /dm */ { 0, &BX_CPU_C::NOP },
/* 91 /dm */ { 0, &BX_CPU_C::XCHG_ERXEAX },
@ -2037,7 +2037,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 97 /dm */ { 0, &BX_CPU_C::XCHG_ERXEAX },
/* 98 /dm */ { 0, &BX_CPU_C::CWDE },
/* 99 /dm */ { 0, &BX_CPU_C::CDQ },
/* 9A /dm */ { BxImmediate_IvIw, &BX_CPU_C::CALL32_Ap },
/* 9A /dm */ { BxImmediate_IvIw | BxTraceEnd, &BX_CPU_C::CALL32_Ap },
/* 9B /dm */ { 0, &BX_CPU_C::FWAIT },
/* 9C /dm */ { 0, &BX_CPU_C::PUSHF_Fd },
/* 9D /dm */ { 0, &BX_CPU_C::POPF_Fd },
@ -2077,20 +2077,20 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* BF /dm */ { BxImmediate_Iv, &BX_CPU_C::MOV_ERXId },
/* C0 /dm */ { BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfoG2Eb },
/* C1 /dm */ { BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfoG2Ed },
/* C2 /dm */ { BxImmediate_Iw, &BX_CPU_C::RETnear32_Iw },
/* C3 /dm */ { 0, &BX_CPU_C::RETnear32 },
/* C2 /dm */ { BxImmediate_Iw | BxTraceEnd, &BX_CPU_C::RETnear32_Iw },
/* C3 /dm */ { BxTraceEnd, &BX_CPU_C::RETnear32 },
/* C4 /dm */ { 0, &BX_CPU_C::LES_GdMp },
/* C5 /dm */ { 0, &BX_CPU_C::LDS_GdMp },
/* C6 /dm */ { BxImmediate_Ib, &BX_CPU_C::MOV_EbIbM },
/* C7 /dm */ { BxImmediate_Iv, &BX_CPU_C::MOV_EdIdM },
/* C8 /dm */ { BxImmediate_IwIb, &BX_CPU_C::ENTER32_IwIb },
/* C9 /dm */ { 0, &BX_CPU_C::LEAVE },
/* CA /dm */ { BxImmediate_Iw, &BX_CPU_C::RETfar32_Iw },
/* CB /dm */ { 0, &BX_CPU_C::RETfar32 },
/* CC /dm */ { 0, &BX_CPU_C::INT3 },
/* CD /dm */ { BxImmediate_Ib, &BX_CPU_C::INT_Ib },
/* CE /dm */ { 0, &BX_CPU_C::INTO },
/* CF /dm */ { 0, &BX_CPU_C::IRET32 },
/* CA /dm */ { BxImmediate_Iw | BxTraceEnd, &BX_CPU_C::RETfar32_Iw },
/* CB /dm */ { BxTraceEnd, &BX_CPU_C::RETfar32 },
/* CC /dm */ { BxTraceEnd, &BX_CPU_C::INT3 },
/* CD /dm */ { BxImmediate_Ib | BxTraceEnd, &BX_CPU_C::INT_Ib },
/* CE /dm */ { BxTraceEnd, &BX_CPU_C::INTO },
/* CF /dm */ { BxTraceEnd, &BX_CPU_C::IRET32 },
/* D0 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
/* D1 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Ed },
/* D2 /dm */ { BxGroup2, NULL, BxOpcodeInfoG2Eb },
@ -2119,27 +2119,27 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* DE /dm */ { 0, &BX_CPU_C::FPU_ESC },
/* DF /dm */ { 0, &BX_CPU_C::FPU_ESC },
#endif
/* E0 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPNE_Jb },
/* E1 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::LOOPE_Jb },
/* E2 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::LOOP_Jb },
/* E3 /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JCXZ_Jb },
/* E0 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::LOOPNE_Jb },
/* E1 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::LOOPE_Jb },
/* E2 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::LOOP_Jb },
/* E3 /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JCXZ_Jb },
/* E4 /dm */ { BxImmediate_Ib, &BX_CPU_C::IN_ALIb },
/* E5 /dm */ { BxImmediate_Ib, &BX_CPU_C::IN_EAXIb },
/* E6 /dm */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbAL },
/* E7 /dm */ { BxImmediate_Ib, &BX_CPU_C::OUT_IbEAX },
/* E8 /dm */ { BxImmediate_BrOff32, &BX_CPU_C::CALL_Jd },
/* E9 /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JMP_Jd },
/* EA /dm */ { BxImmediate_IvIw, &BX_CPU_C::JMP_Ap },
/* EB /dm */ { BxImmediate_BrOff8, &BX_CPU_C::JMP_Jd },
/* E8 /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::CALL_Jd },
/* E9 /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JMP_Jd },
/* EA /dm */ { BxImmediate_IvIw | BxTraceEnd, &BX_CPU_C::JMP_Ap },
/* EB /dm */ { BxImmediate_BrOff8 | BxTraceEnd, &BX_CPU_C::JMP_Jd },
/* EC /dm */ { 0, &BX_CPU_C::IN_ALDX },
/* ED /dm */ { 0, &BX_CPU_C::IN_EAXDX },
/* EE /dm */ { 0, &BX_CPU_C::OUT_DXAL },
/* EF /dm */ { 0, &BX_CPU_C::OUT_DXEAX },
/* F0 /dm */ { BxPrefix, &BX_CPU_C::BxError }, // LOCK:
/* F1 /dm */ { 0, &BX_CPU_C::INT1 },
/* F1 /dm */ { BxTraceEnd, &BX_CPU_C::INT1 },
/* F2 /dm */ { BxPrefix, &BX_CPU_C::BxError }, // REPNE/REPNZ
/* F3 /dm */ { BxPrefix, &BX_CPU_C::BxError }, // REP,REPE/REPZ
/* F4 /dm */ { 0, &BX_CPU_C::HLT },
/* F4 /dm */ { BxTraceEnd, &BX_CPU_C::HLT },
/* F5 /dm */ { 0, &BX_CPU_C::CMC },
/* F6 /dm */ { BxGroup3, NULL, BxOpcodeInfoG3EbM },
/* F7 /dm */ { BxGroup3, NULL, BxOpcodeInfoG3EdM },
@ -2158,22 +2158,22 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F 03 /dm */ { 0, &BX_CPU_C::LSL_GvEw },
/* 0F 04 /dm */ { 0, &BX_CPU_C::BxError },
#if BX_SUPPORT_X86_64
/* 0F 05 /dm */ { 0, &BX_CPU_C::SYSCALL },
/* 0F 05 /dm */ { BxTraceEnd, &BX_CPU_C::SYSCALL },
#elif BX_CPU_LEVEL == 2
/* 0F 05 /dm */ { 0, &BX_CPU_C::LOADALL },
/* 0F 05 /dm */ { BxTraceEnd, &BX_CPU_C::LOADALL },
#else
/* 0F 05 /dm */ { 0, &BX_CPU_C::BxError },
#endif
/* 0F 06 /dm */ { 0, &BX_CPU_C::CLTS },
#if BX_SUPPORT_X86_64
/* 0F 07 /dm */ { 0, &BX_CPU_C::SYSRET },
/* 0F 07 /dm */ { BxTraceEnd, &BX_CPU_C::SYSRET },
#else
/* 0F 07 /dm */ { 0, &BX_CPU_C::BxError },
#endif
/* 0F 08 /dm */ { 0, &BX_CPU_C::INVD },
/* 0F 09 /dm */ { 0, &BX_CPU_C::WBINVD },
/* 0F 08 /dm */ { BxTraceEnd, &BX_CPU_C::INVD },
/* 0F 09 /dm */ { BxTraceEnd, &BX_CPU_C::WBINVD },
/* 0F 0A /dm */ { 0, &BX_CPU_C::BxError },
/* 0F 0B /dm */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F 0B /dm */ { BxTraceEnd, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F 0C /dm */ { 0, &BX_CPU_C::BxError },
#if BX_SUPPORT_X86_64 || BX_SUPPORT_3DNOW
/* 0F 0D /dm */ { 0, &BX_CPU_C::NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
@ -2215,11 +2215,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
#endif
/* 0F 20 /dm */ { 0, &BX_CPU_C::MOV_RdCd },
/* 0F 21 /dm */ { 0, &BX_CPU_C::MOV_RdDd },
/* 0F 22 /dm */ { 0, &BX_CPU_C::MOV_CdRd },
/* 0F 23 /dm */ { 0, &BX_CPU_C::MOV_DdRd },
/* 0F 24 /dm */ { 0, &BX_CPU_C::MOV_RdTd },
/* 0F 22 /dm */ { BxTraceEnd, &BX_CPU_C::MOV_CdRd },
/* 0F 23 /dm */ { BxTraceEnd, &BX_CPU_C::MOV_DdRd },
/* 0F 24 /dm */ { BxTraceEnd, &BX_CPU_C::MOV_RdTd }, // not implemented
/* 0F 25 /dm */ { 0, &BX_CPU_C::BxError },
/* 0F 26 /dm */ { 0, &BX_CPU_C::MOV_TdRd },
/* 0F 26 /dm */ { BxTraceEnd, &BX_CPU_C::MOV_TdRd }, // not implemented
/* 0F 27 /dm */ { 0, &BX_CPU_C::BxError },
/* 0F 28 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f29 },
@ -2233,8 +2233,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F 31 /dm */ { 0, &BX_CPU_C::RDTSC },
/* 0F 32 /dm */ { 0, &BX_CPU_C::RDMSR },
/* 0F 33 /dm */ { 0, &BX_CPU_C::RDPMC },
/* 0F 34 /dm */ { 0, &BX_CPU_C::SYSENTER },
/* 0F 35 /dm */ { 0, &BX_CPU_C::SYSEXIT },
/* 0F 34 /dm */ { BxTraceEnd, &BX_CPU_C::SYSENTER },
/* 0F 35 /dm */ { BxTraceEnd, &BX_CPU_C::SYSEXIT },
/* 0F 36 /dm */ { 0, &BX_CPU_C::BxError },
/* 0F 37 /dm */ { 0, &BX_CPU_C::BxError },
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
@ -2317,22 +2317,22 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F 7D /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7d },
/* 0F 7E /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7e },
/* 0F 7F /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0f7f },
/* 0F 80 /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JO_Jd },
/* 0F 81 /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JNO_Jd },
/* 0F 82 /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JB_Jd },
/* 0F 83 /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JNB_Jd },
/* 0F 84 /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JZ_Jd },
/* 0F 85 /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JNZ_Jd },
/* 0F 86 /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JBE_Jd },
/* 0F 87 /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JNBE_Jd },
/* 0F 88 /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JS_Jd },
/* 0F 89 /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JNS_Jd },
/* 0F 8A /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JP_Jd },
/* 0F 8B /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JNP_Jd },
/* 0F 8C /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JL_Jd },
/* 0F 8D /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JNL_Jd },
/* 0F 8E /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JLE_Jd },
/* 0F 8F /dm */ { BxImmediate_BrOff32, &BX_CPU_C::JNLE_Jd },
/* 0F 80 /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JO_Jd },
/* 0F 81 /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNO_Jd },
/* 0F 82 /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JB_Jd },
/* 0F 83 /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNB_Jd },
/* 0F 84 /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JZ_Jd },
/* 0F 85 /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNZ_Jd },
/* 0F 86 /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JBE_Jd },
/* 0F 87 /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNBE_Jd },
/* 0F 88 /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JS_Jd },
/* 0F 89 /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNS_Jd },
/* 0F 8A /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JP_Jd },
/* 0F 8B /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNP_Jd },
/* 0F 8C /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JL_Jd },
/* 0F 8D /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNL_Jd },
/* 0F 8E /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JLE_Jd },
/* 0F 8F /dm */ { BxImmediate_BrOff32 | BxTraceEnd, &BX_CPU_C::JNLE_Jd },
/* 0F 90 /dm */ { 0, &BX_CPU_C::SETO_Eb },
/* 0F 91 /dm */ { 0, &BX_CPU_C::SETNO_Eb },
/* 0F 92 /dm */ { 0, &BX_CPU_C::SETB_Eb },
@ -2355,11 +2355,11 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F A3 /dm */ { 0, &BX_CPU_C::BT_EdGdM },
/* 0F A4 /dm */ { BxImmediate_Ib, &BX_CPU_C::SHLD_EdGd },
/* 0F A5 /dm */ { 0, &BX_CPU_C::SHLD_EdGd },
/* 0F A6 /dm */ { 0, &BX_CPU_C::CMPXCHG_XBTS },
/* 0F A7 /dm */ { 0, &BX_CPU_C::CMPXCHG_IBTS },
/* 0F A6 /dm */ { BxTraceEnd, &BX_CPU_C::CMPXCHG_XBTS }, // not implemented
/* 0F A7 /dm */ { BxTraceEnd, &BX_CPU_C::CMPXCHG_IBTS }, // not implemented
/* 0F A8 /dm */ { 0, &BX_CPU_C::PUSH32_GS },
/* 0F A9 /dm */ { 0, &BX_CPU_C::POP32_GS },
/* 0F AA /dm */ { 0, &BX_CPU_C::RSM },
/* 0F AA /dm */ { BxTraceEnd, &BX_CPU_C::RSM },
/* 0F AB /dm */ { BxLockable, &BX_CPU_C::BTS_EdGdM },
/* 0F AC /dm */ { BxImmediate_Ib, &BX_CPU_C::SHRD_EdGd },
/* 0F AD /dm */ { 0, &BX_CPU_C::SHRD_EdGd },
@ -2374,7 +2374,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F B6 /dm */ { 0, &BX_CPU_C::MOVZX_GdEbM },
/* 0F B7 /dm */ { 0, &BX_CPU_C::MOVZX_GdEwM },
/* 0F B8 /dm */ { BxPrefixSSE, NULL, BxOpcodeGroupSSE_0fb8d },
/* 0F B9 /dm */ { 0, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F B9 /dm */ { BxTraceEnd, &BX_CPU_C::UndefinedOpcode }, // UD2 opcode
/* 0F BA /dm */ { BxGroup8, NULL, BxOpcodeInfoG8EdIbM },
/* 0F BB /dm */ { BxLockable, &BX_CPU_C::BTC_EdGdM },
/* 0F BC /dm */ { 0, &BX_CPU_C::BSF_GdEd },
@ -2797,10 +2797,15 @@ modrm_done:
// mod == 0xc0 can't be BxLockable in fetchdecode tables
if (/*(mod == 0xc0) ||*/ !(attr & BxLockable)) {
BX_INFO(("LOCK prefix unallowed (op1=0x%x, attr=0x%x, mod=0x%x, nnn=%u)", b1, attr, mod, nnn));
UndefinedOpcode(instruction);
// replace execution function with undefined-opcode
instruction->execute = &BX_CPU_C::BxError;
}
}
#if BX_SUPPORT_TRACE_CACHE
if (attr & BxTraceEnd) instruction->setStopTraceAttr();
#endif
imm_mode = attr & BxImmediate;
if (imm_mode) {
switch (imm_mode) {
@ -2935,8 +2940,16 @@ modrm_done:
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_SEG_REG_DS);
#if BX_SUPPORT_TRACE_CACHE
// set stop-trace attribute for invalid instructions
if(instruction->execute == &BX_CPU_C::BxError) {
instruction->setStopTraceAttr();
}
#endif
instruction->setB1(b1);
instruction->setILen(ilen);
return(1);
}

88
bochs/cpu/fetchdecode.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.h,v 1.44 2007-11-29 22:22:24 sshwarts Exp $
// $Id: fetchdecode.h,v 1.45 2007-12-09 18:36:05 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005 Stanislav Shwartsman
@ -2887,10 +2887,10 @@ static const BxOpcodeInfo_t BxOpcodeInfoG5wM[8] = {
// attributes defined in main area
/* 0 */ { BxLockable, &BX_CPU_C::INC_EwM },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EwM },
/* 2 */ { 0, &BX_CPU_C::CALL_Ew },
/* 3 */ { 0, &BX_CPU_C::CALL16_Ep },
/* 4 */ { 0, &BX_CPU_C::JMP_Ew },
/* 5 */ { 0, &BX_CPU_C::JMP16_Ep },
/* 2 */ { BxTraceEnd, &BX_CPU_C::CALL_Ew },
/* 3 */ { BxTraceEnd, &BX_CPU_C::CALL16_Ep },
/* 4 */ { BxTraceEnd, &BX_CPU_C::JMP_Ew },
/* 5 */ { BxTraceEnd, &BX_CPU_C::JMP16_Ep },
/* 6 */ { 0, &BX_CPU_C::PUSH_EwM },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
@ -2899,9 +2899,9 @@ static const BxOpcodeInfo_t BxOpcodeInfoG5wR[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::INC_EwR },
/* 1 */ { 0, &BX_CPU_C::DEC_EwR },
/* 2 */ { 0, &BX_CPU_C::CALL_Ew },
/* 2 */ { BxTraceEnd, &BX_CPU_C::CALL_Ew },
/* 3 */ { 0, &BX_CPU_C::BxError }, // CALL16_Ep
/* 4 */ { 0, &BX_CPU_C::JMP_Ew },
/* 4 */ { BxTraceEnd, &BX_CPU_C::JMP_Ew },
/* 5 */ { 0, &BX_CPU_C::BxError }, // JMP16_Ep
/* 6 */ { 0, &BX_CPU_C::PUSH_EwR },
/* 7 */ { 0, &BX_CPU_C::BxError }
@ -2911,10 +2911,10 @@ static const BxOpcodeInfo_t BxOpcodeInfoG5dM[8] = {
// attributes defined in main area
/* 0 */ { BxLockable, &BX_CPU_C::INC_EdM },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EdM },
/* 2 */ { 0, &BX_CPU_C::CALL_Ed },
/* 3 */ { 0, &BX_CPU_C::CALL32_Ep },
/* 4 */ { 0, &BX_CPU_C::JMP_Ed },
/* 5 */ { 0, &BX_CPU_C::JMP32_Ep },
/* 2 */ { BxTraceEnd, &BX_CPU_C::CALL_Ed },
/* 3 */ { BxTraceEnd, &BX_CPU_C::CALL32_Ep },
/* 4 */ { BxTraceEnd, &BX_CPU_C::JMP_Ed },
/* 5 */ { BxTraceEnd, &BX_CPU_C::JMP32_Ep },
/* 6 */ { 0, &BX_CPU_C::PUSH_EdM },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
@ -2923,9 +2923,9 @@ static const BxOpcodeInfo_t BxOpcodeInfoG5dR[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::INC_EdR },
/* 1 */ { 0, &BX_CPU_C::DEC_EdR },
/* 2 */ { 0, &BX_CPU_C::CALL_Ed },
/* 2 */ { BxTraceEnd, &BX_CPU_C::CALL_Ed },
/* 3 */ { 0, &BX_CPU_C::BxError }, // CALL32_Ep
/* 4 */ { 0, &BX_CPU_C::JMP_Ed },
/* 4 */ { BxTraceEnd, &BX_CPU_C::JMP_Ed },
/* 5 */ { 0, &BX_CPU_C::BxError }, // JMP32_Ep
/* 6 */ { 0, &BX_CPU_C::PUSH_EdR },
/* 7 */ { 0, &BX_CPU_C::BxError }
@ -2935,10 +2935,10 @@ static const BxOpcodeInfo_t BxOpcodeInfoG5dR[8] = {
static const BxOpcodeInfo_t BxOpcodeInfo64G5wM[8] = {
/* 0 */ { BxLockable, &BX_CPU_C::INC_EwM },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EwM },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::CALL16_Ep },
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::JMP16_Ep },
/* 2 */ { BxTraceEnd, &BX_CPU_C::CALL_Eq },
/* 3 */ { BxTraceEnd, &BX_CPU_C::CALL16_Ep },
/* 4 */ { BxTraceEnd, &BX_CPU_C::JMP_Eq },
/* 5 */ { BxTraceEnd, &BX_CPU_C::JMP16_Ep },
/* 6 */ { 0, &BX_CPU_C::PUSH_EwM },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
@ -2946,9 +2946,9 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G5wM[8] = {
static const BxOpcodeInfo_t BxOpcodeInfo64G5wR[8] = {
/* 0 */ { 0, &BX_CPU_C::INC_EwR },
/* 1 */ { 0, &BX_CPU_C::DEC_EwR },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 2 */ { BxTraceEnd, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::BxError }, // CALL16_Ep
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 4 */ { BxTraceEnd, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::BxError }, // JMP16_Ep
/* 6 */ { 0, &BX_CPU_C::PUSH_EwR },
/* 7 */ { 0, &BX_CPU_C::BxError }
@ -2957,10 +2957,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G5wR[8] = {
static const BxOpcodeInfo_t BxOpcodeInfo64G5dM[8] = {
/* 0 */ { BxLockable, &BX_CPU_C::INC_EdM },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EdM },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::CALL32_Ep },
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::JMP32_Ep },
/* 2 */ { BxTraceEnd, &BX_CPU_C::CALL_Eq },
/* 3 */ { BxTraceEnd, &BX_CPU_C::CALL32_Ep },
/* 4 */ { BxTraceEnd, &BX_CPU_C::JMP_Eq },
/* 5 */ { BxTraceEnd, &BX_CPU_C::JMP32_Ep },
/* 6 */ { 0, &BX_CPU_C::PUSH_EqM },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
@ -2968,9 +2968,9 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G5dM[8] = {
static const BxOpcodeInfo_t BxOpcodeInfo64G5dR[8] = {
/* 0 */ { 0, &BX_CPU_C::INC_EdR },
/* 1 */ { 0, &BX_CPU_C::DEC_EdR },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 2 */ { BxTraceEnd, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::BxError }, // CALL32_Ep
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 4 */ { BxTraceEnd, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::BxError }, // JMP32_Ep
/* 6 */ { 0, &BX_CPU_C::PUSH_EqR },
/* 7 */ { 0, &BX_CPU_C::BxError }
@ -2979,10 +2979,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G5dR[8] = {
static const BxOpcodeInfo_t BxOpcodeInfo64G5qM[8] = {
/* 0 */ { BxLockable, &BX_CPU_C::INC_EqM },
/* 1 */ { BxLockable, &BX_CPU_C::DEC_EqM },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::CALL64_Ep },
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::JMP64_Ep },
/* 2 */ { BxTraceEnd, &BX_CPU_C::CALL_Eq },
/* 3 */ { BxTraceEnd, &BX_CPU_C::CALL64_Ep },
/* 4 */ { BxTraceEnd, &BX_CPU_C::JMP_Eq },
/* 5 */ { BxTraceEnd, &BX_CPU_C::JMP64_Ep },
/* 6 */ { 0, &BX_CPU_C::PUSH_EqM },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
@ -2990,9 +2990,9 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G5qM[8] = {
static const BxOpcodeInfo_t BxOpcodeInfo64G5qR[8] = {
/* 0 */ { 0, &BX_CPU_C::INC_EqR },
/* 1 */ { 0, &BX_CPU_C::DEC_EqR },
/* 2 */ { 0, &BX_CPU_C::CALL_Eq },
/* 2 */ { BxTraceEnd, &BX_CPU_C::CALL_Eq },
/* 3 */ { 0, &BX_CPU_C::BxError }, // CALL64_Ep
/* 4 */ { 0, &BX_CPU_C::JMP_Eq },
/* 4 */ { BxTraceEnd, &BX_CPU_C::JMP_Eq },
/* 5 */ { 0, &BX_CPU_C::BxError }, // JMP64_Ep
/* 6 */ { 0, &BX_CPU_C::PUSH_EqR },
/* 7 */ { 0, &BX_CPU_C::BxError }
@ -3006,8 +3006,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G5qR[8] = {
static const BxOpcodeInfo_t BxOpcodeInfoG6[8] = {
/* 0 */ { 0, &BX_CPU_C::SLDT_Ew },
/* 1 */ { 0, &BX_CPU_C::STR_Ew },
/* 2 */ { 0, &BX_CPU_C::LLDT_Ew },
/* 3 */ { 0, &BX_CPU_C::LTR_Ew },
/* 2 */ { BxTraceEnd, &BX_CPU_C::LLDT_Ew },
/* 3 */ { BxTraceEnd, &BX_CPU_C::LTR_Ew },
/* 4 */ { 0, &BX_CPU_C::VERR_Ew },
/* 5 */ { 0, &BX_CPU_C::VERW_Ew },
/* 6 */ { 0, &BX_CPU_C::BxError },
@ -3028,7 +3028,7 @@ static const BxOpcodeInfo_t BxOpcodeInfoG6[8] = {
static const BxOpcodeInfo_t opcodesGroupRmMONITOR[8] = {
/* 0 */ { 0, &BX_CPU_C::MONITOR },
/* 1 */ { 0, &BX_CPU_C::MWAIT },
/* 1 */ { BxTraceEnd, &BX_CPU_C::MWAIT },
/* 2 */ { 0, &BX_CPU_C::BxError },
/* 3 */ { 0, &BX_CPU_C::BxError },
/* 4 */ { 0, &BX_CPU_C::BxError },
@ -3044,7 +3044,7 @@ static const BxOpcodeInfo_t BxOpcodeInfoG7R[8] = {
/* 3 */ { 0, &BX_CPU_C::BxError },
/* 4 */ { 0, &BX_CPU_C::SMSW_Ew },
/* 5 */ { 0, &BX_CPU_C::BxError },
/* 6 */ { 0, &BX_CPU_C::LMSW_Ew },
/* 6 */ { BxTraceEnd, &BX_CPU_C::LMSW_Ew },
/* 7 */ { 0, &BX_CPU_C::BxError }
};
@ -3052,12 +3052,12 @@ static const BxOpcodeInfo_t BxOpcodeInfoG7M[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::SGDT_Ms },
/* 1 */ { 0, &BX_CPU_C::SIDT_Ms },
/* 2 */ { 0, &BX_CPU_C::LGDT_Ms },
/* 3 */ { 0, &BX_CPU_C::LIDT_Ms },
/* 2 */ { BxTraceEnd, &BX_CPU_C::LGDT_Ms },
/* 3 */ { BxTraceEnd, &BX_CPU_C::LIDT_Ms },
/* 4 */ { 0, &BX_CPU_C::SMSW_Ew },
/* 5 */ { 0, &BX_CPU_C::BxError },
/* 6 */ { 0, &BX_CPU_C::LMSW_Ew },
/* 7 */ { 0, &BX_CPU_C::INVLPG }
/* 6 */ { BxTraceEnd, &BX_CPU_C::LMSW_Ew },
/* 7 */ { BxTraceEnd, &BX_CPU_C::INVLPG }
};
#if BX_SUPPORT_X86_64
@ -3079,19 +3079,19 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G7R[8] = {
/* 3 */ { 0, &BX_CPU_C::BxError },
/* 4 */ { 0, &BX_CPU_C::SMSW_Ew },
/* 5 */ { 0, &BX_CPU_C::BxError },
/* 6 */ { 0, &BX_CPU_C::LMSW_Ew },
/* 6 */ { BxTraceEnd, &BX_CPU_C::LMSW_Ew },
/* 7 */ { BxRMGroup, NULL, opcodesGroup64RmINVLPG }
};
static const BxOpcodeInfo_t BxOpcodeInfo64G7M[8] = {
/* 0 */ { 0, &BX_CPU_C::SGDT64_Ms },
/* 1 */ { 0, &BX_CPU_C::SIDT64_Ms },
/* 2 */ { 0, &BX_CPU_C::LGDT64_Ms },
/* 3 */ { 0, &BX_CPU_C::LIDT64_Ms },
/* 2 */ { BxTraceEnd, &BX_CPU_C::LGDT64_Ms },
/* 3 */ { BxTraceEnd, &BX_CPU_C::LIDT64_Ms },
/* 4 */ { 0, &BX_CPU_C::SMSW_Ew },
/* 5 */ { 0, &BX_CPU_C::BxError },
/* 6 */ { 0, &BX_CPU_C::LMSW_Ew },
/* 7 */ { 0, &BX_CPU_C::INVLPG }
/* 6 */ { BxTraceEnd, &BX_CPU_C::LMSW_Ew },
/* 7 */ { BxTraceEnd, &BX_CPU_C::INVLPG }
};
#endif

712
bochs/cpu/fetchdecode64.cc
View File

File diff suppressed because it is too large Load Diff

13
bochs/cpu/icache.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: icache.h,v 1.20 2007-12-04 17:34:20 sshwarts Exp $
// $Id: icache.h,v 1.21 2007-12-09 18:36:05 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -115,12 +115,21 @@ extern bxPageWriteStampTable pageWriteStampTable;
#define BxICacheEntries (32 * 1024) // Must be a power of 2.
#if BX_SUPPORT_TRACE_CACHE
#define BX_MAX_TRACE_LENGTH 16
#endif
struct bxICacheEntry_c
{
bx_phy_address pAddr; // Physical address of the instruction
Bit32u writeStamp; // Generation ID. Each write to a physical page
// decrements this value
bxInstruction_c i; // The instruction decode information
#if BX_SUPPORT_TRACE_CACHE
Bit32u ilen; // Trace length in instructions
bxInstruction_c i[BX_MAX_TRACE_LENGTH];
#else
bxInstruction_c i;
#endif
};
class BOCHSAPI bxICache_c {

3
bochs/main.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: main.cc,v 1.368 2007-11-20 18:36:26 sshwarts Exp $
// $Id: main.cc,v 1.369 2007-12-09 18:36:00 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -1003,6 +1003,7 @@ void bx_init_hardware()
BX_INFO((" Guest2HostTLB support: %s",BX_SupportGuest2HostTLB?"yes":"no"));
BX_INFO((" RepeatSpeedups support: %s",BX_SupportRepeatSpeedups?"yes":"no"));
BX_INFO((" Icache support: %s",BX_SUPPORT_ICACHE?"yes":"no"));
BX_INFO((" Trace cache support: %s",BX_SUPPORT_TRACE_CACHE?"yes":"no"));
BX_INFO((" Fast function calls: %s",BX_FAST_FUNC_CALL?"yes":"no"));
BX_INFO(("Devices configuration"));
BX_INFO((" ACPI support: %s",BX_SUPPORT_ACPI?"yes":"no"));