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Little bit optimize memory access functions. Now values are calculated only if they actually needed.

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This commit is contained in:
Stanislav Shwartsman 2004-09-13 20:48:11 +00:00
parent 6663dec9d1
commit 6cdb42d909
5 changed files with 126 additions and 192 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

278
bochs/cpu/access.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: access.cc,v 1.45 2004-08-13 20:00:02 sshwarts Exp $
// $Id: access.cc,v 1.46 2004-09-13 20:48:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -303,24 +303,19 @@ accessOK:
#if BX_SupportGuest2HostTLB
{
bx_address lpf;
Bit32u tlbIndex, pageOffset;
pageOffset = laddr & 0xfff;
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = LPFOf(laddr);
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
bx_address lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf)))
{
Bit32u accessBits;
bx_hostpageaddr_t hostPageAddr;
Bit8u *hostAddr;
{
// See if the TLB entry privilege level allows us write access
// from this CPL.
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
Bit32u accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
bx_hostpageaddr_t hostPageAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
Bit32u pageOffset = laddr & 0xfff;
Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
@ -369,25 +364,19 @@ accessOK:
#if BX_SupportGuest2HostTLB
{
bx_address lpf;
Bit32u tlbIndex, pageOffset;
pageOffset = laddr & 0xfff;
Bit32u pageOffset = laddr & 0xfff;
if (pageOffset <= 0xffe) { // Make sure access does not span 2 pages.
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf))
) {
Bit32u accessBits;
bx_hostpageaddr_t hostPageAddr;
Bit16u *hostAddr;
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
bx_address lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf)))
{
// See if the TLB entry privilege level allows us write access
// from this CPL.
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
Bit32u accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
bx_hostpageaddr_t hostPageAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
@ -437,25 +426,20 @@ accessOK:
#if BX_SupportGuest2HostTLB
{
bx_address lpf;
Bit32u tlbIndex, pageOffset;
pageOffset = laddr & 0xfff;
Bit32u pageOffset = laddr & 0xfff;
if (pageOffset <= 0xffc) { // Make sure access does not span 2 pages.
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf))
) {
Bit32u accessBits;
bx_hostpageaddr_t hostPageAddr;
Bit32u *hostAddr;
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
bx_address lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf)))
{
// See if the TLB entry privilege level allows us write access
// from this CPL.
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
Bit32u accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
bx_hostpageaddr_t hostPageAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
@ -505,23 +489,17 @@ accessOK:
#if BX_SupportGuest2HostTLB
{
bx_address lpf;
Bit32u tlbIndex, pageOffset;
pageOffset = laddr & 0xfff;
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = LPFOf(laddr);
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
bx_address lpf = LPFOf(laddr);
if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf)) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
Bit32u accessBits;
bx_hostpageaddr_t hostPageAddr;
Bit8u *hostAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
Bit32u accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1<<pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
Bit32u pageOffset = laddr & 0xfff;
Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
if (hostPageAddr) {
*data = *hostAddr;
return;
@ -557,24 +535,18 @@ accessOK:
#if BX_SupportGuest2HostTLB
{
bx_address lpf;
Bit32u tlbIndex, pageOffset;
pageOffset = laddr & 0xfff;
Bit32u pageOffset = laddr & 0xfff;
if (pageOffset <= 0xffe) { // Make sure access does not span 2 pages.
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = LPFOf(laddr);
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
bx_address lpf = LPFOf(laddr);
if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf)) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
Bit32u accessBits;
bx_hostpageaddr_t hostPageAddr;
Bit16u *hostAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
Bit32u accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1<<pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
if (hostPageAddr) {
ReadHostWordFromLittleEndian(hostAddr, *data);
return;
@ -611,24 +583,18 @@ accessOK:
#if BX_SupportGuest2HostTLB
{
bx_address lpf;
Bit32u tlbIndex, pageOffset;
pageOffset = laddr & 0xfff;
Bit32u pageOffset = laddr & 0xfff;
if (pageOffset <= 0xffc) { // Make sure access does not span 2 pages.
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = LPFOf(laddr);
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
bx_address lpf = LPFOf(laddr);
if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf)) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
Bit32u accessBits;
bx_hostpageaddr_t hostPageAddr;
Bit32u *hostAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
Bit32u accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1<<pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
if (hostPageAddr) {
ReadHostDWordFromLittleEndian(hostAddr, *data);
return;
@ -670,24 +636,18 @@ accessOK:
#if BX_SupportGuest2HostTLB
{
bx_address lpf;
Bit32u tlbIndex, pageOffset;
pageOffset = laddr & 0xfff;
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf))
) {
Bit32u accessBits;
bx_hostpageaddr_t hostPageAddr;
Bit8u *hostAddr;
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
bx_address lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf)))
{
// See if the TLB entry privilege level allows us write access
// from this CPL.
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
Bit32u accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
bx_hostpageaddr_t hostPageAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
Bit32u pageOffset = laddr & 0xfff;
Bit8u *hostAddr = (Bit8u*) (hostPageAddr | pageOffset);
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
@ -740,25 +700,19 @@ accessOK:
#if BX_SupportGuest2HostTLB
{
bx_address lpf;
Bit32u tlbIndex, pageOffset;
pageOffset = laddr & 0xfff;
Bit32u pageOffset = laddr & 0xfff;
if (pageOffset <= 0xffe) { // Make sure access does not span 2 pages.
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf))
) {
Bit32u accessBits;
bx_hostpageaddr_t hostPageAddr;
Bit16u *hostAddr;
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
bx_address lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf)))
{
// See if the TLB entry privilege level allows us write access
// from this CPL.
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
Bit32u accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
bx_hostpageaddr_t hostPageAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset);
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
@ -809,25 +763,19 @@ accessOK:
#if BX_SupportGuest2HostTLB
{
bx_address lpf;
Bit32u tlbIndex, pageOffset;
pageOffset = laddr & 0xfff;
Bit32u pageOffset = laddr & 0xfff;
if (pageOffset <= 0xffc) { // Make sure access does not span 2 pages.
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf))
) {
Bit32u accessBits;
bx_hostpageaddr_t hostPageAddr;
Bit32u *hostAddr;
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
bx_address lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf)))
{
// See if the TLB entry privilege level allows us write access
// from this CPL.
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
Bit32u accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
bx_hostpageaddr_t hostPageAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
@ -865,8 +813,8 @@ BX_CPU_C::write_RMW_virtual_byte(Bit8u val8)
{
if (BX_CPU_THIS_PTR address_xlation.pages > 2) {
// Pages > 2 means it stores a host address for direct access.
Bit8u * hostAddr = (Bit8u *) BX_CPU_THIS_PTR address_xlation.pages;
* hostAddr = val8;
Bit8u *hostAddr = (Bit8u *) BX_CPU_THIS_PTR address_xlation.pages;
*hostAddr = val8;
}
else {
// address_xlation.pages must be 1
@ -955,25 +903,19 @@ accessOK:
#if BX_SupportGuest2HostTLB
{
bx_address lpf;
Bit32u tlbIndex, pageOffset;
pageOffset = laddr & 0xfff;
Bit32u pageOffset = laddr & 0xfff;
if (pageOffset <= 0xff8) { // Make sure access does not span 2 pages.
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf))
) {
Bit32u accessBits;
bx_hostpageaddr_t hostPageAddr;
Bit64u *hostAddr;
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
bx_address lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf)))
{
// See if the TLB entry privilege level allows us write access
// from this CPL.
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
hostAddr = (Bit64u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
Bit32u accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
bx_hostpageaddr_t hostPageAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset);
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[
@ -1023,24 +965,18 @@ accessOK:
#if BX_SupportGuest2HostTLB
{
bx_address lpf;
Bit32u tlbIndex, pageOffset;
pageOffset = laddr & 0xfff;
Bit32u pageOffset = laddr & 0xfff;
if (pageOffset <= 0xff8) { // Make sure access does not span 2 pages.
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = LPFOf(laddr);
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
bx_address lpf = LPFOf(laddr);
if (BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf)) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
Bit32u accessBits;
bx_hostpageaddr_t hostPageAddr;
Bit64u *hostAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
hostAddr = (Bit64u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
Bit32u accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1<<pl)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset);
if (hostPageAddr) {
ReadHostQWordFromLittleEndian(hostAddr, *data);
return;
@ -1112,25 +1048,19 @@ accessOK:
#if BX_SupportGuest2HostTLB
{
bx_address lpf;
Bit32u tlbIndex, pageOffset;
pageOffset = laddr & 0xfff;
Bit32u pageOffset = laddr & 0xfff;
if (pageOffset <= 0xff8) { // Make sure access does not span 2 pages.
tlbIndex = BX_TLB_INDEX_OF(laddr);
lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf))
) {
Bit32u accessBits;
bx_hostpageaddr_t hostPageAddr;
Bit32u *hostAddr;
Bit32u tlbIndex = BX_TLB_INDEX_OF(laddr);
bx_address lpf = LPFOf(laddr);
if ((BX_CPU_THIS_PTR TLB.entry[tlbIndex].lpf == BX_TLB_LPF_VALUE(lpf)))
{
// See if the TLB entry privilege level allows us write access
// from this CPL.
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
Bit32u accessBits = BX_CPU_THIS_PTR TLB.entry[tlbIndex].accessBits;
if (accessBits & (1 << (2 | pl))) {
bx_hostpageaddr_t hostPageAddr;
hostPageAddr = BX_CPU_THIS_PTR TLB.entry[tlbIndex].hostPageAddr;
Bit64u *hostAddr = (Bit64u*) (hostPageAddr | pageOffset);
#if BX_SUPPORT_ICACHE
Bit32u *pageStamp;
pageStamp = & BX_CPU_THIS_PTR iCache.pageWriteStampTable[

22
bochs/cpu/cpu.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.86 2004-07-29 20:30:14 sshwarts Exp $
// $Id: cpu.cc,v 1.87 2004-09-13 20:48:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -197,11 +197,10 @@ printf("CPU_LOOP %d\n", bx_guard.special_unwind_stack);
}
#if BX_SUPPORT_ICACHE
unsigned iCacheHash;
Bit32u pAddr, pageWriteStamp;
pAddr = BX_CPU_THIS_PTR pAddrA20Page + eipBiased;
iCacheHash = BX_CPU_THIS_PTR iCache.hash(pAddr);
unsigned iCacheHash = BX_CPU_THIS_PTR iCache.hash(pAddr);
i = & BX_CPU_THIS_PTR iCache.entry[iCacheHash].i;
pageWriteStamp = BX_CPU_THIS_PTR iCache.pageWriteStampTable[pAddr>>12];
@ -222,10 +221,10 @@ printf("CPU_LOOP %d\n", bx_guard.special_unwind_stack);
BX_INSTR_OPCODE(BX_CPU_ID, BX_CPU_THIS_PTR eipFetchPtr + eipBiased,
i->ilen(), BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b);
#endif
}
}
else
#endif
{
{
// iCache miss. No validated instruction with matching fetch parameters
// is in the iCache. Or we're not compiling iCache support in, in which
// case we always have an iCache miss. :^)
@ -298,9 +297,11 @@ printf("CPU_LOOP %d\n", bx_guard.special_unwind_stack);
}
#endif
// decoding instruction compeleted -> continue with execution
BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID);
if ( !(i->repUsedL() && i->repeatableL()) ) {
// non repeating instruction
BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID);
RIP += i->ilen();
BX_CPU_CALL_METHOD(execute, (i));
BX_CPU_THIS_PTR prev_eip = RIP; // commit new EIP
@ -312,10 +313,8 @@ printf("CPU_LOOP %d\n", bx_guard.special_unwind_stack);
#endif
BX_TICK1_IF_SINGLE_PROCESSOR();
}
}
else {
BX_INSTR_BEFORE_EXECUTION(BX_CPU_ID);
repeat_loop:
if (i->repeatableZFL()) {
@ -432,7 +431,6 @@ debugger_check:
#endif
#if BX_DEBUGGER
// BW vm mode switch support is in dbg_is_begin_instr_bpoint
// note instr generating exceptions never reach this point.
@ -735,9 +733,7 @@ BX_CPU_C::prefetch(void)
temp_rip = RIP;
temp_limit = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled;
laddr = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base +
temp_rip;
laddr = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base + temp_rip;
if (((Bit32u)temp_rip) > temp_limit) {
BX_PANIC(("prefetch: RIP > CS.limit"));

10
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.175 2004-09-06 20:22:37 sshwarts Exp $
// $Id: cpu.h,v 1.176 2004-09-13 20:48:10 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -82,6 +82,14 @@
#define BX_32BIT_REG_ESI 6
#define BX_32BIT_REG_EDI 7
#define BX_64BIT_REG_RAX 0
#define BX_64BIT_REG_RCX 1
#define BX_64BIT_REG_RDX 2
#define BX_64BIT_REG_RBX 3
#define BX_64BIT_REG_RSP 4
#define BX_64BIT_REG_RBP 5
#define BX_64BIT_REG_RSI 6
#define BX_64BIT_REG_RDI 7
#if defined(NEED_CPU_REG_SHORTCUTS)

4
bochs/cpu/data_xfer32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer32.cc,v 1.30 2004-08-13 20:00:03 sshwarts Exp $
// $Id: data_xfer32.cc,v 1.31 2004-09-13 20:48:11 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -101,7 +101,7 @@ BX_CPU_C::LEA_GdM(bxInstruction_c *i)
void
BX_CPU_C::MOV_EAXOd(bxInstruction_c *i)
{
BX_CLEAR_64BIT_HIGH(BX_32BIT_REG_EAX); /* RAX register */
BX_CLEAR_64BIT_HIGH(BX_64BIT_REG_RAX);
/* read from memory address */
if (!BX_NULL_SEG_REG(i->seg())) {

4
bochs/cpu/logical64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: logical64.cc,v 1.11 2004-08-13 20:00:03 sshwarts Exp $
// $Id: logical64.cc,v 1.12 2004-09-13 20:48:11 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -383,7 +383,7 @@ BX_CPU_C::TEST_RAXId(bxInstruction_c *i)
/* op1 is RAX register */
op1_64 = RAX;
/* op2 is imm64 */
/* op2 is imm32 */
op2_64 = (Bit32s) i->Id();
result_64 = op1_64 & op2_64;