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Fixed CR3 restore in RSM instruction

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Added HALT state indication (actually make existant one working for single CPU)
This commit is contained in:
Stanislav Shwartsman 2006-04-10 19:05:21 +00:00
parent df70fa0a2f
commit d972e4a4b7
6 changed files with 18 additions and 20 deletions
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6
bochs/cpu/apic.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: apic.cc,v 1.82 2006-04-07 20:47:31 sshwarts Exp $
// $Id: apic.cc,v 1.83 2006-04-10 19:05:21 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -481,8 +481,8 @@ void bx_local_apic_c::receive_EOI(Bit32u value)
void bx_local_apic_c::startup_msg(Bit32u vector)
{
if(cpu->debug_trap & 0x80000000) {
cpu->debug_trap &= ~0x80000000;
if(cpu->debug_trap & BX_DEBUG_TRAP_HALT_STATE) {
cpu->debug_trap &= ~BX_DEBUG_TRAP_HALT_STATE;
cpu->dword.eip = 0;
cpu->load_seg_reg(&cpu->sregs[BX_SEG_REG_CS], vector*0x100);
BX_INFO(("%s started up at %04X:%08X by APIC", cpu->name, vector*0x100, cpu->dword.eip));

13
bochs/cpu/cpu.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.143 2006-04-07 20:47:31 sshwarts Exp $
// $Id: cpu.cc,v 1.144 2006-04-10 19:05:21 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -503,12 +503,9 @@ unsigned BX_CPU_C::handleAsyncEvent(void)
//
// This area is where we process special conditions and events.
//
if (BX_CPU_THIS_PTR debug_trap & 0x80000000) {
if (BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_HALT_STATE) {
// I made up the bitmask above to mean HALT state.
#if BX_SUPPORT_SMP == 0
BX_CPU_THIS_PTR debug_trap = 0; // clear traps for after resume
BX_CPU_THIS_PTR inhibit_mask = 0; // clear inhibits for after resume
// for one processor, pass the time as quickly as possible until
// an interrupt wakes up the CPU.
#if BX_DEBUGGER
@ -521,10 +518,12 @@ unsigned BX_CPU_C::handleAsyncEvent(void)
BX_CPU_THIS_PTR nmi_pending || BX_CPU_THIS_PTR smi_pending)
{
// interrupt ends the HALT condition
BX_CPU_THIS_PTR debug_trap = 0; // clear traps for after resume
BX_CPU_THIS_PTR inhibit_mask = 0; // clear inhibits for after resume
break;
}
if (BX_CPU_THIS_PTR async_event == 2) {
BX_INFO(("decode: reset detected in halt state"));
if ((BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_HALT_STATE) == 0) {
BX_INFO(("handleAsyncEvent: reset detected in HLT state"));
break;
}
BX_TICK1();

3
bochs/cpu/cpu.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.278 2006-04-07 20:47:32 sshwarts Exp $
// $Id: cpu.h,v 1.279 2006-04-10 19:05:21 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1141,6 +1141,7 @@ public: // for now...
* 0 if current CS:IP caused exception */
unsigned errorno; /* signal exception during instruction emulation */
#define BX_DEBUG_TRAP_HALT_STATE (0x80000000)
Bit32u debug_trap; // holds DR6 value to be set as well
volatile bx_bool async_event;
volatile bx_bool INTR;

6
bochs/cpu/init.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: init.cc,v 1.96 2006-04-05 17:31:31 sshwarts Exp $
// $Id: init.cc,v 1.97 2006-04-10 19:05:21 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -732,11 +732,9 @@ void BX_CPU_C::reset(unsigned source)
// it's an application processor, halt until IPI is heard.
BX_CPU_THIS_PTR msr.apicbase &= ~0x0100; /* clear bit 8 BSP */
BX_INFO(("CPU[%d] is an application processor. Halting until IPI.", apic_id));
debug_trap |= 0x80000000;
debug_trap |= BX_DEBUG_TRAP_HALT_STATE;
async_event = 1;
}
#else
BX_CPU_THIS_PTR async_event=2;
#endif
BX_INSTR_RESET(BX_CPU_ID);

6
bochs/cpu/proc_ctrl.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: proc_ctrl.cc,v 1.145 2006-04-07 20:47:32 sshwarts Exp $
// $Id: proc_ctrl.cc,v 1.146 2006-04-10 19:05:21 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -73,7 +73,7 @@ void BX_CPU_C::shutdown(void)
BX_CPU_THIS_PTR clear_IF();
// artificial trap bit, why use another variable.
BX_CPU_THIS_PTR debug_trap |= 0x80000000; // artificial trap
BX_CPU_THIS_PTR debug_trap |= BX_DEBUG_TRAP_HALT_STATE; // artificial trap
BX_CPU_THIS_PTR async_event = 1; // so processor knows to check
// Execution of this instruction completes. The processor
// will remain in a halt state until one of the above conditions
@ -110,7 +110,7 @@ void BX_CPU_C::HLT(bxInstruction_c *i)
// following HLT.
// artificial trap bit, why use another variable.
BX_CPU_THIS_PTR debug_trap |= 0x80000000; // artificial trap
BX_CPU_THIS_PTR debug_trap |= BX_DEBUG_TRAP_HALT_STATE; // artificial trap
BX_CPU_THIS_PTR async_event = 1; // so processor knows to check
// Execution of this instruction completes. The processor
// will remain in a halt state until one of the above conditions

4
bochs/cpu/smm.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: smm.cc,v 1.15 2006-04-06 18:30:05 sshwarts Exp $
// $Id: smm.cc,v 1.16 2006-04-10 19:05:21 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006 Stanislav Shwartsman
@ -411,7 +411,7 @@ bx_bool BX_CPU_C::smram_restore_state(const Bit32u *saved_state)
SetCR0(temp_cr0);
setEFlags(temp_eflags);
bx_phy_address temp_cr3 = SMRAM_FIELD64(saved_state, SMRAM_OFFSET_RAX_HI32, SMRAM_OFFSET_RAX_LO32);
bx_phy_address temp_cr3 = SMRAM_FIELD(saved_state, SMRAM_OFFSET_CR3);
CR3_change(temp_cr3);
RAX = SMRAM_FIELD64(saved_state, SMRAM_OFFSET_RAX_HI32, SMRAM_OFFSET_RAX_LO32);