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small trace/iacache cleanups, always allow speculative tracing for trace cache

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This commit is contained in:
Stanislav Shwartsman 2008-03-03 14:35:36 +00:00
parent 47a36880e8
commit 2172e96654
5 changed files with 19 additions and 30 deletions
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3
bochs/config.h.in
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@ -733,10 +733,9 @@ typedef
#define BX_SUPPORT_ICACHE 0
#define BX_SUPPORT_TRACE_CACHE 0
#define BX_TRACE_CACHE_NO_SPECULATIVE_TRACING 0 /* allow speculative tracing */
#if (BX_SUPPORT_TRACE_CACHE && BX_SUPPORT_ICACHE==0)
#error Trace cache optimizatin cannot be compiled without iCache!
#error Trace cache optimization cannot be compiled without iCache!
#endif
// if 1, don't do gpf on MSRs that we don't implement

7
bochs/cpu/cpu.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.208 2008-02-29 05:39:38 sshwarts Exp $
// $Id: cpu.cc,v 1.209 2008-03-03 14:35:36 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -61,8 +61,6 @@
void BX_CPU_C::cpu_loop(Bit32u max_instr_count)
{
bxInstruction_c iStorage BX_CPP_AlignN(32);
#if BX_DEBUGGER
BX_CPU_THIS_PTR break_point = 0;
BX_CPU_THIS_PTR magic_break = 0;
@ -123,11 +121,12 @@ no_async_event:
}
#if BX_SUPPORT_TRACE_CACHE == 0
bxInstruction_c iStorage BX_CPP_AlignN(32);
// fetch and decode single instruction
bxInstruction_c *i = fetchInstruction(&iStorage, eipBiased);
#else
unsigned length;
bxInstruction_c *i = fetchInstructionTrace(&iStorage, &length, eipBiased);
bxInstruction_c *i = fetchInstructionTrace(eipBiased, &length);
Bit32u currPageWriteStamp = *(BX_CPU_THIS_PTR currPageWriteStampPtr);
for(;;i++) {

4
bochs/cpu/cpu.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.429 2008-02-29 03:02:02 sshwarts Exp $
// $Id: cpu.h,v 1.430 2008-03-03 14:35:36 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -2757,7 +2757,7 @@ public: // for now...
BX_SMF unsigned fetchDecode64(Bit8u *fetchPtr, bxInstruction_c *i, unsigned remainingInPage);
#endif
#if BX_SUPPORT_TRACE_CACHE
BX_SMF bxInstruction_c* fetchInstructionTrace(bxInstruction_c *iStorage, unsigned *len, Bit32u eipBiased);
BX_SMF bxInstruction_c* fetchInstructionTrace(Bit32u eipBiased, unsigned *len);
BX_SMF bx_bool mergeTraces(bxICacheEntry_c *trace, bxInstruction_c *, bx_phy_address pAddr);
BX_SMF void instrumentTraces(void);
#else

30
bochs/cpu/icache.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: icache.cc,v 1.5 2008-02-02 21:46:51 sshwarts Exp $
// $Id: icache.cc,v 1.6 2008-03-03 14:35:36 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007 Stanislav Shwartsman
@ -83,7 +83,7 @@ static Bit32u iCacheTraceLengh[BX_MAX_TRACE_LENGTH];
#if BX_SUPPORT_TRACE_CACHE
bxInstruction_c* BX_CPU_C::fetchInstructionTrace(bxInstruction_c *iStorage, unsigned *len, Bit32u eipBiased)
bxInstruction_c* BX_CPU_C::fetchInstructionTrace(Bit32u eipBiased, unsigned *len)
{
bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrA20Page + eipBiased;
unsigned iCacheHash = BX_CPU_THIS_PTR iCache.hash(pAddr);
@ -116,7 +116,7 @@ bxInstruction_c* BX_CPU_C::fetchInstructionTrace(bxInstruction_c *iStorage, unsi
bxInstruction_c *i = trace->i;
for (unsigned n=0;n<BX_MAX_TRACE_LENGTH;n++,i++)
for (unsigned n=0;n<BX_MAX_TRACE_LENGTH;n++)
{
#if BX_SUPPORT_X86_64
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
@ -136,10 +136,9 @@ bxInstruction_c* BX_CPU_C::fetchInstructionTrace(bxInstruction_c *iStorage, unsi
// First instruction is boundary fetch, return iStorage and leave
// the trace cache entry invalid (do not cache the instruction)
trace->writeStamp = ICacheWriteStampInvalid;
boundaryFetch(fetchPtr, remainingInPage, iStorage);
*len = 1;
return iStorage;
trace->ilen = 1;
boundaryFetch(fetchPtr, remainingInPage, trace->i);
break;
}
// add instruction to the trace ...
@ -148,22 +147,13 @@ bxInstruction_c* BX_CPU_C::fetchInstructionTrace(bxInstruction_c *iStorage, unsi
// ... and continue to the next instruction
remainingInPage -= iLen;
if (remainingInPage == 0) break;
if (i->getStopTraceAttr() || remainingInPage == 0) break;
pAddr += iLen;
fetchPtr += iLen;
if (i->getStopTraceAttr()) {
#if BX_TRACE_CACHE_NO_SPECULATIVE_TRACING
unsigned b1 = i->b1() & 0x1f0;
if (b1 == 0x70 || b1 == 0x180) { // JCC instruction
mergeTraces(trace, i+1, pAddr);
}
#endif
break;
}
i++;
// try to find a trace starting from current pAddr and merge
if (mergeTraces(trace, i+1, pAddr)) break;
if (mergeTraces(trace, i, pAddr)) break;
}
*len = trace->ilen;
@ -230,7 +220,7 @@ bxInstruction_c* BX_CPU_C::fetchInstruction(bxInstruction_c *iStorage, Bit32u ei
bx_phy_address pAddr = BX_CPU_THIS_PTR pAddrA20Page + eipBiased;
unsigned iCacheHash = BX_CPU_THIS_PTR iCache.hash(pAddr);
bxICacheEntry_c *cache_entry = &(BX_CPU_THIS_PTR iCache.entry[iCacheHash]);
i = &(cache_entry->i);
i = cache_entry->i;
Bit32u pageWriteStamp = *(BX_CPU_THIS_PTR currPageWriteStampPtr);

5
bochs/cpu/icache.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: icache.h,v 1.25 2008-02-02 21:46:51 sshwarts Exp $
// $Id: icache.h,v 1.26 2008-03-03 14:35:36 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -129,7 +129,8 @@ struct bxICacheEntry_c
Bit32u ilen; // Trace length in instructions
bxInstruction_c i[BX_MAX_TRACE_LENGTH];
#else
bxInstruction_c i;
// ... define as array of 1 to simplify merge with trace cache code
bxInstruction_c i[1];
#endif
};