Use LOAD_Eb approach to remove duplicated GbEb methods
This commit is contained in:
Stanislav Shwartsman
parent
a8adb36dc2
commit
70c7c5ceca
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: arith8.cc,v 1.59 2008-08-08 09:22:46 sshwarts Exp $
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// $Id: arith8.cc,v 1.60 2008-08-11 20:34:05 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -44,20 +44,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EbGbM(bxInstruction_c *i)
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SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GbEbM(bxInstruction_c *i)
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{
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Bit8u op1, op2, sum;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
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op2 = read_virtual_byte(i->seg(), eaddr);
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sum = op1 + op2;
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BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), sum);
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SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GbEbR(bxInstruction_c *i)
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{
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Bit8u op1, op2, sum;
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@ -97,21 +83,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EbGbM(bxInstruction_c *i)
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SET_FLAGS_OSZAPC_8(op1, op2, sum, BX_LF_INSTR_ADD_ADC8(temp_CF));
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GbEbM(bxInstruction_c *i)
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{
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Bit8u op1, op2, sum;
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bx_bool temp_CF = getB_CF();
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
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op2 = read_virtual_byte(i->seg(), eaddr);
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sum = op1 + op2 + temp_CF;
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BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), sum);
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SET_FLAGS_OSZAPC_8(op1, op2, sum, BX_LF_INSTR_ADD_ADC8(temp_CF));
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GbEbR(bxInstruction_c *i)
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{
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Bit8u op1, op2, sum;
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@ -153,21 +124,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EbGbM(bxInstruction_c *i)
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SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_LF_INSTR_SUB_SBB8(temp_CF));
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GbEbM(bxInstruction_c *i)
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{
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Bit8u op1_8, op2_8, diff_8;
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bx_bool temp_CF = getB_CF();
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
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op2_8 = read_virtual_byte(i->seg(), eaddr);
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diff_8 = op1_8 - (op2_8 + temp_CF);
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BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), diff_8);
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SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_LF_INSTR_SUB_SBB8(temp_CF));
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GbEbR(bxInstruction_c *i)
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{
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Bit8u op1_8, op2_8, diff_8;
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@ -234,20 +190,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EbGbM(bxInstruction_c *i)
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SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GbEbM(bxInstruction_c *i)
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{
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Bit8u op1_8, op2_8, diff_8;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
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op2_8 = read_virtual_byte(i->seg(), eaddr);
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diff_8 = op1_8 - op2_8;
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BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), diff_8);
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SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GbEbR(bxInstruction_c *i)
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{
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Bit8u op1_8, op2_8, diff_8;
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@ -285,19 +227,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EbGbM(bxInstruction_c *i)
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SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GbEbM(bxInstruction_c *i)
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{
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Bit8u op1_8, op2_8, diff_8;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
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op2_8 = read_virtual_byte(i->seg(), eaddr);
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diff_8 = op1_8 - op2_8;
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SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GbEbR(bxInstruction_c *i)
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{
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Bit8u op1_8, op2_8, diff_8;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.505 2008-08-11 18:53:23 sshwarts Exp $
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// $Id: cpu.h,v 1.506 2008-08-11 20:34:05 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -117,7 +117,6 @@
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#define BH (BX_CPU_THIS_PTR gen_reg[3].word.byte.rh)
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#define TMP8L (BX_CPU_THIS_PTR gen_reg[BX_TMP_REGISTER].word.byte.rl)
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#define TMP8H (BX_CPU_THIS_PTR gen_reg[BX_TMP_REGISTER].word.byte.rh)
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// access to 16 bit general registers
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#define AX (BX_CPU_THIS_PTR gen_reg[0].word.rx)
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@ -185,14 +184,14 @@
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#endif
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#if BX_SUPPORT_X86_64
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#define BX_READ_8BIT_REGx(index,extended) ((((index) < 4) || (extended)) ? \
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#define BX_READ_8BIT_REGx(index,extended) ((((index) & 4) == 0 || (extended)) ? \
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(BX_CPU_THIS_PTR gen_reg[index].word.byte.rl) : \
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(BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh))
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#define BX_READ_64BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].rrx)
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#else
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#define BX_READ_8BIT_REG(index) (((index) < 4) ? \
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(BX_CPU_THIS_PTR gen_reg[index].word.byte.rl) : \
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(BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh))
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#define BX_READ_8BIT_REG(index) (((index) & 4) ? \
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(BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh)) : \
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(BX_CPU_THIS_PTR gen_reg[index].word.byte.rl)
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#define BX_READ_8BIT_REGx(index,ext) BX_READ_8BIT_REG(index)
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#endif
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@ -217,7 +216,7 @@
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#if BX_SUPPORT_X86_64
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#define BX_WRITE_8BIT_REGx(index, extended, val) {\
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if (((index) < 4) || (extended)) \
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if (((index) & 4) == 0 || (extended)) \
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BX_CPU_THIS_PTR gen_reg[index].word.byte.rl = val; \
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else \
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BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh = val; \
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@ -237,10 +236,10 @@
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#else
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#define BX_WRITE_8BIT_REG(index, val) {\
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if ((index) < 4) \
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BX_CPU_THIS_PTR gen_reg[index].word.byte.rl = val; \
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else \
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if ((index) & 4) \
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BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh = val; \
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else \
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BX_CPU_THIS_PTR gen_reg[index].word.byte.rl = val; \
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}
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#define BX_WRITE_8BIT_REGx(index, ext, val) BX_WRITE_8BIT_REG(index, val)
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@ -1126,10 +1125,6 @@ public: // for now...
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BX_SMF void TEST_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void XCHG_EbGbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void XCHG_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void XCHG_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1443,15 +1438,6 @@ public: // for now...
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BX_SMF void BSWAP_ERX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void ADD_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void OR_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void ADC_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SBB_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void AND_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SUB_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void XOR_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CMP_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void ADD_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void OR_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void ADC_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1608,20 +1594,17 @@ public: // for now...
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BX_SMF void SHR_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SAR_EdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EwIwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EdIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EbIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EwIwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MUL_ALEb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void IMUL_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void IMUL_ALEb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void IMUL_GdEdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void DIV_ALEb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void IDIV_ALEb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MUL_ALEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void IMUL_ALEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void DIV_ALEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void IDIV_ALEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MUL_EAXEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void IMUL_EAXEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1665,6 +1648,7 @@ public: // for now...
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BX_SMF void LMSW_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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// service methods
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BX_SMF void LOAD_Eb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_Ed(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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#if BX_SUPPORT_X86_64
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@ -2430,7 +2414,6 @@ public: // for now...
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BX_SMF void CMP_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void XCHG_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -2588,7 +2571,6 @@ public: // for now...
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BX_SMF void NOT_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void NEG_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EqIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void TEST_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MUL_RAXEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: data_xfer.cc,v 1.3 2008-08-10 19:34:28 sshwarts Exp $
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// $Id: data_xfer.cc,v 1.4 2008-08-11 20:34:05 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2008 Stanislav Shwartsman
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@ -26,6 +26,13 @@
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Eb(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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TMP8L = read_virtual_byte(i->seg(), eaddr);
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BX_CPU_CALL_METHOD(i->execute2, (i));
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Ew(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.h,v 1.73 2008-08-11 18:53:23 sshwarts Exp $
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// $Id: fetchdecode.h,v 1.74 2008-08-11 20:34:05 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005 Stanislav Shwartsman
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@ -3232,10 +3232,10 @@ static const BxOpcodeInfo_t BxOpcodeInfoG3EbM[8] = {
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/* 1 */ { BxImmediate_Ib, BX_IA_TEST_EbIbM },
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/* 2 */ { BxLockable, BX_IA_NOT_EbM },
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/* 3 */ { BxLockable, BX_IA_NEG_EbM },
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/* 4 */ { 0, BX_IA_MUL_ALEb },
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/* 5 */ { 0, BX_IA_IMUL_ALEb },
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/* 6 */ { 0, BX_IA_DIV_ALEb },
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/* 7 */ { 0, BX_IA_IDIV_ALEb }
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/* 4 */ { 0, BX_IA_MUL_ALEbM },
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/* 5 */ { 0, BX_IA_IMUL_ALEbM },
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/* 6 */ { 0, BX_IA_DIV_ALEbM },
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/* 7 */ { 0, BX_IA_IDIV_ALEbM }
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};
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static const BxOpcodeInfo_t BxOpcodeInfoG3EbR[8] = {
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@ -3243,10 +3243,10 @@ static const BxOpcodeInfo_t BxOpcodeInfoG3EbR[8] = {
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/* 1 */ { BxImmediate_Ib, BX_IA_TEST_EbIbR },
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/* 2 */ { 0, BX_IA_NOT_EbR },
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/* 3 */ { 0, BX_IA_NEG_EbR },
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/* 4 */ { 0, BX_IA_MUL_ALEb },
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/* 5 */ { 0, BX_IA_IMUL_ALEb },
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/* 6 */ { 0, BX_IA_DIV_ALEb },
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/* 7 */ { 0, BX_IA_IDIV_ALEb }
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/* 4 */ { 0, BX_IA_MUL_ALEbR },
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/* 5 */ { 0, BX_IA_IMUL_ALEbR },
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/* 6 */ { 0, BX_IA_DIV_ALEbR },
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/* 7 */ { 0, BX_IA_IDIV_ALEbR }
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};
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static const BxOpcodeInfo_t BxOpcodeInfoG3EwM[8] = {
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: ia_opcodes.h,v 1.16 2008-08-11 18:53:23 sshwarts Exp $
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// $Id: ia_opcodes.h,v 1.17 2008-08-11 20:34:05 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2008 Stanislav Shwartsman
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@ -44,7 +44,7 @@ bx_define_opcode(BX_IA_ADC_EwGwM, &BX_CPU_C::ADC_EwGwM, NULL, 0)
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bx_define_opcode(BX_IA_ADC_EwGwR, &BX_CPU_C::ADC_GwEwR, NULL, BxArithDstRM)
|
||||
bx_define_opcode(BX_IA_ADC_EwIwM, &BX_CPU_C::ADC_EwIwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_ADC_EwIwR, &BX_CPU_C::ADC_EwIwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GbEbM, &BX_CPU_C::ADC_GbEbM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GbEbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::ADC_GbEbR, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GbEbR, &BX_CPU_C::ADC_GbEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GdEdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::ADC_GdEdR, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GdEdR, &BX_CPU_C::ADC_GdEdR, NULL, 0)
|
||||
@ -65,7 +65,7 @@ bx_define_opcode(BX_IA_ADD_EwGwM, &BX_CPU_C::ADD_EwGwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_ADD_EwGwR, &BX_CPU_C::ADD_GwEwR, NULL, BxArithDstRM)
|
||||
bx_define_opcode(BX_IA_ADD_EwIwM, &BX_CPU_C::ADD_EwIwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_ADD_EwIwR, &BX_CPU_C::ADD_EwIwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_ADD_GbEbM, &BX_CPU_C::ADD_GbEbM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_ADD_GbEbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::ADD_GbEbR, 0)
|
||||
bx_define_opcode(BX_IA_ADD_GbEbR, &BX_CPU_C::ADD_GbEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_ADD_GdEdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::ADD_GdEdR, 0)
|
||||
bx_define_opcode(BX_IA_ADD_GdEdR, &BX_CPU_C::ADD_GdEdR, NULL, 0)
|
||||
@ -86,7 +86,7 @@ bx_define_opcode(BX_IA_AND_EwGwM, &BX_CPU_C::AND_EwGwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_AND_EwGwR, &BX_CPU_C::AND_GwEwR, NULL, BxArithDstRM)
|
||||
bx_define_opcode(BX_IA_AND_EwIwM, &BX_CPU_C::AND_EwIwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_AND_EwIwR, &BX_CPU_C::AND_EwIwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_AND_GbEbM, &BX_CPU_C::AND_GbEbM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_AND_GbEbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::AND_GbEbR, 0)
|
||||
bx_define_opcode(BX_IA_AND_GbEbR, &BX_CPU_C::AND_GbEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_AND_GdEdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::AND_GdEdR, 0)
|
||||
bx_define_opcode(BX_IA_AND_GdEdR, &BX_CPU_C::AND_GdEdR, NULL, 0)
|
||||
@ -234,7 +234,7 @@ bx_define_opcode(BX_IA_CMP_EwGwM, &BX_CPU_C::CMP_EwGwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CMP_EwGwR, &BX_CPU_C::CMP_GwEwR, NULL, BxArithDstRM)
|
||||
bx_define_opcode(BX_IA_CMP_EwIwM, &BX_CPU_C::CMP_EwIwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CMP_EwIwR, &BX_CPU_C::CMP_EwIwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GbEbM, &BX_CPU_C::CMP_GbEbM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GbEbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::CMP_GbEbR, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GbEbR, &BX_CPU_C::CMP_GbEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GdEdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::CMP_GdEdR, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GdEdR, &BX_CPU_C::CMP_GdEdR, NULL, 0)
|
||||
@ -260,7 +260,8 @@ bx_define_opcode(BX_IA_DEC_ERX, &BX_CPU_C::DEC_ERX, NULL, 0)
|
||||
bx_define_opcode(BX_IA_DEC_EwR, &BX_CPU_C::DEC_RX, NULL, 0)
|
||||
bx_define_opcode(BX_IA_DEC_EwM, &BX_CPU_C::DEC_EwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_DEC_RX, &BX_CPU_C::DEC_RX, NULL, 0)
|
||||
bx_define_opcode(BX_IA_DIV_ALEb, &BX_CPU_C::DIV_ALEb, NULL, 0)
|
||||
bx_define_opcode(BX_IA_DIV_ALEbR, &BX_CPU_C::DIV_ALEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_DIV_ALEbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::DIV_ALEbR, 0)
|
||||
bx_define_opcode(BX_IA_DIV_AXEwR, &BX_CPU_C::DIV_AXEwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_DIV_AXEwM, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::DIV_AXEwR, 0)
|
||||
bx_define_opcode(BX_IA_DIV_EAXEdR, &BX_CPU_C::DIV_EAXEdR, NULL, 0)
|
||||
@ -268,12 +269,14 @@ bx_define_opcode(BX_IA_DIV_EAXEdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::DIV_EAXEdR, 0)
|
||||
bx_define_opcode(BX_IA_ENTER16_IwIb, &BX_CPU_C::ENTER16_IwIb, NULL, 0)
|
||||
bx_define_opcode(BX_IA_ENTER32_IwIb, &BX_CPU_C::ENTER32_IwIb, NULL, 0)
|
||||
bx_define_opcode(BX_IA_HLT, &BX_CPU_C::HLT, NULL, 0)
|
||||
bx_define_opcode(BX_IA_IDIV_ALEb, &BX_CPU_C::IDIV_ALEb, NULL, 0)
|
||||
bx_define_opcode(BX_IA_IDIV_ALEbR, &BX_CPU_C::IDIV_ALEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_IDIV_ALEbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::IDIV_ALEbR, 0)
|
||||
bx_define_opcode(BX_IA_IDIV_AXEwR, &BX_CPU_C::IDIV_AXEwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_IDIV_AXEwM, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::IDIV_AXEwR, 0)
|
||||
bx_define_opcode(BX_IA_IDIV_EAXEdR, &BX_CPU_C::IDIV_EAXEdR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_IDIV_EAXEdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::IDIV_EAXEdR, 0)
|
||||
bx_define_opcode(BX_IA_IMUL_ALEb, &BX_CPU_C::IMUL_ALEb, NULL, 0)
|
||||
bx_define_opcode(BX_IA_IMUL_ALEbR, &BX_CPU_C::IMUL_ALEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_IMUL_ALEbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::IMUL_ALEbR, 0)
|
||||
bx_define_opcode(BX_IA_IMUL_AXEwR, &BX_CPU_C::IMUL_AXEwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_IMUL_AXEwM, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::IMUL_AXEwR, 0)
|
||||
bx_define_opcode(BX_IA_IMUL_EAXEdR, &BX_CPU_C::IMUL_EAXEdR, NULL, 0)
|
||||
@ -429,7 +432,8 @@ bx_define_opcode(BX_IA_MOVZX_GdEwM, &BX_CPU_C::MOVZX_GdEwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_MOVZX_GdEwR, &BX_CPU_C::MOVZX_GdEwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_MOVZX_GwEbM, &BX_CPU_C::MOVZX_GwEbM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_MOVZX_GwEbR, &BX_CPU_C::MOVZX_GwEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_MUL_ALEb, &BX_CPU_C::MUL_ALEb, NULL, 0)
|
||||
bx_define_opcode(BX_IA_MUL_ALEbR, &BX_CPU_C::MUL_ALEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_MUL_ALEbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::MUL_ALEbR, 0)
|
||||
bx_define_opcode(BX_IA_MUL_AXEwR, &BX_CPU_C::MUL_AXEwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_MUL_AXEwM, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::MUL_AXEwR, 0)
|
||||
bx_define_opcode(BX_IA_MUL_EAXEdR, &BX_CPU_C::MUL_EAXEdR, NULL, 0)
|
||||
@ -462,7 +466,7 @@ bx_define_opcode(BX_IA_OR_EwGwM, &BX_CPU_C::OR_EwGwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_OR_EwGwR, &BX_CPU_C::OR_GwEwR, NULL, BxArithDstRM)
|
||||
bx_define_opcode(BX_IA_OR_EwIwM, &BX_CPU_C::OR_EwIwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_OR_EwIwR, &BX_CPU_C::OR_EwIwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_OR_GbEbM, &BX_CPU_C::OR_GbEbM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_OR_GbEbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::OR_GbEbR, 0)
|
||||
bx_define_opcode(BX_IA_OR_GbEbR, &BX_CPU_C::OR_GbEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_OR_GdEdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::OR_GdEdR, 0)
|
||||
bx_define_opcode(BX_IA_OR_GdEdR, &BX_CPU_C::OR_GdEdR, NULL, 0)
|
||||
@ -596,7 +600,7 @@ bx_define_opcode(BX_IA_SBB_EwGwM, &BX_CPU_C::SBB_EwGwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_SBB_EwGwR, &BX_CPU_C::SBB_GwEwR, NULL, BxArithDstRM)
|
||||
bx_define_opcode(BX_IA_SBB_EwIwM, &BX_CPU_C::SBB_EwIwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_SBB_EwIwR, &BX_CPU_C::SBB_EwIwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GbEbM, &BX_CPU_C::SBB_GbEbM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GbEbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::SBB_GbEbR, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GbEbR, &BX_CPU_C::SBB_GbEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GdEdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::SBB_GdEdR, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GdEdR, &BX_CPU_C::SBB_GdEdR, NULL, 0)
|
||||
@ -670,7 +674,7 @@ bx_define_opcode(BX_IA_SUB_EwGwM, &BX_CPU_C::SUB_EwGwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_SUB_EwGwR, &BX_CPU_C::SUB_GwEwR, NULL, BxArithDstRM)
|
||||
bx_define_opcode(BX_IA_SUB_EwIwM, &BX_CPU_C::SUB_EwIwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_SUB_EwIwR, &BX_CPU_C::SUB_EwIwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GbEbM, &BX_CPU_C::SUB_GbEbM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GbEbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::SUB_GbEbR, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GbEbR, &BX_CPU_C::SUB_GbEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GdEdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::SUB_GdEdR, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GdEdR, &BX_CPU_C::SUB_GdEdR, NULL, 0)
|
||||
@ -681,17 +685,17 @@ bx_define_opcode(BX_IA_SYSEXIT, &BX_CPU_C::SYSEXIT, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_ALIb, &BX_CPU_C::TEST_ALIb, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_AXIw, &BX_CPU_C::TEST_AXIw, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EAXId, &BX_CPU_C::TEST_EAXId, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EbGbM, &BX_CPU_C::TEST_EbGbM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EbGbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::TEST_EbGbR, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EbGbR, &BX_CPU_C::TEST_EbGbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EbIbM, &BX_CPU_C::TEST_EbIbM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EbIbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::TEST_EbIbR, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EbIbR, &BX_CPU_C::TEST_EbIbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EdGdM, &BX_CPU_C::TEST_EdGdM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EdGdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::TEST_EdGdR, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EdGdR, &BX_CPU_C::TEST_EdGdR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EdIdM, &BX_CPU_C::TEST_EdIdM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EdIdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::TEST_EdIdR, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EdIdR, &BX_CPU_C::TEST_EdIdR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EwGwM, &BX_CPU_C::TEST_EwGwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EwGwM, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::TEST_EwGwR, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EwGwR, &BX_CPU_C::TEST_EwGwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EwIwM, &BX_CPU_C::TEST_EwIwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EwIwM, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::TEST_EwIwR, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EwIwR, &BX_CPU_C::TEST_EwIwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_UD2A, &BX_CPU_C::UndefinedOpcode, NULL, 0)
|
||||
bx_define_opcode(BX_IA_UD2B, &BX_CPU_C::UndefinedOpcode, NULL, 0)
|
||||
@ -729,7 +733,7 @@ bx_define_opcode(BX_IA_XOR_EwGwM, &BX_CPU_C::XOR_EwGwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_XOR_EwGwR, &BX_CPU_C::XOR_GwEwR, NULL, BxArithDstRM)
|
||||
bx_define_opcode(BX_IA_XOR_EwIwM, &BX_CPU_C::XOR_EwIwM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_XOR_EwIwR, &BX_CPU_C::XOR_EwIwR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GbEbM, &BX_CPU_C::XOR_GbEbM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GbEbM, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::XOR_GbEbR, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GbEbR, &BX_CPU_C::XOR_GbEbR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GdEdM, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::XOR_GdEdR, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GdEdR, &BX_CPU_C::XOR_GdEdR, NULL, 0)
|
||||
@ -1351,7 +1355,7 @@ bx_define_opcode(BX_IA_SUB_EqIdR, &BX_CPU_C::SUB_EqIdR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_XOR_EqIdR, &BX_CPU_C::XOR_EqIdR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_CMP_EqIdR, &BX_CPU_C::CMP_EqIdR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EqGqR, &BX_CPU_C::TEST_EqGqR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EqGqM, &BX_CPU_C::TEST_EqGqM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EqGqM, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::TEST_EqGqR, 0)
|
||||
bx_define_opcode(BX_IA_TEST_RAXId, &BX_CPU_C::TEST_RAXId, NULL, 0)
|
||||
bx_define_opcode(BX_IA_XCHG_EqGqR, &BX_CPU_C::XCHG_EqGqR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_XCHG_EqGqM, &BX_CPU_C::XCHG_EqGqM, NULL, 0)
|
||||
@ -1482,7 +1486,7 @@ bx_define_opcode(BX_IA_NOT_EqM, &BX_CPU_C::NOT_EqM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_NEG_EqM, &BX_CPU_C::NEG_EqM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_NOT_EqR, &BX_CPU_C::NOT_EqR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_NEG_EqR, &BX_CPU_C::NEG_EqR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EqIdM, &BX_CPU_C::TEST_EqIdM, NULL, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EqIdM, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::TEST_EqIdR, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EqIdR, &BX_CPU_C::TEST_EqIdR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_MUL_RAXEqR, &BX_CPU_C::MUL_RAXEqR, NULL, 0)
|
||||
bx_define_opcode(BX_IA_MUL_RAXEqM, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::MUL_RAXEqR, 0)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: logical16.cc,v 1.41 2008-08-09 21:05:06 sshwarts Exp $
|
||||
// $Id: logical16.cc,v 1.42 2008-08-11 20:34:05 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -227,18 +227,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwIwR(bxInstruction_c *i)
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwGwM(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, op2_16;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_16 = read_virtual_word(i->seg(), eaddr);
|
||||
op2_16 = BX_READ_16BIT_REG(i->nnn());
|
||||
op1_16 &= op2_16;
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwGwR(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, op2_16;
|
||||
@ -260,15 +248,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_AXIw(bxInstruction_c *i)
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwIwM(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
Bit16u op1_16 = read_virtual_word(i->seg(), eaddr);
|
||||
op1_16 &= i->Iw();
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwIwR(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: logical32.cc,v 1.42 2008-08-09 21:05:07 sshwarts Exp $
|
||||
// $Id: logical32.cc,v 1.43 2008-08-11 20:34:05 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -232,19 +232,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdIdR(bxInstruction_c *i)
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdGdM(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, op2_32;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_32 = read_virtual_dword(i->seg(), eaddr);
|
||||
op2_32 = BX_READ_32BIT_REG(i->nnn());
|
||||
op1_32 &= op2_32;
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdGdR(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, op2_32;
|
||||
@ -267,15 +254,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EAXId(bxInstruction_c *i)
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdIdM(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
Bit32u op1_32 = read_virtual_dword(i->seg(), eaddr);
|
||||
op1_32 &= i->Id();
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdIdR(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: logical64.cc,v 1.31 2008-08-09 21:05:07 sshwarts Exp $
|
||||
// $Id: logical64.cc,v 1.32 2008-08-11 20:34:05 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -244,19 +244,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EqIdR(bxInstruction_c *i)
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqGqM(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_64 = read_virtual_qword_64(i->seg(), eaddr);
|
||||
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
||||
op1_64 &= op2_64;
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqGqR(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64;
|
||||
@ -279,19 +266,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_RAXId(bxInstruction_c *i)
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqIdM(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_64 = read_virtual_qword_64(i->seg(), eaddr);
|
||||
op2_64 = (Bit32s) i->Id();
|
||||
op1_64 &= op2_64;
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqIdR(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: logical8.cc,v 1.41 2008-08-08 09:22:47 sshwarts Exp $
|
||||
// $Id: logical8.cc,v 1.42 2008-08-11 20:34:05 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -44,20 +44,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EbGbM(bxInstruction_c *i)
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GbEbM(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1, op2;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
op2 = read_virtual_byte(i->seg(), eaddr);
|
||||
op1 ^= op2;
|
||||
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GbEbR(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1, op2;
|
||||
@ -161,20 +147,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EbGbM(bxInstruction_c *i)
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GbEbM(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1, op2;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
op2 = read_virtual_byte(i->seg(), eaddr);
|
||||
op1 |= op2;
|
||||
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GbEbR(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1, op2;
|
||||
@ -213,20 +185,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EbGbM(bxInstruction_c *i)
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GbEbM(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1, op2;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
op2 = read_virtual_byte(i->seg(), eaddr);
|
||||
op1 &= op2;
|
||||
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GbEbR(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1, op2;
|
||||
@ -275,19 +233,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EbIbR(bxInstruction_c *i)
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbGbM(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1, op2;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1 = read_virtual_byte(i->seg(), eaddr);
|
||||
op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
op1 &= op2;
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbGbR(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1, op2;
|
||||
@ -310,15 +255,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_ALIb(bxInstruction_c *i)
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbIbM(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
Bit8u op1 = read_virtual_byte(i->seg(), eaddr);
|
||||
op1 &= i->Ib();
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbIbR(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: mult8.cc,v 1.30 2008-08-08 09:22:47 sshwarts Exp $
|
||||
// $Id: mult8.cc,v 1.31 2008-08-11 20:34:05 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -30,21 +30,10 @@
|
||||
#include "cpu.h"
|
||||
#define LOG_THIS BX_CPU_THIS_PTR
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MUL_ALEb(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MUL_ALEbR(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op2, op1;
|
||||
|
||||
op1 = AL;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op2 = read_virtual_byte(i->seg(), eaddr);
|
||||
}
|
||||
Bit8u op1 = AL;
|
||||
Bit8u op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
|
||||
|
||||
Bit32u product_16 = ((Bit16u) op1) * ((Bit16u) op2);
|
||||
|
||||
@ -62,21 +51,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MUL_ALEb(bxInstruction_c *i)
|
||||
}
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_ALEb(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_ALEbR(bxInstruction_c *i)
|
||||
{
|
||||
Bit8s op2, op1;
|
||||
|
||||
op1 = AL;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op2 = (Bit8s) read_virtual_byte(i->seg(), eaddr);
|
||||
}
|
||||
Bit8s op1 = AL;
|
||||
Bit8s op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
|
||||
|
||||
Bit16s product_16 = op1 * op2;
|
||||
Bit8u product_8 = (product_16 & 0xFF);
|
||||
@ -96,30 +74,18 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_ALEb(bxInstruction_c *i)
|
||||
}
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::DIV_ALEb(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::DIV_ALEbR(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op2, quotient_8l, remainder_8;
|
||||
Bit16u quotient_16, op1;
|
||||
|
||||
op1 = AX;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op2 = read_virtual_byte(i->seg(), eaddr);
|
||||
}
|
||||
|
||||
Bit8u op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
|
||||
if (op2 == 0) {
|
||||
exception(BX_DE_EXCEPTION, 0, 0);
|
||||
}
|
||||
|
||||
quotient_16 = op1 / op2;
|
||||
remainder_8 = op1 % op2;
|
||||
quotient_8l = quotient_16 & 0xFF;
|
||||
Bit16u op1 = AX;
|
||||
|
||||
Bit16u quotient_16 = op1 / op2;
|
||||
Bit8u remainder_8 = op1 % op2;
|
||||
Bit8u quotient_8l = quotient_16 & 0xFF;
|
||||
|
||||
if (quotient_16 != quotient_8l)
|
||||
{
|
||||
@ -131,33 +97,22 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DIV_ALEb(bxInstruction_c *i)
|
||||
AH = remainder_8;
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::IDIV_ALEb(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::IDIV_ALEbR(bxInstruction_c *i)
|
||||
{
|
||||
Bit8s op2, quotient_8l, remainder_8;
|
||||
Bit16s quotient_16, op1;
|
||||
|
||||
op1 = AX;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op2 = (Bit8s) read_virtual_byte(i->seg(), eaddr);
|
||||
}
|
||||
|
||||
if (op2 == 0)
|
||||
exception(BX_DE_EXCEPTION, 0, 0);
|
||||
Bit16s op1 = AX;
|
||||
|
||||
/* check MIN_INT case */
|
||||
if (op1 == ((Bit16s)0x8000))
|
||||
exception(BX_DE_EXCEPTION, 0, 0);
|
||||
|
||||
quotient_16 = op1 / op2;
|
||||
remainder_8 = op1 % op2;
|
||||
quotient_8l = quotient_16 & 0xFF;
|
||||
Bit8s op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
|
||||
|
||||
if (op2 == 0)
|
||||
exception(BX_DE_EXCEPTION, 0, 0);
|
||||
|
||||
Bit16s quotient_16 = op1 / op2;
|
||||
Bit8s remainder_8 = op1 % op2;
|
||||
Bit8s quotient_8l = quotient_16 & 0xFF;
|
||||
|
||||
if (quotient_16 != quotient_8l)
|
||||
exception(BX_DE_EXCEPTION, 0, 0);
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user