mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
10,979 Commits 11 Branches 185 Tags 48 MiB
b60d7d3154
Commit Graph

3160 Commits

Author SHA1 Message Date
Stanislav Shwartsman
85b0402668 fixes for disasm 2013-10-02 19:23:34 +00:00
Stanislav Shwartsman
8c60799e72 fix for new disasm interface 2013-10-01 20:17:21 +00:00
Stanislav Shwartsman
e592f81209 updates to internal disasm 2013-10-01 18:47:55 +00:00
Stanislav Shwartsman
147d788022 few fixes in new disasm module 2013-09-30 20:16:52 +00:00
Stanislav Shwartsman
fd383435f0 - Initial code for bx_Instruction_c disassembler which (together with Bochs decoder) will replace Bochs disasm module someday (very soon). 
The code already knows to disasm most of the opcodes with their operands.

- Split according to OSIZE opcodes RDFSBASE/WRFSBASE / RDGSBASE/WRGSBASE both for disasm and performance

- Minimize amount of opcode forms in ia_opcodes.h again.
  For example Udq means the same as Wdq but with no memory form.
 2013-09-30 19:01:42 +00:00
Stanislav Shwartsman
fa06b26c88 Make possible to deliver instruction name for disasm directly from bx_ia_opcode_name (some opcodes were renamed). 
Fixed bug in stack optimization in 64-bit mode (should result in some speedup)
ia_opcode.h - eliminate some OP_M cases when they actually meant "value of specific type in the memory"
example: "MOVBE Md, Gd" actually means "MOVBE Ed, Gd"which just not have reg/reg form.
 2013-09-26 18:54:32 +00:00
Stanislav Shwartsman
839b841c38 added register type to register source information in decoder 2013-09-24 09:50:25 +00:00
Stanislav Shwartsman
ff79cbd596 Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm) 
The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm.

Two bug fixes on the way:
TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit)
BMI2: fixed operands order for PEXT/PDEP instructions
AVX2: fixed gather instruction decoding bug from decoder alias commit
 2013-09-24 05:21:00 +00:00
Stanislav Shwartsman
f791802286 infrastructure change for several AVX handlers to support any VL and only 128/256 2013-09-21 20:40:57 +00:00
Stanislav Shwartsman
404b8b1475 move end of trace indication to separate 'flags' field of bx_ia_opcode. this saves a lot of code duplication and simplifies the decode tables. also on the way found missing SVM opcodes that missed 'end of trace' mark 2013-09-21 18:58:01 +00:00
Stanislav Shwartsman
047b17d415 fixed typo in makefile 2013-09-21 10:52:18 +00:00
Stanislav Shwartsman
cd55ace8c8 fixed compilation err, rename opcode and handler functions for PUSHA/POPA instructions 2013-09-21 10:03:49 +00:00
Stanislav Shwartsman
2526282ed9 small additions for avx512 2013-09-20 18:27:33 +00:00
Stanislav Shwartsman
3803ac7fbe fixed evex override mscsr controls 2013-09-19 21:38:25 +00:00
Stanislav Shwartsman
0441f82b02 implement more AVX512 instructions 2013-09-19 20:35:55 +00:00
Stanislav Shwartsman
55f9155bc5 add new file 2013-09-19 18:32:39 +00:00
Stanislav Shwartsman
8b3a0acde9 implement first EVEX instructions - VADDPS/PD/SS/SD 2013-09-19 18:31:30 +00:00
Stanislav Shwartsman
8e71a86542 seve vex prefix value to the indication of vex prefix used 2013-09-18 18:01:48 +00:00
Stanislav Shwartsman
da0e2baf22 avoid segfault when decoding incorrectly encoded kmask op 2013-09-17 21:01:24 +00:00
Stanislav Shwartsman
d169860f6c added masked operations to simd_pfp.h, optimize simd_int.h, rewrite dpps instr using new masked op from simd_pfp.h 2013-09-17 20:49:26 +00:00
Stanislav Shwartsman
aa25c1db6a name convention change - search and replace 2013-09-17 17:34:20 +00:00
Stanislav Shwartsman
b6c39a3176 merge AVX and SSE .bochsrc options to single SIMD option which will configure SSE and AVX together 2013-09-16 19:50:36 +00:00
Stanislav Shwartsman
1cebe5f83d rellback part of commit with xmm register access interface changes - doesn't work for big endian hosts 2013-09-16 19:10:42 +00:00
Stanislav Shwartsman
0cb0acc30f added evex decode tables - next step to populate them :) 2013-09-15 20:48:39 +00:00
Stanislav Shwartsman
1e1fa45cac fixed makefile after file rename 2013-09-08 20:16:38 +00:00
Stanislav Shwartsman
e4a99b4294 rename avx512_mask.cc 2013-09-08 20:15:52 +00:00
Stanislav Shwartsman
132714bf29 fixed compilation w/o EVEX support enabled 2013-09-08 19:45:46 +00:00
Stanislav Shwartsman
8881800b1f enable avx-512 in init.cc 2013-09-08 19:35:37 +00:00
Stanislav Shwartsman
7297323c69 First step of AVX512 support implementation (simplest) 
decode and implement KMASK manipulation instructions
disasm: coming soon
 2013-09-08 19:19:16 +00:00
Stanislav Shwartsman
6ddfe5fc3b reorg avx opcodes in ia_opcodes.h. place v128 and v256 opcodes together. todo: find way to merge them sometimes 2013-09-07 18:52:31 +00:00
Stanislav Shwartsman
a6b85d9443 compress xop tables for vex.l - smaller binary size 2013-09-06 18:56:46 +00:00
Stanislav Shwartsman
0fd4e3450c update (c) for few files 2013-09-05 18:40:14 +00:00
Stanislav Shwartsman
2c9cf33b2f update (c) for few files 2013-09-05 18:37:10 +00:00
Stanislav Shwartsman
69f947cef2 fixes and small optimizations for avx and xop decoding 2013-09-05 18:29:50 +00:00
Stanislav Shwartsman
f36364bc65 it doesn't matter if it was vex or xop ... 2013-09-05 17:52:47 +00:00
Volker Ruppert
7c0a261751 final fix for BX_CPU_LEVEL 4 2013-09-05 06:42:17 +00:00
Stanislav Shwartsman
897bf85494 fixed bug in fma4 decoding - found now thanks to new tables re-org 2013-09-04 18:37:49 +00:00
Stanislav Shwartsman
2f957bf142 re-arrange AVX/XOP table to avoid redundant multiplication in decode. TODO: compress the tables 2x using aliases 2013-09-04 18:36:01 +00:00
Stanislav Shwartsman
bb695fd5f5 remove redundant (and incorrect) check 2013-09-04 16:47:52 +00:00
Stanislav Shwartsman
81affbe328 fixed incorrect lock prefix detection 2013-08-30 20:08:04 +00:00
Stanislav Shwartsman
c2558f52d6 generic_cpuid: fixed xsave cpuid leaf when xsave is disabled (need to clear output) 2013-08-29 19:58:31 +00:00
Stanislav Shwartsman
59c65151f5 various fixes 2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
7e2ab5ca81 decode simplification for AMD XOP prefix 2013-08-28 19:56:19 +00:00
Stanislav Shwartsman
5d61c19b0b evex support - step2 2013-08-27 20:47:24 +00:00
Stanislav Shwartsman
5fe5bf1ed6 fixed alias typo corrupting avx opcodes 2013-08-27 19:45:31 +00:00
Stanislav Shwartsman
c5f72033ad correct vzeroupper opcode 2013-08-27 06:57:48 +00:00
Stanislav Shwartsman
735154a755 oops, typo bug in prev commit 2013-08-24 19:46:04 +00:00
Stanislav Shwartsman
65e6760915 small decode optimization 2013-08-24 19:29:43 +00:00
Stanislav Shwartsman
748a0da712 one more step in the way towards avx-512 which have more vector registers 2013-08-24 12:12:10 +00:00
Stanislav Shwartsman
701d88388e fixed FCS/FDS deprecation 2013-08-22 20:21:36 +00:00
Stanislav Shwartsman
3a7e336cb6 more opcode alias - now VEX.W alias 2013-08-21 18:45:36 +00:00
Stanislav Shwartsman
115ec37a4c make decoder tables smaller using decode aliases 2013-08-21 04:52:49 +00:00
Stanislav Shwartsman
33a7063e60 bug fixes 2013-08-05 15:33:41 +00:00
Stanislav Shwartsman
362b99eba0 fixed typo in last commit 2013-08-04 19:47:19 +00:00
Stanislav Shwartsman
3fabcb00b7 VMX: CMPXHG instructions should always write to the memory destination, even if the value unchanged - it affects VMEXIT conditions for the full apic virtualization 
Fixed also CMPXHG16B instruction (last one, others were fixed earlier)
 2013-08-04 19:37:04 +00:00
Stanislav Shwartsman
7005afd3a8 clean up BxRepeatable attribute - not needed anymore after VL AVX field moved to new location 2013-07-26 15:42:49 +00:00
Stanislav Shwartsman
2dbe81db51 first infrastructure changes to support EVEX prefix and AVX-512 extensions recently published by Intel 2013-07-26 12:50:56 +00:00
Stanislav Shwartsman
0da1d659d3 CMPXHG should always write to memory dest - affects APIC virtualization VMEXIT conditions 2013-07-24 21:06:24 +00:00
Stanislav Shwartsman
54d3dc4353 properly added sha.cc to the tree 2013-07-24 18:56:37 +00:00
Stanislav Shwartsman
2357dc5ccc Fixed number of invocations of the BX_INSTR_LIN_ACCESS instrumentation callback in cpu/access32.cc, cpu/access64.cc and cpu/paging.cc specify the BX_READ memory access type where BX_RW really applies. 
SF Patch #1335 by Mateusz Jurczyk
 2013-07-24 18:54:18 +00:00
Stanislav Shwartsman
4c7031962e added new sha.cc file 2013-07-24 18:47:28 +00:00
Stanislav Shwartsman
852b5c3749 implemented SHA new instructions announced in recent Intel SDM extensions document rev015 2013-07-24 18:44:22 +00:00
Stanislav Shwartsman
fd71b03353 add some definitions introduced in recent Intel SDM extensions document (rev015) 2013-07-23 20:51:52 +00:00
Stanislav Shwartsman
4a36fb3edc fixed debug print message for BOUND instruction 2013-07-22 18:52:15 +00:00
Stanislav Shwartsman
148cb1aee0 Thanks to avanced trace linking 256K entries ICache is not needed anymore. 
Reduce to 64K entries and save memory.
 2013-06-29 10:25:56 +00:00
Stanislav Shwartsman
ef0d2142ab Allow cross-page trace linking again. 
The SMC problem was solved in following manner:

 - Every trace linked to another remembers when it was linked (a special timestamp value called traceLinkTimeStamp)
 - When true SMC happens it incremements the traceLinkTimeStamp
 - Jump to the linked trace won't be allowed if traceLinkTimeStamp in the link doesn't match traceLinkTimeStamp

So SMC effectively breaks all trace links and therefore I should not care for them anymore

5%-10% speedup on OS boot benchamarks observed
 2013-06-29 10:16:28 +00:00
Stanislav Shwartsman
0276bdfb3e still not allow cross page linking until SMC issue will be solved - cause Win98 crash 2013-06-28 07:51:42 +00:00
Stanislav Shwartsman
c42afb0a2d allow linking of traces cross 4K page boundary 2013-06-23 21:12:03 +00:00
Stanislav Shwartsman
91b3417e57 small bugfix 2013-06-23 15:45:25 +00:00
Stanislav Shwartsman
d30d1ac93a small bugfix 2013-06-21 14:12:46 +00:00
Stanislav Shwartsman
c7698a5589 implemented fcs/fds deprecation. added haswell to cpudb.h as well 2013-06-20 20:12:53 +00:00
Stanislav Shwartsman
b335f472bd Added Haswell configuration to CPUDB 2013-06-20 19:33:30 +00:00
Stanislav Shwartsman
769d35b06c remove debug print from Sandy Bridge CPUID wrongly commited 2013-06-15 17:57:03 +00:00
Stanislav Shwartsman
edc3003f35 do not use cpuid:level param when it doesn't exists 2013-06-15 17:53:49 +00:00
Stanislav Shwartsman
9651b5d53c bugfix: vmx preemption timer vmexit should not wakeup CPU from sleep state. cpuid: added definitions from recently published intel SDM rev047 2013-06-04 20:28:27 +00:00
Stanislav Shwartsman
b950de7155 add more vmx capabilities to generic cpu 2013-05-20 18:18:52 +00:00
Stanislav Shwartsman
964583a40f Added X2APIC support to Ivy Bridge configuration 2013-05-20 18:15:35 +00:00
Stanislav Shwartsman
2bca9b8273 updates in CPUID defines after new published AMD SDM 2013-05-17 19:41:57 +00:00
Stanislav Shwartsman
1304b3fb4b Do not report Architectural Performance Monitoring in CPUID 
Reporting true capabilities breaks Win7 x64 installation
 2013-05-07 15:34:58 +00:00
Stanislav Shwartsman
694dc8a0e1 fixed generic cpuid leafs - all std leafs > 2 were corrupted 2013-05-06 20:33:27 +00:00
Stanislav Shwartsman
b2b42dd714 small fix for LOAD_SS interrupts inhibit 2013-05-04 19:10:50 +00:00
Stanislav Shwartsman
139ec7d538 PANIC on options which require P6 when CPU_LEVEL is set to 5 instead of ignoring them 2013-04-17 20:24:12 +00:00
Stanislav Shwartsman
3fbdf7ff03 do not recognize MTRR MSRs when mtrr is not enabled 2013-04-17 19:59:56 +00:00
Stanislav Shwartsman
9b958b3a05 allow to select CPU level = 5 from .bochsrc even when Bochs is compiled with CPU_LEVEL=6 2013-04-17 19:46:11 +00:00
Stanislav Shwartsman
025fb15461 properly handle RDMSR/WRMSR of MSR_PAT when PAT feature is disabled 2013-04-11 19:41:54 +00:00
Stanislav Shwartsman
f1c7d163a1 activity state is ignored when vmenter injecting event 2013-04-09 20:36:02 +00:00
Stanislav Shwartsman
a277d60d89 implemented vmentering to non-active cpu state 2013-04-09 15:43:15 +00:00
Stanislav Shwartsman
6a8357105b fix for guest segment AR field size 2013-04-08 17:29:00 +00:00
Stanislav Shwartsman
13a6524acb hw task switch tempdr6 hanlding fix 2013-03-15 08:26:22 +00:00
Stanislav Shwartsman
913e3defd1 fixed SIPI delivery bug from one the latest checkins 2013-03-13 19:06:55 +00:00
Stanislav Shwartsman
53d14c01b5 correctly signal bit 12 (nmi unblocking by iret) in vmx interruption info. todo: find how to implement it clean way 2013-03-06 21:11:23 +00:00
Stanislav Shwartsman
1a770dd260 implementation of virtual NMI 2013-03-05 21:12:43 +00:00
Stanislav Shwartsman
39ae66b5a3 Suppress 'entering paged real mode' CR0 check for SVM guest 
After a lot of thinking and browsing in the SVM arch forums I assume now that it shold be fine to enter to paged real mode under SVM guest.
The test case to consider:

  (paged) real mode guest -> entering Pmode (not paged) -> disabling the Pmode back

Ths assumption still should be validated with real AMD hardware

Context: AMD's manual about CR0 intercept priority :
	"Checks non-memory exceptions (CPL, illegal bit combinations, etc.) before the intercept"

The check for 'paged real mode' suposed to be illegal bit combination ...
 2013-02-27 19:11:28 +00:00
Stanislav Shwartsman
ab63b22a68 SVM: implemented missed RSM, LDTR READ/WRITE, TR READ/WRITE and IRET intercepts 2013-02-25 19:36:41 +00:00
Stanislav Shwartsman
8708d05bea rename some VMX controls to match intel docs. added missed VMX consistency check 2013-02-24 20:22:22 +00:00
Volker Ruppert
058c0e05fb - removed wx debugger dialogs (enhanced gui debugger now almost stable with wx) 2013-02-16 12:22:13 +00:00
Stanislav Shwartsman
e43ac349a6 fixed injected exception err code check for unrestricted guests 2013-02-14 19:31:42 +00:00
Stanislav Shwartsman
40669115e1 use different formatter for printing phy address in paging dbg messages 2013-02-14 19:30:59 +00:00
Volker Ruppert
97de484efb use enhanced gui debugger instead of classic wx debugger if BX_DEBUGGER_GUI == 1 
The Windows version looks almost stable, but the GTK version fails in some cases.
That's why the classic wx debugger is still available if BX_DEBUGGER_GUI is set to 0.
- added function close_debug_dialog() to handle the simulation stop case in wx
- disable all the wx debugger related code if BX_DEBUGGER_GUI is set to 1
- added enhanced debugger specific init code similar to the code in sdl.cc
- include debugger related resources on Windows
- TODO: make the GTK / wxGTK case stable and remove the wx debugger
 2013-02-12 21:08:35 +00:00
Stanislav Shwartsman
ec971d0ce8 add #VE exception specific VMCS fields into VMCS bitmap 2013-01-28 20:20:54 +00:00
Stanislav Shwartsman
863e1a0f8a fixed compilation with debugger enabled 2013-01-28 18:26:56 +00:00
Stanislav Shwartsman
64df073617 implemented virtualization exception feature 2013-01-28 16:30:25 +00:00
Stanislav Shwartsman
d38fce8218 preparation for future extension in translate_linear - I would like to return data to caller through tlbEntry 2013-01-27 19:27:30 +00:00
Stanislav Shwartsman
016e112ac2 fixed compilation err with vmx=1 2013-01-23 19:04:53 +00:00
Stanislav Shwartsman
a0c9522fef fix compilation with no vmx enabled 2013-01-22 19:06:20 +00:00
Stanislav Shwartsman
8865df606a fixed typo bug in VMX code 2013-01-22 08:39:41 +00:00
Stanislav Shwartsman
608775cd5a vmread/vmwrite should always check for CPL, also when in vmx guest 2013-01-21 20:20:14 +00:00
Stanislav Shwartsman
3ab0331307 implemented VMCS shadowing (Intel SDM rev045) 2013-01-21 19:55:00 +00:00
Stanislav Shwartsman
9e896ce0bf SFENCE instruction doesn't require SSE2 2013-01-20 17:56:08 +00:00
Stanislav Shwartsman
4bed791ccb Added year 2013 to Copyright in all files already modified in new year 2013-01-19 20:45:03 +00:00
Stanislav Shwartsman
05d36f0acc fixed performance bug in smap/smep fix - tlb never had user executable page permission 2013-01-19 20:14:44 +00:00
Stanislav Shwartsman
eda28b95f4 unfortunately this change is rquired to make SMAP and SMEP features to work. 
I observed ~5% emulation slowdown ... thinking about possible mitigations

this fixes TLB issue with SMAP and SMEP features.
these features introduce a new behavior when page can be inaccessible by System (CPL=0).
Current behavior is accessBits was not supporting it but legacy (from Bochs 2.3.6) was.
The wrong behavior can be observed if user access a user page and system access the same page later.
user access is fine and pass SMEP/SMA checks and stores the translation in TLB.
the system access will hit the TLB and nobody could detect that system cannot access that page.
 2013-01-16 17:28:20 +00:00
Stanislav Shwartsman
c337b7babb Intel Software Developers Manual rev45 was released 
Added CPUID bits and preparations for newly documented VMX features
 2013-01-16 16:57:48 +00:00
Stanislav Shwartsman
c96f5e27a9 flush tlb also when cr4.smap changes 2013-01-14 17:02:51 +00:00
Stanislav Shwartsman
d93607cfe6 implemented pause threshold count in SVN + bugfix in SMAP 2013-01-08 21:03:22 +00:00
Stanislav Shwartsman
93d6c2e1fc added AMD Bulldozer architecture CPU (Zambezi) to CPUDB 2013-01-07 19:33:04 +00:00
Stanislav Shwartsman
c6b1f6c22b fixed IsValidPageAlignedPhyAddr check for VMX/SVM 2012-12-30 19:49:20 +00:00
Stanislav Shwartsman
685e0091b4 fixed decoding of RDRAND/RDSEED with 0x66 prefix 2012-12-27 19:31:21 +00:00
Stanislav Shwartsman
48d7fa3786 fixed code duplication, mainly in vmx/svm code 2012-12-26 21:59:16 +00:00
Stanislav Shwartsman
6e5a934eea XSAVE: Fixed XCR0 reserved combination checking in XSETBV instruction 2012-12-23 16:54:18 +00:00
Stanislav Shwartsman
ce2751a13c move misaligned_sse from compile time to .bochsrc option 2012-12-20 19:43:11 +00:00
Stanislav Shwartsman
db4d75317a fixed small avx issues 2012-12-11 21:01:05 +00:00
Stanislav Shwartsman
318ad5e26d optimize avx stores 2012-12-10 14:43:21 +00:00
Stanislav Shwartsman
182ad65ea3 changes in avx emulation code 2012-12-09 16:42:48 +00:00
Stanislav Shwartsman
574b69c81e fixed MSDEV warnings 2012-11-27 15:40:45 +00:00
Stanislav Shwartsman
64f9c12bbc name new CPUID bits from AMD 2012-11-10 11:00:09 +00:00
Stanislav Shwartsman
edf4ea4c74 fixed SF bug #1318 dbg: several issues with 'set' command 2012-11-06 20:01:02 +00:00
Stanislav Shwartsman
7bace61c12 fixed compilation issue 2012-11-05 06:41:10 +00:00
Stanislav Shwartsman
8a01ee1661 implemented SVM decode assists. some is still missing - coming soon 2012-11-02 07:46:50 +00:00
Stanislav Shwartsman
8d32f2e305 fixed another compilaton err in vapic 2012-10-28 18:32:58 +00:00
Stanislav Shwartsman
7e663e785e fix compilation err 2012-10-28 16:34:25 +00:00
Stanislav Shwartsman
744001e35e Implemented VMX APIC Registers Virtualization and VMX Virtual Interrupt Delivery emulation 
Bugfix: VMX: VmEntry should do TPR Virtualization (TPR Shadow + APIC Access Virtualization case is affected) and even could possibly cause TPR Threshold VMEXIT
 2012-10-26 18:43:53 +00:00
Stanislav Shwartsman
9b65cae026 make WRMSR end-of-trace instruction 2012-10-25 16:49:22 +00:00
Stanislav Shwartsman
4273b41d00 fixed write to apicbase when in x2apic mode 2012-10-25 16:09:34 +00:00
Stanislav Shwartsman
7e1b67f91e fixed bugs in vmx code 2012-10-25 16:08:28 +00:00
Stanislav Shwartsman
e4d659c54d fix compilation err 2012-10-25 16:07:11 +00:00
Stanislav Shwartsman
45d5d690d7 initialize random generator for RDRAND/RDSEED 2012-10-09 20:53:50 +00:00
Stanislav Shwartsman
2638c1136a Add RDRAND/RDSEED instructions support (+ disasm) 
Of course no true random numbers will be generated - use standard "C" rand() function as stub.
In future it will be possible to improve (using another random generator) or even use real rdrand/rdseed intrinsics
 2012-10-09 15:16:48 +00:00
Stanislav Shwartsman
e7a2c9892c re-implement VTPF write using event handling interface as trap event (in preparation to more apic virtualization features) 2012-10-07 09:16:13 +00:00
Stanislav Shwartsman
b0edc32f4c fixed compilation with VMX 2012-10-06 09:13:41 +00:00
Stanislav Shwartsman
c48e516386 implemented injection of MTF event. The MTF VMexec control is still not implemented yet 2012-10-05 20:48:22 +00:00
Stanislav Shwartsman
3cd11b02ee optimization and bugfix for prev commit 2012-10-04 21:30:50 +00:00
Stanislav Shwartsman
1b228aec32 Fixed double and triple fault detection in exception.cc. Remove errorno variable from CPU (redundant now) 2012-10-04 20:52:27 +00:00
Stanislav Shwartsman
f69bc016d2 vmx: nmi blocking after NMI event injection. better dbg print for VMEXIT 2012-10-04 16:15:58 +00:00
Stanislav Shwartsman
be1642e02e fixed compile with debugger enabled 2012-10-03 20:32:02 +00:00
Stanislav Shwartsman
2ca0c6c677 Move INTR, Local APIC INTR and SVN VINTR into new event interface (hardest part) 
Minor speedup (of 1-2%) was observed due to new implementation
Remove obsolete dbg_take_irq function and dbg_force_interrupt function from CPU code, the functions were not working properly anyway
 2012-10-03 20:24:29 +00:00
Stanislav Shwartsman
49bb3ba8f5 some cleanups and optimizations with new event interface 2012-10-03 15:49:45 +00:00
Stanislav Shwartsman
ae06a0825b svm virq - move to new event interface 2012-10-02 20:49:16 +00:00
Stanislav Shwartsman
9132c29280 optimization and code duplication cleanup in event handling code 2012-10-02 20:07:26 +00:00
Stanislav Shwartsman
dbb23aed43 close another SMC hole 2012-10-01 18:19:09 +00:00
Stanislav Shwartsman
3a6f649b18 fixed comment 2012-10-01 12:08:23 +00:00
Stanislav Shwartsman
e397a86ce0 fixed code duplication related to EXT field 2012-09-29 09:31:34 +00:00
Stanislav Shwartsman
dc369d831f small cleanup 2012-09-27 07:03:25 +00:00
Stanislav Shwartsman
8189a5ed20 fixed compilation with SMP 2012-09-26 16:00:49 +00:00
Stanislav Shwartsman
b2afa834c5 fixed compilation with intrumentation w/o x86-64 2012-09-25 20:48:46 +00:00
Stanislav Shwartsman
66a9a769fc fixed nmi window exiting 2012-09-25 20:00:33 +00:00
Stanislav Shwartsman
08d0ef6dbf fixes for new event handling code 2012-09-25 13:53:26 +00:00
Stanislav Shwartsman
d5f858d100 transfer VMX NMI window exiting into event vector infrastructure 2012-09-25 10:21:29 +00:00
Stanislav Shwartsman
40ba9c8d7b introducing new interface for handling CPU events based on vector of events and not on many not related variables. this is very initial implementation which takes into new interface only few events, more will code soon 2012-09-25 09:35:38 +00:00
Stanislav Shwartsman
f0c153e550 fixed warning 2012-09-24 19:53:49 +00:00
Stanislav Shwartsman
da150bc163 small optimization in icache 2012-09-23 19:35:46 +00:00
Stanislav Shwartsman
eb348992c2 optimize POPCNT implementation 2012-09-21 14:56:56 +00:00
Stanislav Shwartsman
74f5bb1934 WBINVD not necessary havw to flush ICACHE 2012-09-21 08:55:10 +00:00
Stanislav Shwartsman
f419798ca5 fixed reset value for mtrr 2012-09-15 19:52:11 +00:00
Stanislav Shwartsman
4f6557697b small comments updates in vmx code 2012-09-13 05:33:05 +00:00
Volker Ruppert
c2560a8d44 - fpu directory is now a subdirectory in 'cpu' 2012-09-12 21:08:40 +00:00
Stanislav Shwartsman
2c5165bc06 fix check of error_code feild on event injection 2012-09-12 04:12:58 +00:00
Stanislav Shwartsman
2f3c7ff8e4 implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14 
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc

Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
 2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
0386f49e03 fixed comments for SHLD/SHRD instructrions and make code a little more clear 2012-09-09 17:44:42 +00:00
Stanislav Shwartsman
7e48b30b5d fixed random freeze issues caused by commit rev11402 2012-09-06 19:51:33 +00:00
Stanislav Shwartsman
bff3ba1535 small optimization in lazy flags code 2012-09-06 19:49:14 +00:00
Stanislav Shwartsman
f1fd44b2cf preparations for apic regs virtualization feature described in SDM rev044 2012-09-06 15:21:08 +00:00
Stanislav Shwartsman
8044a2bda6 rename i->execute field in the instruction 
move victim cache lookup into cache lookup so traces could be linked with victim cache hits directly
 2012-09-04 15:45:05 +00:00
Stanislav Shwartsman
295e3ab8db fixed compilation warning 2012-09-02 18:38:04 +00:00
Stanislav Shwartsman
d1879b839e increase icache size 2012-09-01 19:13:01 +00:00
Stanislav Shwartsman
86a06ff9f6 more new vmx defines 2012-08-31 15:38:28 +00:00
Stanislav Shwartsman
2a459fb9be add more disclosed VMCS fields and vmexit codes to enums (from rev44 published today) 2012-08-31 09:25:13 +00:00
Stanislav Shwartsman
40a9992aa6 small cleanups 2012-08-28 16:05:39 +00:00
Stanislav Shwartsman
e17cffab57 simplify generated code 2012-08-26 15:49:30 +00:00
Stanislav Shwartsman
c41cbe6d56 Link traces over taken branch optimization which makes handlers chaining even more efficient. 
I observed 5% speedup in all disk images over 2.6pre1.
The change is safe (passed all regressions) and I will be glad to make it into Bochs 2.6!
 2012-08-21 19:58:41 +00:00
Stanislav Shwartsman
399168e37d small cleanup 2012-08-19 18:44:08 +00:00
Stanislav Shwartsman
dd7b968404 SSE cvt instructions: transition from FPU to MMX state has higher priority than SSE exception (#XF/#UD) 2012-08-11 07:41:13 +00:00
Stanislav Shwartsman
df90b80352 set of small cpu fixes 2012-08-09 13:11:25 +00:00
Stanislav Shwartsman
0c11901d6b fixed segment limit check for AVX mem access - same fix for stores 2012-08-08 20:43:07 +00:00
Stanislav Shwartsman
af9e072ad6 fixed segment limit check for AVX mem access 2012-08-08 20:39:36 +00:00
Stanislav Shwartsman
be76f38b46 correct MOVBE decoding with prefix 0x66, also correct ADX decoding 2012-08-08 20:11:27 +00:00
Stanislav Shwartsman
fee1000ba2 split PINSRB instruction to /r and /m form 2012-08-07 14:38:43 +00:00
Stanislav Shwartsman
cac261553d Fixed stupid typo which caused incorrect VMX instr info on LDTR/TR instruction VMEXIT 2012-08-06 20:41:16 +00:00
Stanislav Shwartsman
cc694377b9 Standartization of Bochs instruction handlers. 
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.

Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code

Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)

Huge patch. Almost all source files wre modified.
 2012-08-05 13:52:40 +00:00
Stanislav Shwartsman
4d03b57291 Allow larger quantum value for SMP simulations (up to 32) 
Update CHANGES
 2012-08-02 20:48:27 +00:00
Stanislav Shwartsman
d5c5c8e9e1 fixed bug produced by SVN commit rev11299 - missed case to clean 2012-08-02 20:43:14 +00:00
Stanislav Shwartsman
2e0f79d499 fixed compilation with AVX OFF but x86-64 on 2012-08-02 12:13:21 +00:00
Stanislav Shwartsman
b43ac7358e fixed typo-like bug in smm.cc 2012-08-01 14:56:51 +00:00
Stanislav Shwartsman
a1ebdc41ac Fixed SF bug [3548109] VMX State Not Restored After Entering SMM on 32-bit Systems 
Fixed .conf.nothing configure script

Fixed copyright for some files
 2012-07-27 08:13:39 +00:00
Stanislav Shwartsman
e0729e32b8 fixed bug 3548108 VMEXIT instruction length Not always getting updated 2012-07-26 16:03:26 +00:00
Stanislav Shwartsman
d9998269ef added branch_eip into near branch instructiontation callbacks 2012-07-24 15:32:55 +00:00
Stanislav Shwartsman
b225c158a9 fixed link error with no x86-64 2012-07-14 08:45:43 +00:00
Volker Ruppert
61292eb45b - missing SHELL fixes 2012-07-14 07:13:56 +00:00
Volker Ruppert
53438e92c6 - fixes based on Debian patches by Guillem Jover 
- set SHELL variable with configure script
  - add '--tag CXX' argument to libtool calls
 2012-07-14 07:01:43 +00:00
Stanislav Shwartsman
5d66e8450e implemented ADCX/ADOX instructions from rev013 of arch extensions published by Intel 2012-07-12 14:51:54 +00:00
Stanislav Shwartsman
bafde35c9c Intel Architecture 
Instruction Set Extensions
Programming Reference
rev013

was published including RDSEED and ADCX/ADOX instructions

add CPUID bits and VMX controls mentioned in the document
 2012-07-11 18:58:00 +00:00
Stanislav Shwartsman
ec06475dbf improve x86 hw breakpoint handling 2012-07-11 15:07:54 +00:00
Stanislav Shwartsman
58dde88887 VME is for CPU_LEVEL>=5 only 2012-07-08 18:16:25 +00:00
Stanislav Shwartsman
1964ef679a fixed compilation with x86-64 disabled 2012-07-01 14:46:27 +00:00
Stanislav Shwartsman
874ba7388d coding style change 2012-06-30 19:33:49 +00:00
Stanislav Shwartsman
39f3051ce5 fixed opcode primitive used for AVX instructions reading only half register (8byte) from the memory 2012-06-30 19:31:32 +00:00
Stanislav Shwartsman
16ecab5644 trying to guess real HW behavior for (V)DPPS/(V)DPPD instructions 2012-06-30 18:19:22 +00:00
Stanislav Shwartsman
f12396566c added CR8 to control registers print in debugger 2012-06-28 18:27:26 +00:00
Stanislav Shwartsman
3415f7bb0f add XD bit to page attributes print 2012-06-28 10:59:30 +00:00
Stanislav Shwartsman
79628a2f4f fixed VME corner case 2012-06-27 15:09:10 +00:00
Stanislav Shwartsman
4c38969ef0 fixed uninitialized variables 2012-06-24 17:52:45 +00:00
Stanislav Shwartsman
48ae41a2fd fixed MASKMOVDQU SSE instruction to match hardware 2012-06-23 16:25:52 +00:00
Stanislav Shwartsman
515d8b5c25 add new instrumentation callbacks for physical memory access from CPU 2012-06-18 11:41:26 +00:00
Stanislav Shwartsman
720a9b2fb7 fixed 64-bit segment print from internal debugger 2012-06-14 18:56:47 +00:00
Stanislav Shwartsman
171d400bd8 GATHER: update gather mask handling to match latest Intel SDM definition 
Fixes in x86 HW breakpoint handling
 2012-06-06 14:01:45 +00:00
Stanislav Shwartsman
6782efde05 correctly initialize lazy flags on reset 2012-06-05 20:53:22 +00:00
Stanislav Shwartsman
832d3a09a3 compile fix for SMP disable 2012-06-05 11:42:07 +00:00
Stanislav Shwartsman
a604818ecf fixed another valgrind issue 2012-06-05 11:40:59 +00:00
Stanislav Shwartsman
efcca3e9d4 fixup VCVTPH2PS instruction implementation to match published Intel SDM 2012-06-05 11:36:50 +00:00
Stanislav Shwartsman
37e193d49c clean one more valgrind issue 2012-06-04 19:21:23 +00:00
Stanislav Shwartsman
5192d09655 fixed some more valgrind issues 2012-06-04 18:46:07 +00:00
Stanislav Shwartsman
7bae496840 fixed valgrind issues in apic initialization and generic cpuid reported in SF bug report 2012-06-04 14:27:34 +00:00
Stanislav Shwartsman
bd6330d480 small optimization for debugger 2012-06-03 18:46:20 +00:00
Stanislav Shwartsman
2ee3386c37 cpu bugfixes 2012-05-31 14:25:49 +00:00
Stanislav Shwartsman
f528290652 fixed bug EPT Access Dirty support 2012-05-27 19:17:13 +00:00
Stanislav Shwartsman
8e7f582bc3 correct init.cc fix - copy/paste issue 2012-05-20 19:02:29 +00:00
Stanislav Shwartsman
3f32517201 small fix for save/restore 2012-05-20 18:58:57 +00:00
Stanislav Shwartsman
f9540f1c24 - Improved CPU status restore after restoring from Bochs saved image 
- Changed many BX_ERROR messages about VMX VMEXIT takesn to BX_DEBUG
 2012-05-19 20:36:40 +00:00
Stanislav Shwartsman
2644ef5f63 another had_vex/had_xop fix 2012-05-19 19:46:10 +00:00
Stanislav Shwartsman
59eb1318d5 small fix 2012-05-19 19:38:57 +00:00
Stanislav Shwartsman
ffc5e4bf2d optimize x2apic reg write 2012-05-12 19:07:18 +00:00
Stanislav Shwartsman
08d4655886 X2APIC: incorrect write to self IPI X2APIC register (with reserved bits set) should not trigger the self IPI 2012-05-12 12:49:05 +00:00
Stanislav Shwartsman
03162d86f5 LAPIC: fixed timer interrupts after reloading of LAPIC Timer Divide Configuration register 2012-05-12 11:52:29 +00:00
Stanislav Shwartsman
9ea0987396 fixed send_ipi case in x2apic 2012-05-12 08:07:30 +00:00
Stanislav Shwartsman
6180a0a733 remove unused leafs from generic_cpuid 2012-05-11 06:51:04 +00:00
Stanislav Shwartsman
b5c5082ff2 Completely remove b1() field from bxInstruction structure and resuse it for AVX instructions flags. 
the iaOpcode field has no masking anymore.

fixed bug during the code reorganization:
                        
+ XOP: Fixed instructions with operands order depending on VEX.W (fixed VEX.W read from instruction object)
 2012-05-11 06:35:16 +00:00
Volker Ruppert
53e1a5d204 - fixed typo (file names are case sensitive on Linux and others) 2012-05-08 18:33:26 +00:00
Stanislav Shwartsman
f01e5f3e11 removed b1() from shift methods in CPU - lead to removal of b1() field from bxInstruction_c 2012-05-08 16:42:15 +00:00
Stanislav Shwartsman
708fc666c8 Added Corei7 ivyBridge configuration to CPUDB 2012-05-07 12:31:22 +00:00
Stanislav Shwartsman
9d802e2762 very small cleanup 2012-05-05 18:40:37 +00:00
Stanislav Shwartsman
2188322ab3 fixed CR8 SVM intercepts 2012-05-03 16:12:58 +00:00
Stanislav Shwartsman
39c14ef0d1 Implemented EPT A/D extensions support. 
Bochs is fully aligned with the latest published revision of
Intel Architecture Manual (revision 043) now.
 2012-05-02 18:11:39 +00:00
Stanislav Shwartsman
e12494bf7b fixed segfault when setting ESP/EIP in GUI debugger 2012-04-16 19:18:23 +00:00
Stanislav Shwartsman
c7c431f88e bx_instr_mem_data_access became completely obsolete with new stack optimization merged into SVN. 
It already had limited usability before. With stack direct access optimization the callback won't be called for stack accesses as well.
See note by Brian Slechta:

=== Cut Hete ===
While using Bochs as a reference model for simulations, the simulator needs
information about what loads/stores are taking place with each instruction.
Presumably,  that  is  what  the BX_INSTR_MEM_DATA() instrumentation macros
cover (which is the place where our simulator hooks up).

The RETnear_xxx() functions call access_linear() directly, rather than call
read_virtual_xxx()  functions. This is a problem for code making use of the
BX_INSTR_MEM_DATA()   hook  because  it  does  not  get  called  for  these
instructions.  Should  this  be  changed along with some other instructions
that exhibit this?
=== Cut Hete ===

For Bryan's usage bx_instr_lin_access and bx_instr_phy_read/bx_instr_phy_write callbacks should be used.
 2012-04-11 19:01:25 +00:00
Stanislav Shwartsman
59e13d5299 fixed compilation error with 386/486 and internal dbger enabled 2012-04-11 18:11:14 +00:00
Stanislav Shwartsman
a68ad9a7f6 small code optimization 2012-04-06 09:41:58 +00:00
Stanislav Shwartsman
a6f0ca70ff more robust SVM fix 2012-04-04 19:55:36 +00:00
Stanislav Shwartsman
72a00ce9dd improved debug prints in MOV to/from CR 
SVM bugfix
remove redundant TLB flush call from SVM and VMX code
 2012-04-04 19:31:02 +00:00
Stanislav Shwartsman
279c61dc67 updated + fixed instrumentation example for instr histogram, code cleanup in the cpu 2012-03-28 21:11:19 +00:00
Stanislav Shwartsman
90fc12d9e4 switching between compatibility and long64 mode also affect SS.BASE which is always zero in long64 mode 2012-03-27 15:21:40 +00:00
Stanislav Shwartsman
e7a4a1bec8 surprisingly, opensuse 12.1 requre alignment check support in hardware so I can't disable it by default for all configurations. 
but in case you want a few %% of extra emulation performance - it is still possible to disable it with configure option.
most guests I saw do not use it !
 2012-03-26 19:33:38 +00:00
Stanislav Shwartsman
8b78f6ca2c fixed prev commit 2012-03-26 19:24:20 +00:00
Stanislav Shwartsman
97a6d0ad46 missed ; 2012-03-26 19:08:28 +00:00
Stanislav Shwartsman
547678e8bd fixed compilation error in 386 config. also fixed bugs in tasking code found by new assertion added in stack.cc new code 2012-03-26 19:05:58 +00:00
Stanislav Shwartsman
bfca96f8ce added TLB contents to param tree for debugger purposes. Nopw the TLB could be browsed through param-tree in debugger and GUI debugger as well 2012-03-25 20:56:18 +00:00
Stanislav Shwartsman
d4688e8b95 - Do not compile support for alignment check (#AC exception) by default 
for CPU emulation performance reasons, the alignment check compilation
    still can be enabled using configure option --enable-alignment-check.

There is no software in the world which enable #AC exception checking, this
x86 feature is completely legacy but its emulation support costs up to 3-5%
emulation speed.

The checking for #AC exception enable still will be done, if

 CPL == 3, EFLAGS.AC = 1 and CR0.AM = 1

but the alignment check is not compiled in, the Bochs will PANIC with corresponding message.
You can press 'always continue' and ignore the PANIC, the simulation will continue as if alignment checking is not enabled.
 2012-03-25 19:07:17 +00:00
Stanislav Shwartsman
3ca29cbdf3 stack direct access optimization - 5% emu speedup to all 32-bit guests, for 64-bit guests speedup is less because they have less stack accesses 2012-03-25 11:54:32 +00:00
Stanislav Shwartsman
b5a33e82ac fixed a lot of code duplication in debugging/instrumentation of mem access 2012-03-20 18:26:04 +00:00
Stanislav Shwartsman
e1506e3e29 some cleanup in CPU code + patch SVM SS.DPL instead of failing VMRUN 2012-03-19 19:24:15 +00:00
Stanislav Shwartsman
a8565cdfc3 added missed line in MSR fix 2012-03-17 12:07:27 +00:00
Stanislav Shwartsman
bd4aa017fe Lazy flags improvement patch by Darek Mihocka - measured 5% speedup everywhere accross the board 
The problem with Parity is it is generally referenced very rarely so the current lazy flags code is not efficient to updated Parify flag only (because it updates low 8 bits of .result value the existing Zero Flag has to be shadowed in .auxbits.
So I flipped it around, to make Parity be shadowed in auxbits.  .result now is only needed to derive Zero Flag, and both Sign and Parify are derived from .result + .auxbits (as Zero Flag is now).  For the 90% of the conditional jumps that are JZ or JNZ, this is a speedup.
Parity is now derived from 8 bits in .result and 8 bits in .auxbits, and Sign is derived from one flag in .result and 1 bit in .auxbits by XOR-ing them all together.  It makes the code sequences for SAHF and POPF simpler too.
 2012-03-17 08:51:52 +00:00
Stanislav Shwartsman
5a33b1be84 mvoed MWAIT_IS_NOP option from CPUID to CPU - it has meaning even if CPUID tree is not used because CPU is configured with CPUDB pre-defined configuration 2012-03-15 19:46:57 +00:00
Stanislav Shwartsman
9d5d33632c VMX: Fixed reading of VMX MSR-HI (0xC0000000 <= index <= 0xC0001FFF) bitmaps / Fixed memory overflow 2012-03-14 19:42:06 +00:00
Stanislav Shwartsman
a9d03340d6 correctly handle EFER.LMA and EFER.LME with unrestricted guests 2012-03-14 19:17:27 +00:00
Stanislav Shwartsman
a668ff9908 small code optimization 2012-03-13 19:41:10 +00:00
Stanislav Shwartsman
25ffaeeea8 fixed VMX issue + small code reorg 2012-03-13 15:18:21 +00:00
Stanislav Shwartsman
9c27d279b9 removed incorrect BX_INFO msg 2012-03-07 20:07:57 +00:00
Stanislav Shwartsman
562c8c91d1 fixed FMA4 instructions sources 2012-03-06 15:18:35 +00:00
Stanislav Shwartsman
bde2f4d829 correctly handle #UD because of XOP.VVV 2012-03-05 19:48:55 +00:00
Stanislav Shwartsman
95e4191cd1 any vex instruction must use VEX.VVV or #UD 2012-03-04 17:56:22 +00:00
Stanislav Shwartsman
c52d97cb7f fixed comments in paging.cc 2012-02-28 22:39:33 +00:00
Stanislav Shwartsman
1f14c171ed rename some SSE handlers 2012-02-28 18:53:58 +00:00
Stanislav Shwartsman
d4541f1a88 removed dedicated handler for MOVNTI - can be replaced with existing handlers 2012-02-27 15:50:43 +00:00
Stanislav Shwartsman
959ab435cf fixed compilation err with SVM 2012-02-24 21:31:31 +00:00
Stanislav Shwartsman
86c7033a63 name cpu log functions in lower case 2012-02-23 19:31:02 +00:00
Stanislav Shwartsman
1599031869 changed BX_INFO back to BX_DEBUG 2012-02-19 20:16:10 +00:00
Stanislav Shwartsman
f48317affc SVM: Added EXITINFO2 write on VMEXIT (missed in prev commit) 
Added phenom_8650_toliman <AMD Phenom X3 8650 (Toliman)> comment into .bochsrc example with all other supported CPU configs.
Added missed SVM definitions into Toliman CPUDB module
 2012-02-19 20:15:23 +00:00
Stanislav Shwartsman
92376fb693 svm updates 2012-02-19 12:16:58 +00:00
Stanislav Shwartsman
c70a42c5d7 merged patch ftom SF bug 3459998 Bochs cannot be compiled outside the source tree 2012-02-19 12:16:14 +00:00
Stanislav Shwartsman
c2670b40d5 small cleanup in paging code 2012-02-15 19:49:35 +00:00
Stanislav Shwartsman
2f7e5ab3a3 fixed bugs in toliman configuration 2012-02-14 22:01:50 +00:00
Stanislav Shwartsman
5c02e7cebd do not need to load PAE PDPTRs if going to nested paging mode 2012-02-14 12:36:39 +00:00
Stanislav Shwartsman
bb7a648d91 Major commit ! 
------------

Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest !
A lot of code duplication was added for now - major cleanup will follow later.

! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled.

Some CPUID modules rework done to enable Toliman configuration.

Ckean up 'executable' attribute from all CPU source files.
 2012-02-13 23:29:01 +00:00
Stanislav Shwartsman
deaf58b130 read from CPUDB svm extensions 2012-02-13 21:55:27 +00:00
Stanislav Shwartsman
813fe4e6b9 reduce code duplication - continue preparing for nested paging implementation 2012-02-13 20:06:04 +00:00
Stanislav Shwartsman
4d0a5c1b07 - VMX: EPT misconfiguration should always take priority above EPT permissions violation (translate_guest_physical corner case bug) 
- VMX: EPT reserved bits set should cause EPT misconfiguration and not EPT violation
- VMX: EPT walk for guest CR3 address should be considered as 'page walk'
 2012-02-12 21:30:22 +00:00
Stanislav Shwartsman
0b5f798af1 re-commit changes from SVN rev11026 which were accidentially undo'ed by last Volker's commit 2012-02-12 19:13:57 +00:00
Volker Ruppert
de94b08a1a - class bx_list_c now contains a chained list of parameters. Removed the now 
obsolete maxsize parameter from all lists.
 2012-02-12 18:43:20 +00:00
Stanislav Shwartsman
855d2adece cleanups in paging code 2012-02-12 16:09:35 +00:00
Stanislav Shwartsman
fa182e96b5 for future nested paging: under NP PDPTR CACHE will contain NP PDPTR entries 2012-02-10 20:39:46 +00:00
Stanislav Shwartsman
b497077b70 intel disclosed more cpuid bits 2012-02-08 19:54:22 +00:00
Stanislav Shwartsman
9bebe91826 eliminate duplicated cpu methods by adding extra param to opcodes with no modrm 2012-02-03 10:24:59 +00:00
Stanislav Shwartsman
14ec87768e expand FCMOV function to 8 different functions - each one is much simpler to implement and understand 2012-02-01 12:07:53 +00:00
Stanislav Shwartsman
2e44613032 dos2unix for avx_pfp.cc 2012-01-30 15:29:22 +00:00
Stanislav Shwartsman
457c56c822 fixup for EPT paging 2012-01-22 18:39:15 +00:00
Stanislav Shwartsman
fc6712e3a3 undo part of prev paging commit 2012-01-19 20:01:32 +00:00
Stanislav Shwartsman
12afed23a1 small fix and cleanups in paging code 2012-01-19 06:38:22 +00:00
Stanislav Shwartsman
9461797886 added extra param to debugger phy access callback + cleanup in vmexit functions 2012-01-17 21:50:15 +00:00
Stanislav Shwartsman
f4b49633d4 paging code rework (cont) 2012-01-17 18:20:55 +00:00
Stanislav Shwartsman
0d64a6cb92 fixed paging bug in previous commit 2012-01-16 15:26:25 +00:00
Stanislav Shwartsman
7d641450ec remove param from check_entry_PAE function - it is always the same for all calls 2012-01-15 20:25:39 +00:00
Stanislav Shwartsman
c7cb99787e rework in paging code before nested paging implementation for SVM - step 2 
optimize TLB flush code
 2012-01-15 19:38:00 +00:00
Stanislav Shwartsman
4db23355cd rework in paging code before nested paging implementation for SVM - step 1 2012-01-15 17:54:13 +00:00
Stanislav Shwartsman
f5d55f5eb6 - Implemented Task Switch intercept in SVM, cleanup in task switch handling code 
- Changed (c) year in several cpu files
- Cleanup and indent fixes in VMX code
 2012-01-11 20:21:29 +00:00
Stanislav Shwartsman
cb366e00c5 fixed code duplication in exceptions 2012-01-11 06:27:35 +00:00
Stanislav Shwartsman
ba7887f31c fixed code duplication with v86 interrupt redirection 2012-01-10 08:13:34 +00:00
Stanislav Shwartsman
8d698c7087 fixed compilation err ith cpu-level=5 and cleanups 2012-01-09 20:52:15 +00:00
Stanislav Shwartsman
87b1c31495 fixed SVM VmEXIT on #PF error code 2012-01-09 20:24:23 +00:00
Stanislav Shwartsman
f64c38dfaf fix in SVM event injection 2012-01-09 20:15:15 +00:00
Stanislav Shwartsman
2900956327 Split back some frequently used arithmetic and logic opcodes (which were done as Load+Op before). 2012-01-09 13:09:59 +00:00
Stanislav Shwartsman
35bfe11c3d SVM: forgot to save RFLAGS in guest state 2012-01-08 19:46:38 +00:00
Stanislav Shwartsman
a531f8081c fixed compilation with cpu-level=5 2012-01-08 16:58:14 +00:00
Stanislav Shwartsman
76ee7b499b svm updates 2012-01-08 14:09:51 +00:00
Stanislav Shwartsman
9261b2fa14 removed param_names.h include where not needed anymore 2012-01-07 17:54:19 +00:00
Stanislav Shwartsman
7defa74261 cleaned up code duplication in CPUDB classes 2012-01-07 17:06:03 +00:00
Stanislav Shwartsman
a804adac46 fixed compilation err with SMP enabled 2012-01-07 16:45:25 +00:00
Stanislav Shwartsman
edfff5bf44 fixed VMX+EPT VirtualBox failures 2012-01-06 10:30:07 +00:00
Stanislav Shwartsman
e2ff4bc6d4 clear exitinfo1/2 fields in SVM on VMENTER 2012-01-05 22:23:05 +00:00
Stanislav Shwartsman
665d4568ee convert most popular svn/vmx msgs to bx_debug - can be used together with enabling log options per device from .bochsrc 2012-01-05 19:42:58 +00:00
Stanislav Shwartsman
fddccfb498 code cleanup + copy/paste removal 2012-01-04 21:36:39 +00:00
Stanislav Shwartsman
0e17f8f195 implemented AMD APIC extensions for SVM support 2012-01-04 16:06:37 +00:00
Stanislav Shwartsman
8c8fa8ec25 vmx cleanups 2012-01-03 20:27:40 +00:00
Stanislav Shwartsman
c857488ed9 Added Corei5 750 (Lynnfield) configuration to the CPUDB 2012-01-02 20:59:02 +00:00
Stanislav Shwartsman
3b98634045 show EFER in debug print outside long mode too 2012-01-02 20:06:03 +00:00
Stanislav Shwartsman
5847e772a6 set async_event when injecting virq to SVM guest 2012-01-01 21:22:56 +00:00
Stanislav Shwartsman
269d5e3443 more SVM fixes 2012-01-01 20:26:23 +00:00
Stanislav Shwartsman
810aa1b67c fixes for SVN. also turion64_tyler supports RDTSCP - include it in CPUID 2012-01-01 17:54:41 +00:00
Stanislav Shwartsman
30d90c1dc1 more SVM fixes 2011-12-31 20:10:11 +00:00
Stanislav Shwartsman
b97a108d93 SVM: allow entering vm8086 and also paged real mode 2011-12-31 16:33:36 +00:00
Stanislav Shwartsman
a0b5ff48ec more SVM fixes 2011-12-31 14:22:51 +00:00
Stanislav Shwartsman
3c0d712146 SVM fixes 2011-12-31 13:58:55 +00:00
Stanislav Shwartsman
fe6741d84d fixed SVM bug 2011-12-31 13:26:55 +00:00
Stanislav Shwartsman
fe6328d18c correctly enable SVM support in internal CPU features list 2011-12-31 12:58:20 +00:00
Stanislav Shwartsman
46d8a5894e removed bad RDMSR/WRMSR check which disabled access to AMD extended MSRs 2011-12-31 12:37:35 +00:00
Stanislav Shwartsman
560e3ca254 compilation fix for smp=0 2011-12-30 18:55:19 +00:00
Stanislav Shwartsman
cee8a3b9ef AMD's core has special 0x80000008.ecx value 2011-12-30 18:53:41 +00:00
Stanislav Shwartsman
088ab4832f turion64 tyler supports cmpxchg16b 2011-12-30 18:46:46 +00:00
Stanislav Shwartsman
2a0d989755 fixed compilation err with SVm w/o VMX 2011-12-30 12:24:22 +00:00
Stanislav Shwartsman
93523a657d remove patch that always kept IF set after HLT - not needed anymore 2011-12-30 08:50:01 +00:00
Stanislav Shwartsman
abda3a967c added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
Stanislav Shwartsman
5da69a6fb4 fixed typo - invalid CPUID leaf should go to max std leaf 2011-12-28 21:59:39 +00:00
Stanislav Shwartsman
2b854cb101 added basic (very basic) SVM CPUID into generic_cpuid module 2011-12-28 21:54:51 +00:00
Stanislav Shwartsman
0a14f08f16 completing SVM coding, missed - CPUID, extended APIC 2011-12-28 16:12:28 +00:00
Stanislav Shwartsman
864ea23b5b take events handling logic from cpu.cc to new file event.cc 2011-12-28 12:26:45 +00:00
Stanislav Shwartsman
2b8371f2b6 implemented SVM_GIF handling 2011-12-27 20:46:15 +00:00
Stanislav Shwartsman
7f5f917a34 more SVM implementation 2011-12-27 19:42:11 +00:00
Stanislav Shwartsman
c32eaa5d05 added more svm intercepts 2011-12-26 20:51:57 +00:00
Stanislav Shwartsman
6ae86a059b firt cleanup in SVM code. added intercept check for MSR and IO 2011-12-26 19:57:39 +00:00
Stanislav Shwartsman
8b4a2c2034 implemented some more intercepts. 
fixed compilation without SVM
 2011-12-26 16:33:13 +00:00
Stanislav Shwartsman
bfcbb81602 SVM: 
- IO intercept is not implemented yet
 - MSR intercept is not implemented yet

VMX:
 Fixed Bochs PANIC crash when doing I/O access crossing VMX I/O permission bitmaps.
 This can happen because access_physical_read and access_physical_write cannot access memory cross 4K boundary.
 2011-12-25 22:09:31 +00:00