Split back some frequently used arithmetic and logic opcodes (which were done as Load+Op before).
This commit is contained in:
parent
35bfe11c3d
commit
2900956327
@ -68,6 +68,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GwEwR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GwEwM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
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Bit32u op2_16 = read_virtual_word(i->seg(), eaddr);
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Bit32u sum_16 = op1_16 + op2_16;
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BX_WRITE_16BIT_REG(i->nnn(), sum_16);
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SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_AXIw(bxInstruction_c *i)
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{
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Bit32u op1_16 = AX;
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@ -109,6 +124,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GwEwR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GwEwM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
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Bit32u op2_16 = read_virtual_word(i->seg(), eaddr);
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Bit32u sum_16 = op1_16 + op2_16 + getB_CF();
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BX_WRITE_16BIT_REG(i->nnn(), sum_16);
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SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_AXIw(bxInstruction_c *i)
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{
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Bit32u op1_16 = AX;
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@ -150,6 +180,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GwEwR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GwEwM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
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Bit32u op2_16 = read_virtual_word(i->seg(), eaddr);
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Bit32u diff_16 = op1_16 - (op2_16 + getB_CF());
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BX_WRITE_16BIT_REG(i->nnn(), diff_16);
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SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_AXIw(bxInstruction_c *i)
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{
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Bit32u op1_16 = AX;
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@ -219,6 +264,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GwEwR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GwEwM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
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Bit32u op2_16 = read_virtual_word(i->seg(), eaddr);
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Bit32u diff_16 = op1_16 - op2_16;
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BX_WRITE_16BIT_REG(i->nnn(), diff_16);
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SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_AXIw(bxInstruction_c *i)
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{
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Bit32u op1_16 = AX;
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@ -256,6 +316,19 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GwEwR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GwEwM(bxInstruction_c *i)
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{
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
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Bit32u op2_16 = read_virtual_word(i->seg(), eaddr);
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Bit32u diff_16 = op1_16 - op2_16;
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SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_AXIw(bxInstruction_c *i)
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{
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Bit32u op1_16 = AX;
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@ -73,6 +73,23 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GdEdR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GdEdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, sum_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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op2_32 = read_virtual_dword(i->seg(), eaddr);
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sum_32 = op1_32 + op2_32;
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BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EAXId(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32 = i->Id(), sum_32;
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@ -120,6 +137,24 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GdEdR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GdEdM(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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Bit32u op1_32, op2_32, sum_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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op2_32 = read_virtual_dword(i->seg(), eaddr);
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sum_32 = op1_32 + op2_32 + temp_CF;
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BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
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SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EAXId(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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@ -169,6 +204,24 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GdEdR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GdEdM(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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Bit32u op1_32, op2_32, diff_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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op2_32 = read_virtual_dword(i->seg(), eaddr);
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diff_32 = op1_32 - (op2_32 + temp_CF);
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BX_WRITE_32BIT_REGZ(i->nnn(), diff_32);
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EAXId(bxInstruction_c *i)
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{
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bx_bool temp_CF = getB_CF();
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@ -247,6 +300,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GdEdR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GdEdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, diff_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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op2_32 = read_virtual_dword(i->seg(), eaddr);
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diff_32 = op1_32 - op2_32;
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BX_WRITE_32BIT_REGZ(i->nnn(), diff_32);
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EAXId(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, diff_32;
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@ -289,6 +358,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GdEdR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GdEdM(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, diff_32;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_32 = BX_READ_32BIT_REG(i->nnn());
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op2_32 = read_virtual_dword(i->seg(), eaddr);
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diff_32 = op1_32 - op2_32;
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SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EAXId(bxInstruction_c *i)
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{
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Bit32u op1_32, op2_32, diff_32;
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@ -57,6 +57,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GqEqR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GqEqM(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, sum_64;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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op2_64 = read_virtual_qword_64(i->seg(), eaddr);
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sum_64 = op1_64 + op2_64;
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BX_WRITE_64BIT_REG(i->nnn(), sum_64);
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SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_RAXId(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, sum_64;
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@ -98,7 +114,23 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GqEqR(bxInstruction_c *i)
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op2_64 = BX_READ_64BIT_REG(i->rm());
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sum_64 = op1_64 + op2_64 + getB_CF();
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/* now write sum back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), sum_64);
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SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GqEqM(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, sum_64;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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op2_64 = read_virtual_qword_64(i->seg(), eaddr);
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sum_64 = op1_64 + op2_64 + getB_CF();
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BX_WRITE_64BIT_REG(i->nnn(), sum_64);
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SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
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@ -147,7 +179,23 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GqEqR(bxInstruction_c *i)
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op2_64 = BX_READ_64BIT_REG(i->rm());
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diff_64 = op1_64 - (op2_64 + getB_CF());
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/* now write diff back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), diff_64);
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SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GqEqM(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, diff_64;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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op2_64 = read_virtual_qword_64(i->seg(), eaddr);
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diff_64 = op1_64 - (op2_64 + getB_CF());
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BX_WRITE_64BIT_REG(i->nnn(), diff_64);
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SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
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@ -163,7 +211,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_RAXId(bxInstruction_c *i)
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op2_64 = (Bit32s) i->Id();
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diff_64 = op1_64 - (op2_64 + getB_CF());
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/* now write diff back to destination */
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RAX = diff_64;
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SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
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@ -227,7 +274,23 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GqEqR(bxInstruction_c *i)
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op2_64 = BX_READ_64BIT_REG(i->rm());
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diff_64 = op1_64 - op2_64;
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/* now write diff back to destination */
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BX_WRITE_64BIT_REG(i->nnn(), diff_64);
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SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GqEqM(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, diff_64;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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op2_64 = read_virtual_qword_64(i->seg(), eaddr);
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diff_64 = op1_64 - op2_64;
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BX_WRITE_64BIT_REG(i->nnn(), diff_64);
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SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
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@ -243,7 +306,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_RAXId(bxInstruction_c *i)
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op2_64 = (Bit32s) i->Id();
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diff_64 = op1_64 - op2_64;
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/* now write diff back to destination */
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RAX = diff_64;
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SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
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@ -279,6 +341,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GqEqR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GqEqM(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, diff_64;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_64 = BX_READ_64BIT_REG(i->nnn());
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op2_64 = read_virtual_qword_64(i->seg(), eaddr);
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diff_64 = op1_64 - op2_64;
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SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_RAXId(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, diff_64;
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@ -52,6 +52,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GbEbR(bxInstruction_c *i)
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GbEbM(bxInstruction_c *i)
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{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
Bit32u op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
Bit32u op2 = read_virtual_byte(i->seg(), eaddr);
|
||||
Bit32u sum = op1 + op2;
|
||||
|
||||
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), sum);
|
||||
|
||||
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_ALIb(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1 = AL;
|
||||
@ -92,6 +107,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GbEbR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GbEbM(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
Bit32u op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
Bit32u op2 = read_virtual_byte(i->seg(), eaddr);
|
||||
Bit32u sum = op1 + op2 + getB_CF();
|
||||
|
||||
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), sum);
|
||||
|
||||
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_ALIb(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1 = AL;
|
||||
@ -132,6 +162,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GbEbR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GbEbM(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
Bit32u op1_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
Bit32u op2_8 = read_virtual_byte(i->seg(), eaddr);
|
||||
Bit32u diff_8 = op1_8 - (op2_8 + getB_CF());
|
||||
|
||||
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), diff_8);
|
||||
|
||||
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_ALIb(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_8 = AL;
|
||||
@ -199,6 +244,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GbEbR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GbEbM(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
Bit32u op1_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
Bit32u op2_8 = read_virtual_byte(i->seg(), eaddr);
|
||||
Bit32u diff_8 = op1_8 - op2_8;
|
||||
|
||||
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), diff_8);
|
||||
|
||||
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_ALIb(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_8 = AL;
|
||||
@ -236,6 +296,19 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GbEbR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GbEbM(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
Bit32u op1_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
Bit32u op2_8 = read_virtual_byte(i->seg(), eaddr);
|
||||
Bit32u diff_8 = op1_8 - op2_8;
|
||||
|
||||
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_ALIb(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_8 = AL;
|
||||
|
@ -1429,6 +1429,10 @@ public: // for now...
|
||||
BX_SMF BX_INSF_TYPE TEST_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE TEST_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE TEST_EbGbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE TEST_EwGwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE TEST_EdGdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE XCHG_EbGbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE XCHG_EwGwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE XCHG_EdGdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
@ -1758,6 +1762,15 @@ public: // for now...
|
||||
BX_SMF BX_INSF_TYPE XOR_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE CMP_GbEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE ADD_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE OR_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE ADC_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE SBB_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE AND_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE SUB_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE XOR_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE CMP_GbEbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE ADD_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE OR_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE ADC_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
@ -1848,6 +1861,15 @@ public: // for now...
|
||||
BX_SMF BX_INSF_TYPE XOR_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE CMP_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE ADD_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE OR_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE ADC_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE SBB_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE AND_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE SUB_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE XOR_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE CMP_GwEwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE ADD_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE OR_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE ADC_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
@ -1857,6 +1879,15 @@ public: // for now...
|
||||
BX_SMF BX_INSF_TYPE CMP_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE XOR_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE ADD_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE OR_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE ADC_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE SBB_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE AND_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE SUB_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE CMP_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE XOR_GdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE NOT_EbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE NOT_EwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE NOT_EdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
@ -1925,6 +1956,10 @@ public: // for now...
|
||||
BX_SMF BX_INSF_TYPE TEST_EwIwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE TEST_EdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE TEST_EbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE TEST_EwIwM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE TEST_EdIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE IMUL_GdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE IMUL_GdEdIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
@ -3183,6 +3218,15 @@ public: // for now...
|
||||
BX_SMF BX_INSF_TYPE XOR_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE CMP_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE ADD_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE OR_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE ADC_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE SBB_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE AND_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE SUB_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE XOR_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE CMP_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE ADD_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE OR_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE ADC_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
@ -3220,6 +3264,7 @@ public: // for now...
|
||||
BX_SMF BX_INSF_TYPE CMP_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE TEST_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE TEST_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE TEST_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE XCHG_EqGqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
@ -3387,6 +3432,7 @@ public: // for now...
|
||||
BX_SMF BX_INSF_TYPE NEG_EqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE TEST_EqIdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE TEST_EqIdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE MUL_RAXEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE IMUL_RAXEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
@ -93,21 +93,21 @@ bx_define_opcode(BX_IA_AND_EdId, &BX_CPU_C::AND_EdIdM, &BX_CPU_C::AND_EdIdR, 0,
|
||||
bx_define_opcode(BX_IA_SUB_EdId, &BX_CPU_C::SUB_EdIdM, &BX_CPU_C::SUB_EdIdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_EdId, &BX_CPU_C::XOR_EdIdM, &BX_CPU_C::XOR_EdIdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_EdId, &BX_CPU_C::CMP_EdIdM, &BX_CPU_C::CMP_EdIdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GbEb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::ADC_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::ADC_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::ADC_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GbEb, &BX_CPU_C::ADC_GbEbM, &BX_CPU_C::ADC_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GwEw, &BX_CPU_C::ADC_GwEwM, &BX_CPU_C::ADC_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GdEd, &BX_CPU_C::ADC_GdEdM, &BX_CPU_C::ADC_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADD_ALIb, NULL, &BX_CPU_C::ADD_ALIb, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADD_AXIw, NULL, &BX_CPU_C::ADD_AXIw, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADD_EAXId, NULL, &BX_CPU_C::ADD_EAXId, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADD_GbEb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::ADD_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADD_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::ADD_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADD_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::ADD_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADD_GbEb, &BX_CPU_C::ADD_GbEbM, &BX_CPU_C::ADD_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADD_GwEw, &BX_CPU_C::ADD_GwEwM, &BX_CPU_C::ADD_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADD_GdEd, &BX_CPU_C::ADD_GdEdM, &BX_CPU_C::ADD_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_AND_ALIb, NULL, &BX_CPU_C::AND_ALIb, 0, 0)
|
||||
bx_define_opcode(BX_IA_AND_AXIw, NULL, &BX_CPU_C::AND_AXIw, 0, 0)
|
||||
bx_define_opcode(BX_IA_AND_EAXId, NULL, &BX_CPU_C::AND_EAXId, 0, 0)
|
||||
bx_define_opcode(BX_IA_AND_GbEb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::AND_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_AND_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::AND_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_AND_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::AND_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_AND_GbEb, &BX_CPU_C::AND_GbEbM, &BX_CPU_C::AND_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_AND_GwEw, &BX_CPU_C::AND_GwEwM, &BX_CPU_C::AND_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_AND_GdEd, &BX_CPU_C::AND_GdEdM, &BX_CPU_C::AND_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ARPL_EwGw, &BX_CPU_C::ARPL_EwGw, &BX_CPU_C::ARPL_EwGw, 0, 0)
|
||||
bx_define_opcode(BX_IA_BOUND_GdMa, &BX_CPU_C::BOUND_GdMa, &BX_CPU_C::BxError, 0, 0)
|
||||
bx_define_opcode(BX_IA_BOUND_GwMa, &BX_CPU_C::BOUND_GwMa, &BX_CPU_C::BxError, 0, 0)
|
||||
@ -150,9 +150,9 @@ bx_define_opcode(BX_IA_CMC, NULL, &BX_CPU_C::CMC, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_ALIb, NULL, &BX_CPU_C::CMP_ALIb, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_AXIw, NULL, &BX_CPU_C::CMP_AXIw, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_EAXId, NULL, &BX_CPU_C::CMP_EAXId, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GbEb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::CMP_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::CMP_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::CMP_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GbEb, &BX_CPU_C::CMP_GbEbM, &BX_CPU_C::CMP_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GwEw, &BX_CPU_C::CMP_GwEwM, &BX_CPU_C::CMP_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GdEd, &BX_CPU_C::CMP_GdEdM, &BX_CPU_C::CMP_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_CWD, NULL, &BX_CPU_C::CWD, 0, 0)
|
||||
bx_define_opcode(BX_IA_CWDE, NULL, &BX_CPU_C::CWDE, 0, 0)
|
||||
bx_define_opcode(BX_IA_DEC_Eb, &BX_CPU_C::DEC_EbM, &BX_CPU_C::DEC_EbR, 0, 0)
|
||||
@ -295,9 +295,9 @@ bx_define_opcode(BX_IA_PAUSE, NULL, &BX_CPU_C::PAUSE, 0, 0)
|
||||
bx_define_opcode(BX_IA_OR_ALIb, NULL, &BX_CPU_C::OR_ALIb, 0, 0)
|
||||
bx_define_opcode(BX_IA_OR_AXIw, NULL, &BX_CPU_C::OR_AXIw, 0, 0)
|
||||
bx_define_opcode(BX_IA_OR_EAXId, NULL, &BX_CPU_C::OR_EAXId, 0, 0)
|
||||
bx_define_opcode(BX_IA_OR_GbEb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::OR_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_OR_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::OR_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_OR_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::OR_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_OR_GbEb, &BX_CPU_C::OR_GbEbM, &BX_CPU_C::OR_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_OR_GwEw, &BX_CPU_C::OR_GwEwM, &BX_CPU_C::OR_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_OR_GdEd, &BX_CPU_C::OR_GdEdM, &BX_CPU_C::OR_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_OUT_DXAL, NULL, &BX_CPU_C::OUT_DXAL, 0, 0)
|
||||
bx_define_opcode(BX_IA_OUT_DXAX, NULL, &BX_CPU_C::OUT_DXAX, 0, 0)
|
||||
bx_define_opcode(BX_IA_OUT_DXEAX, NULL, &BX_CPU_C::OUT_DXEAX, 0, 0)
|
||||
@ -400,9 +400,9 @@ bx_define_opcode(BX_IA_SALC, NULL, &BX_CPU_C::SALC, 0, 0)
|
||||
bx_define_opcode(BX_IA_SBB_ALIb, NULL, &BX_CPU_C::SBB_ALIb, 0, 0)
|
||||
bx_define_opcode(BX_IA_SBB_AXIw, NULL, &BX_CPU_C::SBB_AXIw, 0, 0)
|
||||
bx_define_opcode(BX_IA_SBB_EAXId, NULL, &BX_CPU_C::SBB_EAXId, 0, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GbEb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::SBB_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::SBB_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::SBB_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GbEb, &BX_CPU_C::SBB_GbEbM, &BX_CPU_C::SBB_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GwEw, &BX_CPU_C::SBB_GwEwM, &BX_CPU_C::SBB_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GdEd, &BX_CPU_C::SBB_GdEdM, &BX_CPU_C::SBB_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SETB_Eb, &BX_CPU_C::SETB_EbM, &BX_CPU_C::SETB_EbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SETBE_Eb, &BX_CPU_C::SETBE_EbM, &BX_CPU_C::SETBE_EbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SETL_Eb, &BX_CPU_C::SETL_EbM, &BX_CPU_C::SETL_EbR, 0, 0)
|
||||
@ -434,36 +434,36 @@ bx_define_opcode(BX_IA_STR_Ew, &BX_CPU_C::STR_Ew, &BX_CPU_C::STR_Ew, 0, 0)
|
||||
bx_define_opcode(BX_IA_SUB_ALIb, NULL, &BX_CPU_C::SUB_ALIb, 0, 0)
|
||||
bx_define_opcode(BX_IA_SUB_AXIw, NULL, &BX_CPU_C::SUB_AXIw, 0, 0)
|
||||
bx_define_opcode(BX_IA_SUB_EAXId, NULL, &BX_CPU_C::SUB_EAXId, 0, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GbEb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::SUB_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::SUB_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::SUB_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GbEb, &BX_CPU_C::SUB_GbEbM, &BX_CPU_C::SUB_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GwEw, &BX_CPU_C::SUB_GwEwM, &BX_CPU_C::SUB_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GdEd, &BX_CPU_C::SUB_GdEdM, &BX_CPU_C::SUB_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_ALIb, NULL, &BX_CPU_C::TEST_ALIb, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_AXIw, NULL, &BX_CPU_C::TEST_AXIw, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EAXId, NULL, &BX_CPU_C::TEST_EAXId, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EbGb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::TEST_EbGbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EbIb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::TEST_EbIbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EbGb, &BX_CPU_C::TEST_EbGbM, &BX_CPU_C::TEST_EbGbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EbIb, &BX_CPU_C::TEST_EbIbM, &BX_CPU_C::TEST_EbIbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_NOT_Eb, &BX_CPU_C::NOT_EbM, &BX_CPU_C::NOT_EbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_NEG_Eb, &BX_CPU_C::NEG_EbM, &BX_CPU_C::NEG_EbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_MUL_ALEb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::MUL_ALEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_IMUL_ALEb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::IMUL_ALEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_DIV_ALEb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::DIV_ALEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_IDIV_ALEb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::IDIV_ALEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EwIw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::TEST_EwIwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EwIw, &BX_CPU_C::TEST_EwIwM, &BX_CPU_C::TEST_EwIwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_NOT_Ew, &BX_CPU_C::NOT_EwM, &BX_CPU_C::NOT_EwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_NEG_Ew, &BX_CPU_C::NEG_EwM, &BX_CPU_C::NEG_EwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_MUL_AXEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::MUL_AXEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_IMUL_AXEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::IMUL_AXEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_DIV_AXEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::DIV_AXEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_IDIV_AXEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::IDIV_AXEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EdId, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::TEST_EdIdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EdId, &BX_CPU_C::TEST_EdIdM, &BX_CPU_C::TEST_EdIdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_NOT_Ed, &BX_CPU_C::NOT_EdM, &BX_CPU_C::NOT_EdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_NEG_Ed, &BX_CPU_C::NEG_EdM, &BX_CPU_C::NEG_EdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_MUL_EAXEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::MUL_EAXEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_IMUL_EAXEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::IMUL_EAXEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_DIV_EAXEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::DIV_EAXEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_IDIV_EAXEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::IDIV_EAXEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EdGd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::TEST_EdGdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EwGw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::TEST_EwGwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EdGd, &BX_CPU_C::TEST_EdGdM, &BX_CPU_C::TEST_EdGdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EwGw, &BX_CPU_C::TEST_EwGwM, &BX_CPU_C::TEST_EwGwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_VERR_Ew, &BX_CPU_C::VERR_Ew, &BX_CPU_C::VERR_Ew, 0, 0)
|
||||
bx_define_opcode(BX_IA_VERW_Ew, &BX_CPU_C::VERW_Ew, &BX_CPU_C::VERW_Ew, 0, 0)
|
||||
bx_define_opcode(BX_IA_XCHG_EbGb, &BX_CPU_C::XCHG_EbGbM, &BX_CPU_C::XCHG_EbGbR, 0, 0)
|
||||
@ -475,9 +475,9 @@ bx_define_opcode(BX_IA_XLAT, NULL, &BX_CPU_C::XLAT, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_ALIb, NULL, &BX_CPU_C::XOR_ALIb, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_AXIw, NULL, &BX_CPU_C::XOR_AXIw, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_EAXId, NULL, &BX_CPU_C::XOR_EAXId, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GbEb, &BX_CPU_C::LOAD_Eb, &BX_CPU_C::XOR_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::XOR_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::XOR_GdEdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GbEb, &BX_CPU_C::XOR_GbEbM, &BX_CPU_C::XOR_GbEbR, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GwEw, &BX_CPU_C::XOR_GwEwM, &BX_CPU_C::XOR_GwEwR, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GdEd, &BX_CPU_C::XOR_GdEdM, &BX_CPU_C::XOR_GdEdR, 0, 0)
|
||||
|
||||
bx_define_opcode(BX_IA_SYSENTER, NULL, &BX_CPU_C::SYSENTER, BX_ISA_SYSENTER_SYSEXIT, 0)
|
||||
bx_define_opcode(BX_IA_SYSEXIT, NULL, &BX_CPU_C::SYSEXIT, BX_ISA_SYSENTER_SYSEXIT, 0)
|
||||
@ -1154,14 +1154,14 @@ bx_define_opcode(BX_IA_LM_SAHF, NULL, &BX_CPU_C::SAHF, BX_ISA_LM_LAHF_SAHF, 0)
|
||||
bx_define_opcode(BX_IA_SYSCALL, NULL, &BX_CPU_C::SYSCALL, 0, 0)
|
||||
bx_define_opcode(BX_IA_SYSRET, NULL, &BX_CPU_C::SYSRET, 0, 0)
|
||||
|
||||
bx_define_opcode(BX_IA_ADD_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::ADD_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_OR_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::OR_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::ADC_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::SBB_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_AND_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::AND_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::SUB_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::XOR_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::CMP_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADD_GqEq, &BX_CPU_C::ADD_GqEqM, &BX_CPU_C::ADD_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_OR_GqEq, &BX_CPU_C::OR_GqEqM, &BX_CPU_C::OR_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADC_GqEq, &BX_CPU_C::ADC_GqEqM, &BX_CPU_C::ADC_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SBB_GqEq, &BX_CPU_C::SBB_GqEqM, &BX_CPU_C::SBB_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_AND_GqEq, &BX_CPU_C::AND_GqEqM, &BX_CPU_C::AND_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SUB_GqEq, &BX_CPU_C::SUB_GqEqM, &BX_CPU_C::SUB_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_GqEq, &BX_CPU_C::XOR_GqEqM, &BX_CPU_C::XOR_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_GqEq, &BX_CPU_C::CMP_GqEqM, &BX_CPU_C::CMP_GqEqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_ADD_EqGq, &BX_CPU_C::ADD_EqGqM, &BX_CPU_C::ADD_GqEqR, 0, 0) /* dstRM */
|
||||
bx_define_opcode(BX_IA_OR_EqGq, &BX_CPU_C::OR_EqGqM, &BX_CPU_C::OR_GqEqR, 0, 0) /* dstRM */
|
||||
bx_define_opcode(BX_IA_ADC_EqGq, &BX_CPU_C::ADC_EqGqM, &BX_CPU_C::ADC_GqEqR, 0, 0) /* dstRM */
|
||||
@ -1186,7 +1186,7 @@ bx_define_opcode(BX_IA_AND_EqId, &BX_CPU_C::AND_EqIdM, &BX_CPU_C::AND_EqIdR, 0,
|
||||
bx_define_opcode(BX_IA_SUB_EqId, &BX_CPU_C::SUB_EqIdM, &BX_CPU_C::SUB_EqIdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_XOR_EqId, &BX_CPU_C::XOR_EqIdM, &BX_CPU_C::XOR_EqIdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_CMP_EqId, &BX_CPU_C::CMP_EqIdM, &BX_CPU_C::CMP_EqIdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EqGq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::TEST_EqGqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EqGq, &BX_CPU_C::TEST_EqGqM, &BX_CPU_C::TEST_EqGqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_RAXId, NULL, &BX_CPU_C::TEST_RAXId, 0, 0)
|
||||
bx_define_opcode(BX_IA_XCHG_EqGq, &BX_CPU_C::XCHG_EqGqM, &BX_CPU_C::XCHG_EqGqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_LEA_GqM, &BX_CPU_C::LEA_GqM, &BX_CPU_C::BxError, 0, 0)
|
||||
@ -1256,7 +1256,7 @@ bx_define_opcode(BX_IA_RCR_Eq, &BX_CPU_C::RCR_EqM, &BX_CPU_C::RCR_EqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SHL_Eq, &BX_CPU_C::SHL_EqM, &BX_CPU_C::SHL_EqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SHR_Eq, &BX_CPU_C::SHR_EqM, &BX_CPU_C::SHR_EqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_SAR_Eq, &BX_CPU_C::SAR_EqM, &BX_CPU_C::SAR_EqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EqId, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::TEST_EqIdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_TEST_EqId, &BX_CPU_C::TEST_EqIdM, &BX_CPU_C::TEST_EqIdR, 0, 0)
|
||||
bx_define_opcode(BX_IA_NOT_Eq, &BX_CPU_C::NOT_EqM, &BX_CPU_C::NOT_EqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_NEG_Eq, &BX_CPU_C::NEG_EqM, &BX_CPU_C::NEG_EqR, 0, 0)
|
||||
bx_define_opcode(BX_IA_MUL_RAXEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::MUL_RAXEqR, 0, 0)
|
||||
|
@ -54,6 +54,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GwEwR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GwEwM(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, op2_16;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_16 = BX_READ_16BIT_REG(i->nnn());
|
||||
op2_16 = read_virtual_word(i->seg(), eaddr);
|
||||
op1_16 ^= op2_16;
|
||||
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_AXIw(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op_16 = AX ^ i->Iw();
|
||||
@ -166,6 +182,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GwEwR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GwEwM(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, op2_16;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_16 = BX_READ_16BIT_REG(i->nnn());
|
||||
op2_16 = read_virtual_word(i->seg(), eaddr);
|
||||
op1_16 |= op2_16;
|
||||
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_AXIw(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op_16 = AX | i->Iw();
|
||||
@ -206,6 +238,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GwEwR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GwEwM(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, op2_16;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_16 = BX_READ_16BIT_REG(i->nnn());
|
||||
op2_16 = read_virtual_word(i->seg(), eaddr);
|
||||
op1_16 &= op2_16;
|
||||
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_AXIw(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op_16 = AX & i->Iw();
|
||||
@ -254,6 +302,20 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwGwR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwGwM(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16, op2_16;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_16 = read_virtual_word(i->seg(), eaddr);
|
||||
op2_16 = BX_READ_16BIT_REG(i->nnn());
|
||||
op1_16 &= op2_16;
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_AXIw(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op_16 = AX & i->Iw();
|
||||
@ -271,3 +333,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwIwR(bxInstruction_c *i)
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwIwM(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
Bit16u op1_16 = read_virtual_word(i->seg(), eaddr);
|
||||
op1_16 &= i->Iw();
|
||||
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
@ -54,6 +54,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GdEdR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GdEdM(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, op2_32;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_32 = BX_READ_32BIT_REG(i->nnn());
|
||||
op2_32 = read_virtual_dword(i->seg(), eaddr);
|
||||
op1_32 ^= op2_32;
|
||||
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EAXId(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op_32 = EAX ^ i->Id();
|
||||
@ -166,6 +182,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GdEdR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GdEdM(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, op2_32;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_32 = BX_READ_32BIT_REG(i->nnn());
|
||||
op2_32 = read_virtual_dword(i->seg(), eaddr);
|
||||
op1_32 |= op2_32;
|
||||
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EAXId(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op_32 = EAX | i->Id();
|
||||
@ -206,6 +238,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GdEdR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GdEdM(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, op2_32;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_32 = BX_READ_32BIT_REG(i->nnn());
|
||||
op2_32 = read_virtual_dword(i->seg(), eaddr);
|
||||
op1_32 &= op2_32;
|
||||
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EAXId(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op_32 = EAX & i->Id();
|
||||
@ -255,6 +303,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdGdR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdGdM(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32, op2_32;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_32 = read_virtual_dword(i->seg(), eaddr);
|
||||
op2_32 = BX_READ_32BIT_REG(i->nnn());
|
||||
op1_32 &= op2_32;
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EAXId(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op_32 = EAX & i->Id();
|
||||
@ -272,3 +335,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdIdR(bxInstruction_c *i)
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdIdM(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
Bit32u op1_32 = read_virtual_dword(i->seg(), eaddr);
|
||||
op1_32 &= i->Id();
|
||||
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
@ -50,7 +50,23 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GqEqR(bxInstruction_c *i)
|
||||
op2_64 = BX_READ_64BIT_REG(i->rm());
|
||||
op1_64 ^= op2_64;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GqEqM(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_64 = BX_READ_64BIT_REG(i->nnn());
|
||||
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
|
||||
op1_64 ^= op2_64;
|
||||
|
||||
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
|
||||
@ -173,7 +189,23 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GqEqR(bxInstruction_c *i)
|
||||
op2_64 = BX_READ_64BIT_REG(i->rm());
|
||||
op1_64 |= op2_64;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GqEqM(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_64 = BX_READ_64BIT_REG(i->nnn());
|
||||
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
|
||||
op1_64 |= op2_64;
|
||||
|
||||
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
|
||||
@ -220,7 +252,23 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GqEqR(bxInstruction_c *i)
|
||||
op2_64 = BX_READ_64BIT_REG(i->rm());
|
||||
op1_64 &= op2_64;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GqEqM(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_64 = BX_READ_64BIT_REG(i->nnn());
|
||||
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
|
||||
op1_64 &= op2_64;
|
||||
|
||||
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
|
||||
@ -283,6 +331,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqGqR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqGqM(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_64 = read_virtual_qword_64(i->seg(), eaddr);
|
||||
op2_64 = BX_READ_64BIT_REG(i->nnn());
|
||||
op1_64 &= op2_64;
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_RAXId(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64;
|
||||
@ -309,4 +372,19 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqIdR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqIdM(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, op2_64;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1_64 = read_virtual_qword_64(i->seg(), eaddr);
|
||||
op2_64 = (Bit32s) i->Id();
|
||||
op1_64 &= op2_64;
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
#endif /* if BX_SUPPORT_X86_64 */
|
||||
|
@ -54,6 +54,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GbEbR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GbEbM(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1, op2;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
op2 = read_virtual_byte(i->seg(), eaddr);
|
||||
op1 ^= op2;
|
||||
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_ALIb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op_8 = AL ^ i->Ib();
|
||||
@ -170,6 +186,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GbEbR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GbEbM(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1, op2;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
op2 = read_virtual_byte(i->seg(), eaddr);
|
||||
op1 |= op2;
|
||||
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_ALIb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op_8 = AL | i->Ib();
|
||||
@ -210,6 +242,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GbEbR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GbEbM(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1, op2;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
op2 = read_virtual_byte(i->seg(), eaddr);
|
||||
op1 &= op2;
|
||||
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_ALIb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op_8 = AL & i->Ib();
|
||||
@ -261,6 +309,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbGbR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbGbM(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1, op2;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
op1 = read_virtual_byte(i->seg(), eaddr);
|
||||
op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
|
||||
op1 &= op2;
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_ALIb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op_8 = AL & i->Ib();
|
||||
@ -278,3 +341,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbIbR(bxInstruction_c *i)
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbIbM(bxInstruction_c *i)
|
||||
{
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
Bit8u op1 = read_virtual_byte(i->seg(), eaddr);
|
||||
op1 &= i->Ib();
|
||||
SET_FLAGS_OSZAPC_LOGIC_8(op1);
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user