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some cleanups and optimizations with new event interface

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This commit is contained in:
Stanislav Shwartsman 2012-10-03 15:49:45 +00:00
parent 16ee7f8936
commit 49bb3ba8f5
11 changed files with 36 additions and 35 deletions
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3
bochs/bochs.h
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@ -182,7 +182,8 @@ void print_tree(bx_param_c *node, int level = 0);
#define BX_TICK1() bx_pc_system.tick1()
#define BX_TICKN(n) bx_pc_system.tickn(n)
#define BX_INTR bx_pc_system.INTR
#define BX_SET_INTR(b) bx_pc_system.set_INTR(b)
#define BX_RAISE_INTR() bx_pc_system.raise_INTR()
#define BX_CLEAR_INTR() bx_pc_system.clear_INTR()
#define BX_HRQ bx_pc_system.HRQ
#if BX_SUPPORT_SMP

3
bochs/cpu/apic.cc
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@ -880,7 +880,6 @@ Bit8u bx_local_apic_c::acknowledge_int(void)
if(!INTR)
BX_PANIC(("APIC %d acknowledged an interrupt, but INTR=0", apic_id));
BX_ASSERT(INTR);
int vector = highest_priority_int(irr);
if (vector < 0) goto spurious;
if((vector & 0xf0) <= get_ppr()) goto spurious;
@ -893,13 +892,11 @@ Bit8u bx_local_apic_c::acknowledge_int(void)
print_status();
}
INTR = 0;
cpu->async_event = 1;
service_local_apic(); // will set INTR again if another is ready
return vector;
spurious:
INTR = 0;
cpu->async_event = 1;
return spurious_vector;
}

9
bochs/cpu/cpu.h
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@ -1105,7 +1105,7 @@ public: // for now...
BX_SMF BX_CPP_INLINE void signal_event(Bit32u event) {
BX_CPU_THIS_PTR pending_event |= event;
BX_CPU_THIS_PTR async_event = 1;
if (! is_masked_event(event)) BX_CPU_THIS_PTR async_event = 1;
}
BX_SMF BX_CPP_INLINE void clear_event(Bit32u event) {
@ -3976,7 +3976,6 @@ public: // for now...
#endif
BX_SMF void TLB_flush(void);
BX_SMF void TLB_invlpg(bx_address laddr);
BX_SMF void set_INTR(bx_bool value);
BX_SMF void inhibit_interrupts(unsigned mask);
BX_SMF bx_bool interrupts_inhibited(unsigned mask);
BX_SMF const char *strseg(bx_segment_reg_t *seg);
@ -4109,6 +4108,9 @@ public: // for now...
BX_SMF void smram_save_state(Bit32u *smm_saved_state);
BX_SMF bx_bool smram_restore_state(const Bit32u *smm_saved_state);
BX_SMF void raise_INTR(void);
BX_SMF void clear_INTR(void);
BX_SMF void deliver_INIT(void);
BX_SMF void deliver_NMI(void);
BX_SMF void deliver_SMI(void);
@ -4326,9 +4328,6 @@ public: // for now...
BX_SMF void VMexit_ExtInterrupt(void);
BX_SMF void VMexit_TaskSwitch(Bit16u tss_selector, unsigned source) BX_CPP_AttrRegparmN(2);
BX_SMF void VMexit_PAUSE(void);
#if BX_SUPPORT_VMX >= 2
BX_SMF void VMexit_PreemptionTimerExpired(void);
#endif
BX_SMF bx_bool VMexit_CLTS(void);
BX_SMF void VMexit_MSR(unsigned op, Bit32u msr) BX_CPP_AttrRegparmN(2);
BX_SMF void VMexit_IO(bxInstruction_c *i, unsigned port, unsigned len) BX_CPP_AttrRegparmN(3);

12
bochs/cpu/event.cc
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@ -251,7 +251,8 @@ bx_bool BX_CPU_C::handleAsyncEvent(void)
#if BX_SUPPORT_VMX >= 2
else if (is_unmasked_event_pending(BX_EVENT_VMX_PREEMPTION_TIMER_EXPIRED)) {
clear_event(BX_EVENT_VMX_PREEMPTION_TIMER_EXPIRED);
VMexit_PreemptionTimerExpired();
BX_DEBUG(("VMEXIT: VMX Preemption Timer Expired"));
VMexit(VMX_VMEXIT_VMX_PREEMPTION_TIMER_EXPIRED, 0);
}
#endif
#if BX_SUPPORT_VMX
@ -397,12 +398,17 @@ void BX_CPU_C::deliver_SMI(void)
signal_event(BX_EVENT_SMI);
}
void BX_CPU_C::set_INTR(bx_bool value)
void BX_CPU_C::raise_INTR(void)
{
BX_CPU_THIS_PTR INTR = value;
BX_CPU_THIS_PTR INTR = 1;
BX_CPU_THIS_PTR async_event = 1;
}
void BX_CPU_C::clear_INTR(void)
{
BX_CPU_THIS_PTR INTR = 0;
}
#if BX_DEBUGGER
void BX_CPU_C::dbg_take_irq(void)

2
bochs/cpu/init.cc
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@ -187,7 +187,7 @@ static bx_cpuid_t *cpuid_factory(BX_CPU_C *cpu)
// BX_CPU_C constructor
void BX_CPU_C::initialize(void)
{
BX_CPU_THIS_PTR set_INTR(0);
BX_CPU_THIS_PTR clear_INTR();
#if BX_CPU_LEVEL >= 4
BX_CPU_THIS_PTR cpuid = cpuid_factory(this);

3
bochs/cpu/proc_ctrl.cc
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@ -1066,8 +1066,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSCALL(bxInstruction_c *i)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.l = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0; /* available for use by system */
writeEFlags(read_eflags() & (~MSR_FMASK), EFlagsValidMask);
BX_CPU_THIS_PTR clear_RF();
writeEFlags(read_eflags() & ~MSR_FMASK & ~(EFlagsRFMask), EFlagsValidMask);
RIP = temp_RIP;
}
else

2
bochs/cpu/svm.cc
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@ -950,6 +950,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMRUN(bxInstruction_c *i)
BX_CPU_THIS_PTR in_svm_guest = 1;
BX_CPU_THIS_PTR svm_gif = 1;
BX_CPU_THIS_PTR async_event = 1;
//
// Step 4: Inject events to the guest
@ -1108,7 +1109,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CLGI(bxInstruction_c *i)
}
BX_CPU_THIS_PTR svm_gif = 0;
BX_CPU_THIS_PTR async_event = 1;
#endif
BX_NEXT_TRACE(i);

12
bochs/cpu/vmexit.cc
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@ -178,18 +178,6 @@ void BX_CPU_C::VMexit_ExtInterrupt(void)
}
}
#if BX_SUPPORT_VMX >= 2
void BX_CPU_C::VMexit_PreemptionTimerExpired(void)
{
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
if (PIN_VMEXIT(VMX_VM_EXEC_CTRL1_VMX_PREEMPTION_TIMER_VMEXIT)) {
BX_DEBUG(("VMEXIT: VMX Preemption Timer Expired"));
VMexit(VMX_VMEXIT_VMX_PREEMPTION_TIMER_EXPIRED, 0);
}
}
#endif
void BX_CPU_C::VMexit_Event(unsigned type, unsigned vector, Bit16u errcode, bx_bool errcode_valid, Bit64u qualification)
{
if (! BX_CPU_THIS_PTR in_vmx_guest) return;

6
bochs/iodev/pic.cc
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@ -295,7 +295,7 @@ void bx_pic_c::write(Bit32u address, Bit32u value, unsigned io_len)
else {
BX_DEBUG(("master: ICW1: edge triggered mode selected"));
}
BX_SET_INTR(0);
BX_CLEAR_INTR();
return;
}
@ -743,7 +743,7 @@ void bx_pic_c::service_master_pic(void)
BX_DEBUG(("signalling IRQ(%u)", (unsigned) irq));
BX_PIC_THIS s.master_pic.INT = 1;
BX_PIC_THIS s.master_pic.irq = irq;
BX_SET_INTR(1);
BX_RAISE_INTR();
return;
} /* if (unmasked_requests & ... */
}
@ -822,7 +822,7 @@ Bit8u bx_pic_c::IAC(void)
Bit8u vector;
Bit8u irq;
BX_SET_INTR(0);
BX_CLEAR_INTR();
BX_PIC_THIS s.master_pic.INT = 0;
// Check for spurious interrupt
if (BX_PIC_THIS s.master_pic.irr == 0) {

15
bochs/pc_system.cc
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@ -89,11 +89,20 @@ void bx_pc_system_c::set_HRQ(bx_bool val)
BX_CPU(0)->async_event = 1;
}
void bx_pc_system_c::set_INTR(bx_bool value)
void bx_pc_system_c::raise_INTR(void)
{
if (bx_dbg.interrupts)
BX_INFO(("pc_system: Setting INTR=%d on bootstrap processor %d", (int)value, BX_BOOTSTRAP_PROCESSOR));
BX_CPU(BX_BOOTSTRAP_PROCESSOR)->set_INTR(value);
BX_INFO(("pc_system: Setting INTR=1 on bootstrap processor %d", BX_BOOTSTRAP_PROCESSOR));
BX_CPU(BX_BOOTSTRAP_PROCESSOR)->raise_INTR();
}
void bx_pc_system_c::clear_INTR(void)
{
if (bx_dbg.interrupts)
BX_INFO(("pc_system: Setting INTR=0 on bootstrap processor %d", BX_BOOTSTRAP_PROCESSOR));
BX_CPU(BX_BOOTSTRAP_PROCESSOR)->clear_INTR();
}
//

4
bochs/pc_system.h
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@ -157,7 +157,9 @@ public:
volatile bx_bool kill_bochs_request;
void set_HRQ(bx_bool val); // set the Hold ReQuest line
void set_INTR(bx_bool value); // set the INTR line to value
void raise_INTR(void);
void clear_INTR(void);
// Cpu and System Reset
int Reset(unsigned type);