1356 lines
43 KiB
C++
1356 lines
43 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2012 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "param_names.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::UndefinedOpcode(bxInstruction_c *i)
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{
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BX_DEBUG(("UndefinedOpcode: generate #UD exception"));
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exception(BX_UD_EXCEPTION, 0);
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BX_NEXT_TRACE(i); // keep compiler happy
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOP(bxInstruction_c *i)
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{
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// No operation.
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PAUSE(bxInstruction_c *i)
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{
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#if BX_SUPPORT_VMX
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if (BX_CPU_THIS_PTR in_vmx_guest)
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VMexit_PAUSE();
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#endif
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_PAUSE)) Svm_Vmexit(SVM_VMEXIT_PAUSE);
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}
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#endif
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PREFETCH(bxInstruction_c *i)
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{
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#if BX_INSTRUMENTATION
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BX_INSTR_PREFETCH_HINT(BX_CPU_ID, i->src(), i->seg(), BX_CPU_CALL_METHODR(i->ResolveModrm, (i)));
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#endif
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CPUID(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL >= 4
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#if BX_SUPPORT_VMX
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if (BX_CPU_THIS_PTR in_vmx_guest) {
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BX_DEBUG(("VMEXIT: CPUID in VMX non-root operation"));
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VMexit(VMX_VMEXIT_CPUID, 0);
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}
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#endif
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_CPUID)) Svm_Vmexit(SVM_VMEXIT_CPUID);
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}
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#endif
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struct cpuid_function_t leaf;
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BX_CPU_THIS_PTR cpuid->get_cpuid_leaf(EAX, ECX, &leaf);
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RAX = leaf.eax;
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RBX = leaf.ebx;
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RCX = leaf.ecx;
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RDX = leaf.edx;
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#endif
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BX_NEXT_INSTR(i);
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}
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//
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// The shutdown state is very similar to the state following the exection
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// if HLT instruction. In this mode the processor stops executing
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// instructions until #NMI, #SMI, #RESET or #INIT is received. If
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// shutdown occurs why in NMI interrupt handler or in SMM, a hardware
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// reset must be used to restart the processor execution.
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//
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void BX_CPU_C::shutdown(void)
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{
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_SHUTDOWN)) Svm_Vmexit(SVM_VMEXIT_SHUTDOWN);
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}
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#endif
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BX_PANIC(("Entering to shutdown state still not implemented"));
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BX_CPU_THIS_PTR clear_IF();
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// artificial trap bit, why use another variable.
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BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_HLT;
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BX_CPU_THIS_PTR async_event = 1; // so processor knows to check
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// Execution of this instruction completes. The processor
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// will remain in a halt state until one of the above conditions
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// is met.
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BX_INSTR_HLT(BX_CPU_ID);
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#if BX_DEBUGGER
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bx_dbg_halt(BX_CPU_ID);
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#endif
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#if BX_USE_IDLE_HACK
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bx_gui->sim_is_idle();
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#endif
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longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::HLT(bxInstruction_c *i)
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{
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// CPL is always 0 in real mode
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if (/* !real_mode() && */ CPL!=0) {
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BX_DEBUG(("HLT: %s priveledge check failed, CPL=%d, generate #GP(0)",
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cpu_mode_string(BX_CPU_THIS_PTR cpu_mode), CPL));
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exception(BX_GP_EXCEPTION, 0);
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}
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if (! BX_CPU_THIS_PTR get_IF()) {
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BX_INFO(("WARNING: HLT instruction with IF=0!"));
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}
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#if BX_SUPPORT_VMX
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if (BX_CPU_THIS_PTR in_vmx_guest) {
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if (VMEXIT(VMX_VM_EXEC_CTRL2_HLT_VMEXIT)) {
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BX_DEBUG(("VMEXIT: HLT"));
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VMexit(VMX_VMEXIT_HLT, 0);
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}
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}
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#endif
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_HLT)) Svm_Vmexit(SVM_VMEXIT_HLT);
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}
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#endif
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// stops instruction execution and places the processor in a
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// HALT state. An enabled interrupt, NMI, or reset will resume
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// execution. If interrupt (including NMI) is used to resume
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// execution after HLT, the saved CS:eIP points to instruction
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// following HLT.
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// artificial trap bit, why use another variable.
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BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_HLT;
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BX_CPU_THIS_PTR async_event = 1; // so processor knows to check
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// Execution of this instruction completes. The processor
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// will remain in a halt state until one of the above conditions
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// is met.
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BX_INSTR_HLT(BX_CPU_ID);
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#if BX_DEBUGGER
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bx_dbg_halt(BX_CPU_ID);
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#endif
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#if BX_USE_IDLE_HACK
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bx_gui->sim_is_idle();
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#endif
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BX_NEXT_TRACE(i);
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}
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/* 0F 08 */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INVD(bxInstruction_c *i)
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{
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// CPL is always 0 in real mode
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if (/* !real_mode() && */ CPL!=0) {
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BX_ERROR(("INVD: priveledge check failed, generate #GP(0)"));
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exception(BX_GP_EXCEPTION, 0);
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}
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#if BX_SUPPORT_VMX
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if (BX_CPU_THIS_PTR in_vmx_guest) {
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BX_ERROR(("VMEXIT: INVD in VMX non-root operation"));
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VMexit(VMX_VMEXIT_INVD, 0);
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}
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#endif
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT0_INVD)) Svm_Vmexit(SVM_VMEXIT_INVD);
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}
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#endif
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invalidate_prefetch_q();
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BX_DEBUG(("INVD: Flush internal caches !"));
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BX_INSTR_CACHE_CNTRL(BX_CPU_ID, BX_INSTR_INVD);
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flushICaches();
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BX_NEXT_TRACE(i);
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}
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/* 0F 09 */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WBINVD(bxInstruction_c *i)
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{
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// CPL is always 0 in real mode
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if (/* !real_mode() && */ CPL!=0) {
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BX_ERROR(("WBINVD: priveledge check failed, generate #GP(0)"));
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exception(BX_GP_EXCEPTION, 0);
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}
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#if BX_SUPPORT_VMX
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if (BX_CPU_THIS_PTR in_vmx_guest) {
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if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_WBINVD_VMEXIT)) {
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BX_ERROR(("VMEXIT: WBINVD in VMX non-root operation"));
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VMexit(VMX_VMEXIT_WBINVD, 0);
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}
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}
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#endif
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(SVM_INTERCEPT1_WBINVD)) Svm_Vmexit(SVM_VMEXIT_WBINVD);
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}
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#endif
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//invalidate_prefetch_q();
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BX_DEBUG(("WBINVD: WB-Invalidate internal caches !"));
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BX_INSTR_CACHE_CNTRL(BX_CPU_ID, BX_INSTR_WBINVD);
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//flushICaches();
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BX_NEXT_TRACE(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CLFLUSH(bxInstruction_c *i)
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{
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[i->seg()];
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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bx_address laddr = get_laddr(i->seg(), eaddr);
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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if (! IsCanonical(laddr)) {
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BX_ERROR(("CLFLUSH: non-canonical access !"));
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exception(int_number(i->seg()), 0);
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}
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}
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else
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#endif
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{
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// check if we could access the memory segment
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if (!(seg->cache.valid & SegAccessROK)) {
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if (! execute_virtual_checks(seg, (Bit32u) eaddr, 1))
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exception(int_number(i->seg()), 0);
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}
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else {
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if (eaddr > seg->cache.u.segment.limit_scaled) {
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BX_ERROR(("CLFLUSH: segment limit violation"));
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exception(int_number(i->seg()), 0);
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}
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}
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}
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#if BX_INSTRUMENTATION
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bx_phy_address paddr =
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#endif
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translate_linear(laddr, USER_PL, BX_READ);
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BX_INSTR_CLFLUSH(BX_CPU_ID, laddr, paddr);
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#if BX_X86_DEBUGGER
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hwbreakpoint_match(laddr, 1, BX_READ);
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#endif
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BX_NEXT_INSTR(i);
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}
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void BX_CPU_C::handleCpuModeChange(void)
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{
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unsigned mode = BX_CPU_THIS_PTR cpu_mode;
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR efer.get_LMA()) {
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if (! BX_CPU_THIS_PTR cr0.get_PE()) {
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BX_PANIC(("change_cpu_mode: EFER.LMA is set when CR0.PE=0 !"));
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}
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l) {
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BX_CPU_THIS_PTR cpu_mode = BX_MODE_LONG_64;
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}
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else {
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BX_CPU_THIS_PTR cpu_mode = BX_MODE_LONG_COMPAT;
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// clear upper part of RIP/RSP when leaving 64-bit long mode
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BX_CLEAR_64BIT_HIGH(BX_64BIT_REG_RIP);
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BX_CLEAR_64BIT_HIGH(BX_64BIT_REG_RSP);
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}
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// switching between compatibility and long64 mode also affect SS.BASE
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// which is always zero in long64 mode
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invalidate_stack_cache();
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}
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else
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#endif
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{
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if (BX_CPU_THIS_PTR cr0.get_PE()) {
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if (BX_CPU_THIS_PTR get_VM()) {
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BX_CPU_THIS_PTR cpu_mode = BX_MODE_IA32_V8086;
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CPL = 3;
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}
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else
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BX_CPU_THIS_PTR cpu_mode = BX_MODE_IA32_PROTECTED;
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}
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else {
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BX_CPU_THIS_PTR cpu_mode = BX_MODE_IA32_REAL;
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// CS segment in real mode always allows full access
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
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CPL = 0;
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}
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}
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updateFetchModeMask();
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#if BX_CPU_LEVEL >= 6
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#if BX_SUPPORT_AVX
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handleAvxModeChange(); /* protected mode reloaded */
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#endif
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#endif
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if (mode != BX_CPU_THIS_PTR cpu_mode) {
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BX_DEBUG(("%s activated", cpu_mode_string(BX_CPU_THIS_PTR cpu_mode)));
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#if BX_DEBUGGER
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if (BX_CPU_THIS_PTR mode_break) {
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BX_CPU_THIS_PTR stop_reason = STOP_MODE_BREAK_POINT;
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bx_debug_break(); // trap into debugger
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}
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#endif
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}
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}
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#if BX_CPU_LEVEL >= 4
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void BX_CPU_C::handleAlignmentCheck(void)
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{
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if (CPL == 3 && BX_CPU_THIS_PTR cr0.get_AM() && BX_CPU_THIS_PTR get_AC()) {
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#if BX_SUPPORT_ALIGNMENT_CHECK == 0
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BX_PANIC(("WARNING: Alignment check (#AC exception) was not compiled in !"));
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#else
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BX_CPU_THIS_PTR alignment_check_mask = 0xF;
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#endif
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}
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#if BX_SUPPORT_ALIGNMENT_CHECK
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else {
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BX_CPU_THIS_PTR alignment_check_mask = 0;
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}
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#endif
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}
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#endif
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#if BX_CPU_LEVEL >= 6
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void BX_CPU_C::handleSseModeChange(void)
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{
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if(BX_CPU_THIS_PTR cr0.get_TS()) {
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BX_CPU_THIS_PTR sse_ok = 0;
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}
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else {
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if(BX_CPU_THIS_PTR cr0.get_EM() || !BX_CPU_THIS_PTR cr4.get_OSFXSR())
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BX_CPU_THIS_PTR sse_ok = 0;
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else
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BX_CPU_THIS_PTR sse_ok = 1;
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}
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updateFetchModeMask(); /* SSE_OK changed */
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BxNoSSE(bxInstruction_c *i)
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{
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if(BX_CPU_THIS_PTR cr0.get_EM() || !BX_CPU_THIS_PTR cr4.get_OSFXSR())
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exception(BX_UD_EXCEPTION, 0);
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if(BX_CPU_THIS_PTR cr0.get_TS())
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exception(BX_NM_EXCEPTION, 0);
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BX_ASSERT(0);
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BX_NEXT_TRACE(i); // keep compiler happy
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}
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#if BX_SUPPORT_AVX
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void BX_CPU_C::handleAvxModeChange(void)
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{
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if(BX_CPU_THIS_PTR cr0.get_TS()) {
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BX_CPU_THIS_PTR avx_ok = 0;
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}
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else {
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if (! protected_mode() || ! BX_CPU_THIS_PTR cr4.get_OSXSAVE() ||
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(~BX_CPU_THIS_PTR xcr0.val32 & 0x6) != 0) BX_CPU_THIS_PTR avx_ok = 0;
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else
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BX_CPU_THIS_PTR avx_ok = 1;
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}
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updateFetchModeMask(); /* AVX_OK changed */
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BxNoAVX(bxInstruction_c *i)
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{
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if (! protected_mode() || ! BX_CPU_THIS_PTR cr4.get_OSXSAVE())
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exception(BX_UD_EXCEPTION, 0);
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if (~BX_CPU_THIS_PTR xcr0.val32 & 0x6)
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exception(BX_UD_EXCEPTION, 0);
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if(BX_CPU_THIS_PTR cr0.get_TS())
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exception(BX_NM_EXCEPTION, 0);
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BX_ASSERT(0);
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BX_NEXT_TRACE(i); // keep compiler happy
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}
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#endif
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#endif
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void BX_CPU_C::handleCpuContextChange(void)
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{
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TLB_flush();
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invalidate_prefetch_q();
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invalidate_stack_cache();
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#if BX_CPU_LEVEL >= 4
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handleAlignmentCheck();
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#endif
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handleCpuModeChange();
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#if BX_CPU_LEVEL >= 6
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handleSseModeChange();
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#if BX_SUPPORT_AVX
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handleAvxModeChange();
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#endif
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#endif
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDPMC(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL >= 5
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if (! BX_CPU_THIS_PTR cr4.get_PCE() && CPL != 0 ) {
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BX_ERROR(("RDPMC: not allowed to use instruction !"));
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exception(BX_GP_EXCEPTION, 0);
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}
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#if BX_SUPPORT_VMX
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if (BX_CPU_THIS_PTR in_vmx_guest) {
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if (VMEXIT(VMX_VM_EXEC_CTRL2_RDPMC_VMEXIT)) {
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BX_DEBUG(("VMEXIT: RDPMC"));
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VMexit(VMX_VMEXIT_RDPMC, 0);
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}
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}
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#endif
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#if BX_SUPPORT_SVM
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
if (SVM_INTERCEPT(SVM_INTERCEPT0_RDPMC)) Svm_Vmexit(SVM_VMEXIT_RDPMC);
|
|
}
|
|
#endif
|
|
|
|
/* According to manual, Pentium 4 has 18 counters,
|
|
* previous versions have two. And the P4 also can do
|
|
* short read-out (EDX always 0). Otherwise it is
|
|
* limited to 40 bits.
|
|
*/
|
|
|
|
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_SSE2)) { // Pentium 4 processor (see cpuid.cc)
|
|
if ((ECX & 0x7fffffff) >= 18)
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
else {
|
|
if ((ECX & 0xffffffff) >= 2)
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
// Most counters are for hardware specific details, which
|
|
// we anyhow do not emulate (like pipeline stalls etc)
|
|
|
|
// Could be interesting to count number of memory reads,
|
|
// writes. Misaligned etc... But to monitor bochs, this
|
|
// is easier done from the host.
|
|
|
|
RAX = 0;
|
|
RDX = 0; // if P4 and ECX & 0x10000000, then always 0 (short read 32 bits)
|
|
|
|
BX_ERROR(("RDPMC: Performance Counters Support not implemented yet"));
|
|
#endif
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
#if BX_CPU_LEVEL >= 5
|
|
Bit64u BX_CPU_C::get_TSC(void)
|
|
{
|
|
Bit64u tsc = bx_pc_system.time_ticks() - BX_CPU_THIS_PTR tsc_last_reset;
|
|
#if BX_SUPPORT_VMX || BX_SUPPORT_SVM
|
|
tsc += BX_CPU_THIS_PTR tsc_offset;
|
|
#endif
|
|
return tsc;
|
|
}
|
|
|
|
void BX_CPU_C::set_TSC(Bit64u newval)
|
|
{
|
|
// compute the correct setting of tsc_last_reset so that a get_TSC()
|
|
// will return newval
|
|
BX_CPU_THIS_PTR tsc_last_reset = bx_pc_system.time_ticks() - newval;
|
|
|
|
// verify
|
|
BX_ASSERT(get_TSC() == newval);
|
|
}
|
|
#endif
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDTSC(bxInstruction_c *i)
|
|
{
|
|
#if BX_CPU_LEVEL >= 5
|
|
if (BX_CPU_THIS_PTR cr4.get_TSD() && CPL != 0) {
|
|
BX_ERROR(("RDTSC: not allowed to use instruction !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
#if BX_SUPPORT_VMX
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (VMEXIT(VMX_VM_EXEC_CTRL2_RDTSC_VMEXIT)) {
|
|
BX_DEBUG(("VMEXIT: RDTSC"));
|
|
VMexit(VMX_VMEXIT_RDTSC, 0);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#if BX_SUPPORT_SVM
|
|
if (BX_CPU_THIS_PTR in_svm_guest)
|
|
if (SVM_INTERCEPT(SVM_INTERCEPT0_RDTSC)) Svm_Vmexit(SVM_VMEXIT_RDTSC);
|
|
#endif
|
|
|
|
// return ticks
|
|
Bit64u ticks = BX_CPU_THIS_PTR get_TSC();
|
|
|
|
RAX = GET32L(ticks);
|
|
RDX = GET32H(ticks);
|
|
|
|
BX_DEBUG(("RDTSC: ticks 0x%08x:%08x", EDX, EAX));
|
|
#endif
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDTSCP(bxInstruction_c *i)
|
|
{
|
|
#if BX_SUPPORT_X86_64
|
|
|
|
#if BX_SUPPORT_VMX
|
|
// RDTSCP will always #UD in legacy VMX mode
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (! SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_RDTSCP)) {
|
|
BX_ERROR(("RDTSCP in VMX guest: not allowed to use instruction !"));
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
if (BX_CPU_THIS_PTR cr4.get_TSD() && CPL != 0) {
|
|
BX_ERROR(("RDTSCP: not allowed to use instruction !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
#if BX_SUPPORT_VMX
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (VMEXIT(VMX_VM_EXEC_CTRL2_RDTSC_VMEXIT)) {
|
|
BX_DEBUG(("VMEXIT: RDTSCP"));
|
|
VMexit(VMX_VMEXIT_RDTSCP, 0);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#if BX_SUPPORT_SVM
|
|
if (BX_CPU_THIS_PTR in_svm_guest)
|
|
if (SVM_INTERCEPT(SVM_INTERCEPT1_RDTSCP)) Svm_Vmexit(SVM_VMEXIT_RDTSCP);
|
|
#endif
|
|
|
|
// return ticks
|
|
Bit64u ticks = BX_CPU_THIS_PTR get_TSC();
|
|
|
|
RAX = GET32L(ticks);
|
|
RDX = GET32H(ticks);
|
|
RCX = MSR_TSC_AUX;
|
|
|
|
#endif
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
#if BX_SUPPORT_MONITOR_MWAIT
|
|
bx_bool BX_CPU_C::is_monitor(bx_phy_address begin_addr, unsigned len)
|
|
{
|
|
if (! BX_CPU_THIS_PTR monitor.armed) return 0;
|
|
|
|
bx_phy_address monitor_begin = BX_CPU_THIS_PTR monitor.monitor_addr;
|
|
bx_phy_address monitor_end = monitor_begin + CACHE_LINE_SIZE - 1;
|
|
|
|
bx_phy_address end_addr = begin_addr + len;
|
|
if (begin_addr >= monitor_end || end_addr <= monitor_begin)
|
|
return 0;
|
|
else
|
|
return 1;
|
|
}
|
|
|
|
void BX_CPU_C::check_monitor(bx_phy_address begin_addr, unsigned len)
|
|
{
|
|
if (is_monitor(begin_addr, len)) {
|
|
// wakeup from MWAIT state
|
|
if(BX_CPU_THIS_PTR activity_state >= BX_ACTIVITY_STATE_MWAIT)
|
|
BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_ACTIVE;
|
|
// clear monitor
|
|
BX_CPU_THIS_PTR monitor.reset_monitor();
|
|
}
|
|
}
|
|
#endif
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MONITOR(bxInstruction_c *i)
|
|
{
|
|
#if BX_SUPPORT_MONITOR_MWAIT
|
|
// CPL is always 0 in real mode
|
|
if (/* !real_mode() && */ CPL != 0) {
|
|
BX_DEBUG(("MWAIT instruction not recognized when CPL != 0"));
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
}
|
|
|
|
BX_DEBUG(("MONITOR instruction executed EAX = 0x%08x", EAX));
|
|
|
|
#if BX_SUPPORT_VMX
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (VMEXIT(VMX_VM_EXEC_CTRL2_MONITOR_VMEXIT)) {
|
|
BX_DEBUG(("VMEXIT: MONITOR"));
|
|
VMexit(VMX_VMEXIT_MONITOR, 0);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
if (RCX != 0) {
|
|
BX_ERROR(("MONITOR: no optional extensions supported"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[i->seg()];
|
|
|
|
bx_address offset = RAX & i->asize_mask();
|
|
|
|
// set MONITOR
|
|
bx_address laddr = get_laddr(i->seg(), offset);
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
|
|
if (! IsCanonical(laddr)) {
|
|
BX_ERROR(("MONITOR: non-canonical access !"));
|
|
exception(int_number(i->seg()), 0);
|
|
}
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
// check if we could access the memory segment
|
|
if (!(seg->cache.valid & SegAccessROK)) {
|
|
if (! execute_virtual_checks(seg, (Bit32u) offset, 1))
|
|
exception(int_number(i->seg()), 0);
|
|
}
|
|
else {
|
|
if (offset > seg->cache.u.segment.limit_scaled) {
|
|
BX_ERROR(("MONITOR: segment limit violation"));
|
|
exception(int_number(i->seg()), 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
bx_phy_address paddr = translate_linear(laddr, USER_PL, BX_READ);
|
|
|
|
#if BX_SUPPORT_SVM
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
if (SVM_INTERCEPT(SVM_INTERCEPT1_MONITOR)) Svm_Vmexit(SVM_VMEXIT_MONITOR);
|
|
}
|
|
#endif
|
|
|
|
// Set the monitor immediately. If monitor is still armed when we MWAIT,
|
|
// the processor will stall.
|
|
|
|
bx_pc_system.invlpg(paddr);
|
|
|
|
BX_CPU_THIS_PTR monitor.arm(paddr);
|
|
|
|
BX_DEBUG(("MONITOR for phys_addr=0x" FMT_PHY_ADDRX, BX_CPU_THIS_PTR monitor.monitor_addr));
|
|
#endif
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MWAIT(bxInstruction_c *i)
|
|
{
|
|
#if BX_SUPPORT_MONITOR_MWAIT
|
|
// CPL is always 0 in real mode
|
|
if (/* !real_mode() && */ CPL != 0) {
|
|
BX_DEBUG(("MWAIT instruction not recognized when CPL != 0"));
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
}
|
|
|
|
BX_DEBUG(("MWAIT instruction executed ECX = 0x%08x", ECX));
|
|
|
|
#if BX_SUPPORT_VMX
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (VMEXIT(VMX_VM_EXEC_CTRL2_MWAIT_VMEXIT)) {
|
|
BX_DEBUG(("VMEXIT: MWAIT"));
|
|
VMexit(VMX_VMEXIT_MWAIT, BX_CPU_THIS_PTR monitor.armed);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
// only one extension is supported
|
|
// ECX[0] - interrupt MWAIT even if EFLAGS.IF = 0
|
|
if (RCX & ~(BX_CONST64(1))) {
|
|
BX_ERROR(("MWAIT: incorrect optional extensions in RCX"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
#if BX_SUPPORT_SVM
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
if (SVM_INTERCEPT(SVM_INTERCEPT1_MWAIT_ARMED))
|
|
if (BX_CPU_THIS_PTR monitor.armed) Svm_Vmexit(SVM_VMEXIT_MWAIT_CONDITIONAL);
|
|
|
|
if (SVM_INTERCEPT(SVM_INTERCEPT1_MWAIT)) Svm_Vmexit(SVM_VMEXIT_MWAIT);
|
|
}
|
|
#endif
|
|
|
|
// If monitor has already triggered, we just return.
|
|
if (! BX_CPU_THIS_PTR monitor.armed) {
|
|
BX_DEBUG(("MWAIT: the MONITOR was not armed or already triggered"));
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
static bx_bool mwait_is_nop = SIM->get_param_bool(BXPN_MWAIT_IS_NOP)->get();
|
|
if (mwait_is_nop) {
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
// stops instruction execution and places the processor in a optimized
|
|
// state. Events that cause exit from MWAIT state are:
|
|
// A store from another processor to monitored range, any unmasked
|
|
// interrupt, including INTR, NMI, SMI, INIT or reset will resume
|
|
// the execution. Any far control transfer between MONITOR and MWAIT
|
|
// resets the monitoring logic.
|
|
|
|
if (ECX & 1) {
|
|
#if BX_SUPPORT_VMX
|
|
// When "interrupt window exiting" VMX control is set MWAIT instruction
|
|
// won't cause the processor to enter sleep state with EFLAGS.IF = 0
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
if (VMEXIT(VMX_VM_EXEC_CTRL2_INTERRUPT_WINDOW_VMEXIT) && ! BX_CPU_THIS_PTR get_IF()) {
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
}
|
|
#endif
|
|
BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_MWAIT_IF;
|
|
}
|
|
else {
|
|
BX_CPU_THIS_PTR activity_state = BX_ACTIVITY_STATE_MWAIT;
|
|
}
|
|
|
|
BX_CPU_THIS_PTR async_event = 1; // so processor knows to check
|
|
// Execution of this instruction completes. The processor
|
|
// will remain in a optimized state until one of the above
|
|
// conditions is met.
|
|
|
|
BX_INSTR_MWAIT(BX_CPU_ID, BX_CPU_THIS_PTR monitor.monitor_addr, CACHE_LINE_SIZE, ECX);
|
|
|
|
#if BX_USE_IDLE_HACK
|
|
bx_gui->sim_is_idle();
|
|
#endif
|
|
|
|
#if BX_DEBUGGER
|
|
bx_dbg_halt(BX_CPU_ID);
|
|
#endif
|
|
#endif
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSENTER(bxInstruction_c *i)
|
|
{
|
|
#if BX_CPU_LEVEL >= 6
|
|
if (real_mode()) {
|
|
BX_ERROR(("SYSENTER not recognized in real mode !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
if ((BX_CPU_THIS_PTR msr.sysenter_cs_msr & BX_SELECTOR_RPL_MASK) == 0) {
|
|
BX_ERROR(("SYSENTER with zero sysenter_cs_msr !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
BX_CPU_THIS_PTR clear_VM(); // do this just like the book says to do
|
|
BX_CPU_THIS_PTR clear_IF();
|
|
BX_CPU_THIS_PTR clear_RF();
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (long_mode()) {
|
|
if (!IsCanonical(BX_CPU_THIS_PTR msr.sysenter_eip_msr)) {
|
|
BX_ERROR(("SYSENTER with non-canonical SYSENTER_EIP_MSR !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
if (!IsCanonical(BX_CPU_THIS_PTR msr.sysenter_esp_msr)) {
|
|
BX_ERROR(("SYSENTER with non-canonical SYSENTER_ESP_MSR !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
parse_selector(BX_CPU_THIS_PTR msr.sysenter_cs_msr & BX_SELECTOR_RPL_MASK,
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; // base address
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; // 4k granularity
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; // available for use by system
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = !long_mode();
|
|
#if BX_SUPPORT_X86_64
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = long_mode();
|
|
#endif
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
handleCpuModeChange(); // mode change could happen only when in long_mode()
|
|
#else
|
|
updateFetchModeMask(/* CS reloaded */);
|
|
#endif
|
|
|
|
#if BX_SUPPORT_ALIGNMENT_CHECK
|
|
BX_CPU_THIS_PTR alignment_check_mask = 0; // CPL=0
|
|
#endif
|
|
|
|
parse_selector((BX_CPU_THIS_PTR msr.sysenter_cs_msr + 8) & BX_SELECTOR_RPL_MASK,
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; // base address
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 1; // 4k granularity
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; // 32-bit mode
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0; // available for use by system
|
|
#if BX_SUPPORT_X86_64
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.l = 0;
|
|
#endif
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (long_mode()) {
|
|
RSP = BX_CPU_THIS_PTR msr.sysenter_esp_msr;
|
|
RIP = BX_CPU_THIS_PTR msr.sysenter_eip_msr;
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
ESP = (Bit32u) BX_CPU_THIS_PTR msr.sysenter_esp_msr;
|
|
EIP = (Bit32u) BX_CPU_THIS_PTR msr.sysenter_eip_msr;
|
|
}
|
|
|
|
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_SYSENTER,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
|
|
#endif
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSEXIT(bxInstruction_c *i)
|
|
{
|
|
#if BX_CPU_LEVEL >= 6
|
|
if (real_mode() || CPL != 0) {
|
|
BX_ERROR(("SYSEXIT from real mode or with CPL<>0 !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
if ((BX_CPU_THIS_PTR msr.sysenter_cs_msr & BX_SELECTOR_RPL_MASK) == 0) {
|
|
BX_ERROR(("SYSEXIT with zero sysenter_cs_msr !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (i->os64L()) {
|
|
if (!IsCanonical(RDX)) {
|
|
BX_ERROR(("SYSEXIT with non-canonical RDX (RIP) pointer !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
if (!IsCanonical(RCX)) {
|
|
BX_ERROR(("SYSEXIT with non-canonical RCX (RSP) pointer !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
parse_selector(((BX_CPU_THIS_PTR msr.sysenter_cs_msr + 32) & BX_SELECTOR_RPL_MASK) | 3,
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; // base address
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; // 4k granularity
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; // available for use by system
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 1;
|
|
|
|
RSP = RCX;
|
|
RIP = RDX;
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
parse_selector(((BX_CPU_THIS_PTR msr.sysenter_cs_msr + 16) & BX_SELECTOR_RPL_MASK) | 3,
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; // base address
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; // 4k granularity
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; // available for use by system
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1;
|
|
#if BX_SUPPORT_X86_64
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0;
|
|
#endif
|
|
|
|
ESP = ECX;
|
|
EIP = EDX;
|
|
}
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
handleCpuModeChange(); // mode change could happen only when in long_mode()
|
|
#else
|
|
updateFetchModeMask(/* CS reloaded */);
|
|
#endif
|
|
|
|
handleAlignmentCheck(/* CPL change */);
|
|
|
|
parse_selector(((BX_CPU_THIS_PTR msr.sysenter_cs_msr + (i->os64L() ? 40:24)) & BX_SELECTOR_RPL_MASK) | 3,
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 3;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; // base address
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 1; // 4k granularity
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; // 32-bit mode
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0; // available for use by system
|
|
#if BX_SUPPORT_X86_64
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.l = 0;
|
|
#endif
|
|
|
|
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_SYSEXIT,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
|
|
#endif
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSCALL(bxInstruction_c *i)
|
|
{
|
|
#if BX_CPU_LEVEL >= 5
|
|
bx_address temp_RIP;
|
|
|
|
BX_DEBUG(("Execute SYSCALL instruction"));
|
|
|
|
if (!BX_CPU_THIS_PTR efer.get_SCE()) {
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
}
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (long_mode())
|
|
{
|
|
RCX = RIP;
|
|
R11 = read_eflags() & ~(EFlagsRFMask);
|
|
|
|
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
|
|
temp_RIP = MSR_LSTAR;
|
|
}
|
|
else {
|
|
temp_RIP = MSR_CSTAR;
|
|
}
|
|
|
|
// set up CS segment, flat, 64-bit DPL=0
|
|
parse_selector((MSR_STAR >> 32) & BX_SELECTOR_RPL_MASK,
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; /* base address */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; /* 4k granularity */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 1; /* 64-bit code */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; /* available for use by system */
|
|
|
|
handleCpuModeChange(); // mode change could only happen when in long_mode()
|
|
|
|
#if BX_SUPPORT_ALIGNMENT_CHECK
|
|
BX_CPU_THIS_PTR alignment_check_mask = 0; // CPL=0
|
|
#endif
|
|
|
|
// set up SS segment, flat, 64-bit DPL=0
|
|
parse_selector(((MSR_STAR >> 32) + 8) & BX_SELECTOR_RPL_MASK,
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; /* base address */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 1; /* 4k granularity */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; /* 32 bit stack */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.l = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0; /* available for use by system */
|
|
|
|
writeEFlags(read_eflags() & ~MSR_FMASK & ~(EFlagsRFMask), EFlagsValidMask);
|
|
RIP = temp_RIP;
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
// legacy mode
|
|
|
|
ECX = EIP;
|
|
temp_RIP = MSR_STAR & 0xFFFFFFFF;
|
|
|
|
// set up CS segment, flat, 32-bit DPL=0
|
|
parse_selector((MSR_STAR >> 32) & BX_SELECTOR_RPL_MASK,
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; /* base address */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; /* 4k granularity */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1;
|
|
#if BX_SUPPORT_X86_64
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 32-bit code */
|
|
#endif
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; /* available for use by system */
|
|
|
|
updateFetchModeMask(/* CS reloaded */);
|
|
|
|
#if BX_SUPPORT_ALIGNMENT_CHECK
|
|
BX_CPU_THIS_PTR alignment_check_mask = 0; // CPL=0
|
|
#endif
|
|
|
|
// set up SS segment, flat, 32-bit DPL=0
|
|
parse_selector(((MSR_STAR >> 32) + 8) & BX_SELECTOR_RPL_MASK,
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; /* base address */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 1; /* 4k granularity */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; /* 32 bit stack */
|
|
#if BX_SUPPORT_X86_64
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.l = 0;
|
|
#endif
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0; /* available for use by system */
|
|
|
|
BX_CPU_THIS_PTR clear_VM();
|
|
BX_CPU_THIS_PTR clear_IF();
|
|
BX_CPU_THIS_PTR clear_RF();
|
|
RIP = temp_RIP;
|
|
}
|
|
|
|
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_SYSCALL,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
|
|
#endif
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSRET(bxInstruction_c *i)
|
|
{
|
|
#if BX_CPU_LEVEL >= 5
|
|
bx_address temp_RIP;
|
|
|
|
BX_DEBUG(("Execute SYSRET instruction"));
|
|
|
|
if (!BX_CPU_THIS_PTR efer.get_SCE()) {
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
}
|
|
|
|
if(!protected_mode() || CPL != 0) {
|
|
BX_ERROR(("SYSRET: priveledge check failed, generate #GP(0)"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
|
|
{
|
|
if (i->os64L()) {
|
|
if (!IsCanonical(RCX)) {
|
|
BX_ERROR(("SYSRET: canonical failure for RCX (RIP)"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
// Return to 64-bit mode, set up CS segment, flat, 64-bit DPL=3
|
|
parse_selector((((MSR_STAR >> 48) + 16) & BX_SELECTOR_RPL_MASK) | 3,
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; /* base address */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; /* 4k granularity */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 0;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 1; /* 64-bit code */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; /* available for use by system */
|
|
|
|
temp_RIP = RCX;
|
|
}
|
|
else {
|
|
// Return to 32-bit compatibility mode, set up CS segment, flat, 32-bit DPL=3
|
|
parse_selector((MSR_STAR >> 48) | 3,
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; /* base address */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; /* 4k granularity */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 32-bit code */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; /* available for use by system */
|
|
|
|
temp_RIP = ECX;
|
|
}
|
|
|
|
handleCpuModeChange(); // mode change could only happen when in long64 mode
|
|
|
|
handleAlignmentCheck(/* CPL change */);
|
|
|
|
// SS base, limit, attributes unchanged
|
|
parse_selector((Bit16u)(((MSR_STAR >> 48) + 8) | 3),
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 3;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
|
|
|
|
writeEFlags((Bit32u) R11, EFlagsValidMask);
|
|
}
|
|
else // (!64BIT_MODE)
|
|
#endif
|
|
{
|
|
// Return to 32-bit legacy mode, set up CS segment, flat, 32-bit DPL=3
|
|
parse_selector((MSR_STAR >> 48) | 3,
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; /* base address */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; /* 4k granularity */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1;
|
|
#if BX_SUPPORT_X86_64
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 32-bit code */
|
|
#endif
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; /* available for use by system */
|
|
|
|
updateFetchModeMask(/* CS reloaded */);
|
|
|
|
handleAlignmentCheck(/* CPL change */);
|
|
|
|
// SS base, limit, attributes unchanged
|
|
parse_selector((Bit16u)(((MSR_STAR >> 48) + 8) | 3),
|
|
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector);
|
|
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = SegValidCache | SegAccessROK | SegAccessWOK;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 3;
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
|
|
|
|
BX_CPU_THIS_PTR assert_IF();
|
|
temp_RIP = ECX;
|
|
}
|
|
|
|
handleCpuModeChange();
|
|
|
|
RIP = temp_RIP;
|
|
|
|
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_SYSRET,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
|
|
#endif
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SWAPGS(bxInstruction_c *i)
|
|
{
|
|
if(CPL != 0)
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
Bit64u temp_GS_base = MSR_GSBASE;
|
|
MSR_GSBASE = MSR_KERNELGSBASE;
|
|
MSR_KERNELGSBASE = temp_GS_base;
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
/* F3 0F AE /0 */
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDFSBASE(bxInstruction_c *i)
|
|
{
|
|
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
if (i->os64L()) {
|
|
BX_WRITE_64BIT_REG(i->dst(), MSR_FSBASE);
|
|
}
|
|
else {
|
|
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) MSR_FSBASE);
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
/* F3 0F AE /1 */
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDGSBASE(bxInstruction_c *i)
|
|
{
|
|
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
if (i->os64L()) {
|
|
BX_WRITE_64BIT_REG(i->dst(), MSR_GSBASE);
|
|
}
|
|
else {
|
|
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) MSR_GSBASE);
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
/* F3 0F AE /2 */
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRFSBASE(bxInstruction_c *i)
|
|
{
|
|
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
if (i->os64L()) {
|
|
Bit64u fsbase = BX_READ_64BIT_REG(i->src());
|
|
if (!IsCanonical(fsbase)) {
|
|
BX_ERROR(("WRFSBASE: canonical failure !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
MSR_FSBASE = fsbase;
|
|
}
|
|
else {
|
|
// 32-bit value is always canonical
|
|
MSR_FSBASE = BX_READ_32BIT_REG(i->src());
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
/* F3 0F AE /3 */
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRGSBASE(bxInstruction_c *i)
|
|
{
|
|
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
if (i->os64L()) {
|
|
Bit64u gsbase = BX_READ_64BIT_REG(i->src());
|
|
if (!IsCanonical(gsbase)) {
|
|
BX_ERROR(("WRGSBASE: canonical failure !"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
MSR_GSBASE = gsbase;
|
|
}
|
|
else {
|
|
// 32-bit value is always canonical
|
|
MSR_GSBASE = BX_READ_32BIT_REG(i->src());
|
|
}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|
|
|
|
#endif
|