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updates in CPUID defines after new published AMD SDM

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This commit is contained in:
Stanislav Shwartsman 2013-05-17 19:41:57 +00:00
parent 1304b3fb4b
commit 2bca9b8273
3 changed files with 18 additions and 1 deletions
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10
bochs/cpu/cpuid.h
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@ -397,7 +397,10 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// [22:22] Topology extensions support
// [23:23] PerfCtrExtCore: core performance counter extensions support
// [24:24] PerfCtrExtNB: NB performance counter extensions support
// [31:25] reserved
// [25:25] Streaming performance monitor architecture.
// [26:26] Data breakpoint extension. Indicates support for MSR 0xC0011027 and MSRs 0xC001101[B:9].
// [27:27] Performance time-stamp counter. Indicates support for MSR 0xC0010280.
// [31:28] reserved
#define BX_CPUID_EXT2_LAHF_SAHF (1 << 0)
#define BX_CPUID_EXT2_CMP_LEGACY (1 << 1)
@ -424,6 +427,9 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
#define BX_CPUID_EXT2_TOPOLOGY_EXTENSIONS (1 << 22)
#define BX_CPUID_EXT2_PERFCTR_EXT_CORE (1 << 23)
#define BX_CPUID_EXT2_PERFCTR_EXT_NB (1 << 24)
#define BX_CPUID_EXT2_STREAMING_PERFMON (1 << 25)
#define BX_CPUID_EXT2_DATA_BREAKPOINT_EXT (1 << 26)
#define BX_CPUID_EXT2_PERF_TSC (1 << 27)
// CPUID defines - SVM features CPUID[0x8000000A].EDX
// ----------------------------
@ -441,6 +447,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// [10:10] Pause filter support
// [11:11] Reserved
// [12:12] Pause filter threshold support
// [13:13] Advanced Virtual Interrupt Controller
#define BX_CPUID_SVM_NESTED_PAGING (1 << 0)
#define BX_CPUID_SVM_LBR_VIRTUALIZATION (1 << 1)
@ -455,5 +462,6 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
#define BX_CPUID_SVM_PAUSE_FILTER (1 << 10)
#define BX_CPUID_SVM_RESERVED11 (1 << 11)
#define BX_CPUID_SVM_PAUSE_FILTER_THRESHOLD (1 << 12)
#define BX_CPUID_SVM_AVIC (1 << 13)
#endif

8
bochs/cpu/svm.h
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@ -90,6 +90,8 @@ enum SVM_intercept_codes {
SVM_VMEXIT_MWAIT_CONDITIONAL = 140,
SVM_VMEXIT_XSETBV = 141,
SVM_VMEXIT_NPF = 1024,
SVM_VMEXIT_AVIC_INCOMPLETE_IPI = 1025,
SVM_VMEXIT_AVIC_NOACCEL = 1026
};
#define SVM_VMEXIT_INVALID (-1)
@ -126,6 +128,8 @@ enum SVM_intercept_codes {
#define SVM_CONTROL32_EXITINTINFO_ERROR_CODE (0x08c)
#define SVM_CONTROL_NESTED_PAGING_ENABLE (0x090)
#define SVM_VIRTUAL_APIC_BAR (0x098)
#define SVM_CONTROL32_EVENT_INJECTION (0x0a8)
#define SVM_CONTROL32_EVENT_INJECTION_ERRORCODE (0x0ac)
#define SVM_CONTROL64_NESTED_PAGING_HOST_CR3 (0x0b0)
@ -136,6 +140,10 @@ enum SVM_intercept_codes {
#define SVM_CONTROL64_GUEST_INSTR_BYTES (0x0d0)
#define SVM_CONTROL64_GUEST_INSTR_BYTES_HI (0x0d8)
#define SVM_AVIC_BACKING_PAGE (0x0e0)
#define SVM_AVIC_LOGICAL_TABLE_PTR (0x0f0)
#define SVM_AVIC_PHYSICAL_TABLE_PTR (0x0f8)
// ======================
// VMCB save state area
// ======================

1
bochs/cpu/todo
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@ -51,6 +51,7 @@ TODO (know issues in CPU model):
[!] SVM:
- Decoding assists, pause filter, VMCB clean are not implemented yet
- Advanced Virtual Interrupt Controller (AVIC) not implemented yet
- More?
[!] AMD misaligned SSE mode should convert #GP on misaligned SSE access to #AC