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added evex decode tables - next step to populate them :)

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This commit is contained in:
Stanislav Shwartsman 2013-09-15 20:48:39 +00:00
parent 1e1fa45cac
commit 0cb0acc30f
15 changed files with 1892 additions and 66 deletions
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4
bochs/cpu/Makefile.in
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@ -403,7 +403,7 @@ fetchdecode64.o: fetchdecode64.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
fpu/softfloat.h fpu/tag_w.h fpu/status_w.h fpu/control_w.h xmm.h vmx.h stack.h \
fetchdecode.h fetchdecode_x87.h fetchdecode_sse.h fetchdecode_avx.h \
fetchdecode_xop.h
fetchdecode_xop.h fetchdecode_evex.h
fetchdecode.o: fetchdecode.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../gui/siminterface.h \
../cpudb.h ../gui/paramtree.h ../memory/memory.h ../pc_system.h \
@ -411,7 +411,7 @@ fetchdecode.o: fetchdecode.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
fpu/softfloat.h fpu/tag_w.h fpu/status_w.h fpu/control_w.h xmm.h vmx.h stack.h \
fetchdecode.h fetchdecode_x87.h fetchdecode_sse.h fetchdecode_avx.h \
fetchdecode_xop.h
fetchdecode_xop.h fetchdecode_evex.h
flag_ctrl.o: flag_ctrl.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../gui/siminterface.h \
../cpudb.h ../gui/paramtree.h ../memory/memory.h ../pc_system.h \

20
bochs/cpu/avx2.cc
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@ -289,10 +289,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTB_VdqWb(bxInstruction_c
unsigned len = i->getVL();
BxPackedYmmRegister op;
Bit8u val_8 = BX_READ_XMM_REG_LO_BYTE(i->src());
for (unsigned n=0; n < len; n++)
sse_pbroadcastb(&op.ymm128(n), val_8);
simd_pbroadcastb(op.ymm_ubyteptr(), BX_READ_XMM_REG_LO_BYTE(i->src()), len*16);
BX_WRITE_YMM_REGZ_VLEN(i->dst(), op, len);
@ -304,10 +301,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTW_VdqWw(bxInstruction_c
unsigned len = i->getVL();
BxPackedYmmRegister op;
Bit16u val_16 = BX_READ_XMM_REG_LO_WORD(i->src());
for (unsigned n=0; n < len; n++)
sse_pbroadcastw(&op.ymm128(n), val_16);
simd_pbroadcastw(op.ymm_u16ptr(), BX_READ_XMM_REG_LO_WORD(i->src()), len*8);
BX_WRITE_YMM_REGZ_VLEN(i->dst(), op, len);
@ -319,10 +313,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTD_VdqWd(bxInstruction_c
unsigned len = i->getVL();
BxPackedYmmRegister op;
Bit32u val_32 = BX_READ_XMM_REG_LO_DWORD(i->src());
for (unsigned n=0; n < len; n++)
sse_pbroadcastd(&op.ymm128(n), val_32);
simd_pbroadcastd(op.ymm_u32ptr(), BX_READ_XMM_REG_LO_DWORD(i->src()), len*4);
BX_WRITE_YMM_REGZ_VLEN(i->dst(), op, len);
@ -334,10 +325,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTQ_VdqWq(bxInstruction_c
unsigned len = i->getVL();
BxPackedYmmRegister op;
Bit64u val_64 = BX_READ_XMM_REG_LO_QWORD(i->src());
for (unsigned n=0; n < len; n++)
sse_pbroadcastq(&op.ymm128(n), val_64);
simd_pbroadcastq(op.ymm_u64ptr(), BX_READ_XMM_REG_LO_QWORD(i->src()), len*2);
BX_WRITE_YMM_REGZ_VLEN(i->dst(), op, len);

4
bochs/cpu/cpu.h
View File

@ -2116,6 +2116,10 @@ public: // for now...
BX_SMF BX_INSF_TYPE LOAD_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE LOAD_Half_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
#if BX_SUPPORT_EVEX
BX_SMF BX_INSF_TYPE LOAD_BROADCAST_VectorD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE LOAD_BROADCAST_VectorQ(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
#if BX_SUPPORT_FPU == 0 // if FPU is disabled
BX_SMF BX_INSF_TYPE FPU_ESC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);

52
bochs/cpu/fetchdecode.cc
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@ -1289,6 +1289,10 @@ BX_CPU_C::fetchDecode32(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
bx_bool vex_w = 0, vex_l = 0, use_vvv = 0;
#endif
#if BX_SUPPORT_EVEX
unsigned evex_rc = 0;
#endif
os_32 = is_32 =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b;
@ -1412,6 +1416,54 @@ fetch_b1:
OpcodeInfoPtr = &BxOpcodeTableAVX[(opcode_byte-256)*2 + vex_l];
}
#if BX_SUPPORT_EVEX
else if (b1 == 0x62 && (*iptr & 0xc0) == 0xc0) {
had_vex_xop = 1;
if (sse_prefix || ! protected_mode())
goto decode_done;
Bit32u evex;
if (remain > 3) {
evex = FetchDWORD(iptr);
iptr += 4;
remain -= 4;
}
else {
return(-1);
}
// check for reserved EVEX bits
if ((evex & 0x0c) != 0 || (evex & 0x400) == 0)
goto decode_done;
unsigned evex_opcext = evex & 0x3;
if (evex_opcext == 0)
goto decode_done;
sse_prefix = (evex >> 8) & 0x3;
vvv = 15 - ((evex >> 11) & 0xf);
if (vvv >= 8)
goto decode_done;
vex_w = (evex >> 15) & 0x1;
unsigned opmask = (evex >> 16) & 0x7;
i->setOpmask(opmask);
unsigned evex_v = ((evex >> 19) & 0x1) ^ 0x1;
if (evex_v)
goto decode_done;
unsigned evex_b = (evex >> 20) & 0x1;
i->setBroadcast(evex_b);
evex_rc = (evex >> 21) & 0x3;
unsigned evex_z = (evex >> 23) & 0x1;
i->setZeroMasking(evex_z);
unsigned opcode_byte = (evex >> 24);
opcode_byte += 256 * (evex_opcext-1);
has_modrm = 1;
OpcodeInfoPtr = &BxOpcodeTableEVEX[opcode_byte*2 + (opmask != 0)];
}
#endif
else if (b1 == 0x8f && (*iptr & 0xc8) == 0xc8) {
// 3 byte XOP prefix
had_vex_xop = 1;

12
bochs/cpu/fetchdecode.h
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@ -59,8 +59,9 @@ BX_CPP_INLINE Bit64u FetchQWORD(const Bit8u *iptr)
}
#endif
#define BX_PREPARE_SSE (0x80)
#define BX_PREPARE_AVX (0x40)
#define BX_PREPARE_SSE (0x80)
#define BX_PREPARE_AVX (0x40)
#define BX_PREPARE_EVEX (0x20)
struct bxIAOpcodeTable {
BxExecutePtr_tR execute1;
@ -88,8 +89,15 @@ enum {
#include "fetchdecode_x87.h"
#include "fetchdecode_sse.h"
#if BX_SUPPORT_AVX
#include "fetchdecode_avx.h"
#include "fetchdecode_xop.h"
#endif
#if BX_SUPPORT_EVEX
#include "fetchdecode_evex.h"
#endif
/* ************************************************************************ */
/* Opcode Groups */

48
bochs/cpu/fetchdecode64.cc
View File

@ -1708,6 +1708,11 @@ BX_CPU_C::fetchDecode64(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
bx_bool vex_w = 0, vex_l = 0, use_vvv = 0;
#endif
#if BX_SUPPORT_EVEX
unsigned evex_rc = 0;
bx_bool evex_v = 0;
#endif
i->ResolveModrm = 0;
i->init(/*os32*/ 1, // operand size 32 override defaults to 1
/*as32*/ 1, // address size 32 override defaults to 1
@ -1878,6 +1883,49 @@ fetch_b1:
OpcodeInfoPtr = &BxOpcodeTableAVX[(opcode_byte-256)*2 + vex_l];
}
#if BX_SUPPORT_EVEX
else if (b1 == 0x62) {
had_vex_xop = 1;
if (sse_prefix || ! protected_mode())
goto decode_done;
Bit32u evex;
if (remain > 3) {
evex = FetchDWORD(iptr);
iptr += 4;
remain -= 4;
}
else {
return(-1);
}
// check for reserved EVEX bits
if ((evex & 0x0c) != 0 || (evex & 0x400) == 0)
goto decode_done;
unsigned evex_opcext = evex & 0x3;
if (evex_opcext == 0)
goto decode_done;
sse_prefix = (evex >> 8) & 0x3;
vvv = 15 - ((evex >> 11) & 0xf);
vex_w = (evex >> 15) & 0x1;
unsigned opmask = (evex >> 16) & 0x7;
i->setOpmask(opmask);
evex_v = ((evex >> 19) & 0x1) ^ 0x1;
unsigned evex_b = (evex >> 20) & 0x1;
i->setBroadcast(evex_b);
evex_rc = (evex >> 21) & 0x3;
unsigned evex_z = (evex >> 23) & 0x1;
i->setZeroMasking(evex_z);
unsigned opcode_byte = (evex >> 24);
opcode_byte += 256 * (evex_opcext-1);
has_modrm = 1;
OpcodeInfoPtr = &BxOpcodeTableEVEX[opcode_byte*2 + (opmask != 0)];
}
#endif
else if (b1 == 0x8f && (*iptr & 0x08) == 0x08) {
// 3 byte XOP prefix
had_vex_xop = 1;

4
bochs/cpu/fetchdecode_avx.h
View File

@ -24,7 +24,7 @@
#ifndef BX_AVX_FETCHDECODE_TABLES_H
#define BX_AVX_FETCHDECODE_TABLES_H
#if BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
#if BX_SUPPORT_AVX
/* ************************************************************************ */
@ -2069,6 +2069,6 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3*2] = {
/* FF /1 */ { 0, BX_IA_ERROR }
};
#endif // BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
#endif // BX_SUPPORT_AVX
#endif // BX_AVX_FETCHDECODE_TABLES_H

1577
bochs/cpu/fetchdecode_evex.h Normal file
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File diff suppressed because it is too large Load Diff

4
bochs/cpu/fetchdecode_xop.h
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@ -24,7 +24,7 @@
#ifndef BX_XOP_FETCHDECODE_TABLES_H
#define BX_XOP_FETCHDECODE_TABLES_H
#if BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
#if BX_SUPPORT_AVX
/* ************************************************************************ */
@ -865,6 +865,6 @@ static const BxOpcodeInfo_t BxOpcodeTableXOP[256*3] = {
/* FF /0 */ { 0, BX_IA_ERROR }
};
#endif // BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
#endif // BX_SUPPORT_AVX
#endif // BX_XOP_FETCHDECODE_TABLES_H

14
bochs/cpu/ia_opcodes.h
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@ -2386,3 +2386,17 @@ bx_define_opcode(BX_IA_KSHIFTRW_KGwKEw, NULL, &BX_CPU_C::KSHIFTRW_KGwKEw, BX_ISA
bx_define_opcode(BX_IA_KXNORW_KGwKHwKEw, NULL, &BX_CPU_C::KXNORW_KGwKHwKEw, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_KMASK_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_KXORW_KGwKHwKEw, NULL, &BX_CPU_C::KXORW_KGwKHwKEw, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_KMASK_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
#endif
#if BX_SUPPORT_EVEX
// SSE alias
bx_define_opcode(BX_IA_V512_VADDPS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VADDPS_VpsHpsWpsR, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VADDPD_VpdHpdWpdR, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VADDSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_VssHpsWssR, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VADDSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_VsdHpdWsdR, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VADDPS_VpsHpsWps_MASK, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VADDPS_VpsHpsWpsR, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VADDPD_VpdHpdWpd_MASK, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VADDPD_VpdHpdWpdR, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VADDSS_VssHpsWss_MASK, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_VssHpsWssR, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VADDSD_VsdHpdWsd_MASK, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_VsdHpdWsdR, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_EVEX)
// SSE alias
#endif

27
bochs/cpu/instr.h
View File

@ -152,8 +152,8 @@ public:
// use Ib[3] as AVX mask register
// use Ib[2] as AVX attributes
// 7..4 (unused)
// 3..3 Broadcast/RC/SAE context (EVEX.B)
// 2..2 Zeroing/Merging mask (EVEX.Z)
// 3..3 Broadcast/RC/SAE control (EVEX.b)
// 2..2 Zeroing/Merging mask (EVEX.z)
// 1..0 Round control
// use Ib[1] as AVX VL
Bit8u Ib[4];
@ -343,6 +343,29 @@ public:
modRMForm.Ib[1] = value;
}
#if BX_SUPPORT_EVEX
BX_CPP_INLINE void setOpmask(unsigned reg) {
modRMForm.Ib[3] = reg;
}
BX_CPP_INLINE unsigned opmask(void) const {
return modRMForm.Ib[3];
}
BX_CPP_INLINE void setBroadcast(unsigned bit) {
modRMForm.Ib[2] = (modRMForm.Ib[2] & ~(1<<3)) | (bit<<3);
}
BX_CPP_INLINE unsigned getBroadcast(void) const {
return modRMForm.Ib[2] & (1 << 3);
}
BX_CPP_INLINE void setZeroMasking(unsigned bit) {
modRMForm.Ib[2] = (modRMForm.Ib[2] & ~(1<<2)) | (bit<<2);
}
BX_CPP_INLINE unsigned isZeroMasking(void) const {
return modRMForm.Ib[2] & (1 << 2);
}
#endif
BX_CPP_INLINE void setSrcReg(unsigned src, unsigned reg) {
metaData[src] = reg;
}

60
bochs/cpu/load.cc
View File

@ -158,3 +158,63 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Half_Vector(bxInstruction_c *
}
#endif
#if BX_SUPPORT_EVEX
#include "simd_int.h"
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_BROADCAST_VectorD(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit16u opmask = BX_READ_16BIT_OPMASK(i->opmask());
if (opmask == 0) {
BX_NEXT_INSTR(i);
}
unsigned vl = i->getVL();
if (i->getBroadcast()) {
Bit32u val_32 = read_virtual_dword(i->seg(), eaddr);
simd_pbroadcastd(BX_READ_AVX_REG(BX_VECTOR_TMP_REGISTER).vmm_u32ptr(), val_32, vl * 4);
}
else {
if (vl == BX_VL512)
read_virtual_zmmword(i->seg(), eaddr, &BX_READ_AVX_REG(BX_VECTOR_TMP_REGISTER));
if (vl == BX_VL256)
read_virtual_ymmword(i->seg(), eaddr, &BX_READ_YMM_REG(BX_VECTOR_TMP_REGISTER));
else
read_virtual_xmmword(i->seg(), eaddr, &BX_READ_XMM_REG(BX_VECTOR_TMP_REGISTER));
}
return BX_CPU_CALL_METHOD(i->execute2(), (i));
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_BROADCAST_VectorQ(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit16u opmask = BX_READ_8BIT_OPMASK(i->opmask());
if (opmask == 0) {
BX_NEXT_INSTR(i);
}
unsigned vl = i->getVL();
if (i->getBroadcast()) {
Bit64u val_64 = read_virtual_qword(i->seg(), eaddr);
simd_pbroadcastq(BX_READ_AVX_REG(BX_VECTOR_TMP_REGISTER).vmm_u64ptr(), val_64, vl * 2);
}
else {
if (vl == BX_VL512)
read_virtual_zmmword(i->seg(), eaddr, &BX_READ_AVX_REG(BX_VECTOR_TMP_REGISTER));
if (vl == BX_VL256)
read_virtual_ymmword(i->seg(), eaddr, &BX_READ_YMM_REG(BX_VECTOR_TMP_REGISTER));
else
read_virtual_xmmword(i->seg(), eaddr, &BX_READ_XMM_REG(BX_VECTOR_TMP_REGISTER));
}
return BX_CPU_CALL_METHOD(i->execute2(), (i));
}
#endif

24
bochs/cpu/simd_int.h
View File

@ -819,31 +819,31 @@ BX_CPP_INLINE void sse_pmaddwd(BxPackedXmmRegister *op1, const BxPackedXmmRegist
// broadcast
BX_CPP_INLINE void sse_pbroadcastb(BxPackedXmmRegister *op, Bit8u val_8)
BX_CPP_INLINE void simd_pbroadcastb(Bit8u *dst, Bit8u val_8, unsigned len)
{
for(unsigned n=0; n<16; n++) {
op->xmmubyte(n) = val_8;
for(unsigned n=0; n < len; n++) {
dst[n] = val_8;
}
}
BX_CPP_INLINE void sse_pbroadcastw(BxPackedXmmRegister *op, Bit16u val_16)
BX_CPP_INLINE void simd_pbroadcastw(Bit16u *dst, Bit16u val_16, unsigned len)
{
for(unsigned n=0; n<8; n++) {
op->xmm16u(n) = val_16;
for(unsigned n=0; n < len; n++) {
dst[n] = val_16;
}
}
BX_CPP_INLINE void sse_pbroadcastd(BxPackedXmmRegister *op, Bit32u val_32)
BX_CPP_INLINE void simd_pbroadcastd(Bit32u *dst, Bit32u val_32, unsigned len)
{
for(unsigned n=0; n<4; n++) {
op->xmm32u(n) = val_32;
for(unsigned n=0; n < len; n++) {
dst[n] = val_32;
}
}
BX_CPP_INLINE void sse_pbroadcastq(BxPackedXmmRegister *op, Bit64u val_64)
BX_CPP_INLINE void simd_pbroadcastq(Bit64u *dst, Bit64u val_64, unsigned len)
{
for(unsigned n=0; n<2; n++) {
op->xmm64u(n) = val_64;
for(unsigned n=0; n < len; n++) {
dst[n] = val_64;
}
}

2
bochs/cpu/sse_move.cc
View File

@ -549,7 +549,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVLPS_VpsMq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDDUP_VpdWqR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
sse_pbroadcastq(&BX_XMM_REG(i->dst()), BX_READ_XMM_REG_LO_QWORD(i->src()));
simd_pbroadcastq(BX_XMM_REG(i->dst()).xmm_u64ptr(), BX_READ_XMM_REG_LO_QWORD(i->src()), 2);
#endif
BX_NEXT_INSTR(i);

106
bochs/cpu/xmm.h
View File

@ -35,6 +35,16 @@ typedef union bx_xmm_reg_t {
Bit16u xmm_u16[8];
Bit32u xmm_u32[4];
Bit64u xmm_u64[2];
Bit8s* xmm_sbyteptr() { return &xmm_sbyte[0]; }
Bit16s* xmm_s16ptr() { return &xmm_s16[0]; }
Bit32s* xmm_s32ptr() { return &xmm_s32[0]; }
Bit64s* xmm_s64ptr() { return &xmm_s64[0]; }
Bit8u* xmm_ubyteptr() { return &xmm_ubyte[0]; }
Bit16u* xmm_u16ptr() { return &xmm_u16[0]; }
Bit32u* xmm_u32ptr() { return &xmm_u32[0]; }
Bit64u* xmm_u64ptr() { return &xmm_u64[0]; }
} BxPackedXmmRegister;
#ifdef BX_BIG_ENDIAN
@ -100,6 +110,15 @@ typedef union bx_ymm_reg_t {
Bit32u ymm_u32[8];
Bit64u ymm_u64[4];
BxPackedXmmRegister ymm_v128[2];
Bit8s* ymm_sbyteptr() { return &ymm_sbyte[0]; }
Bit16s* ymm_s16ptr() { return &ymm_s16[0]; }
Bit32s* ymm_s32ptr() { return &ymm_s32[0]; }
Bit64s* ymm_s64ptr() { return &ymm_s64[0]; }
Bit8u* ymm_ubyteptr() { return &ymm_ubyte[0]; }
Bit16u* ymm_u16ptr() { return &ymm_u16[0]; }
Bit32u* ymm_u32ptr() { return &ymm_u32[0]; }
Bit64u* ymm_u64ptr() { return &ymm_u64[0]; }
} BxPackedYmmRegister;
#ifdef BX_BIG_ENDIAN
@ -139,6 +158,15 @@ typedef union bx_zmm_reg_t {
Bit64u zmm_u64[8];
BxPackedXmmRegister zmm_v128[4];
BxPackedYmmRegister zmm_v256[2];
Bit8s* zmm_sbyteptr() { return &zmm_sbyte[0]; }
Bit16s* zmm_s16ptr() { return &zmm_s16[0]; }
Bit32s* zmm_s32ptr() { return &zmm_s32[0]; }
Bit64s* zmm_s64ptr() { return &zmm_s64[0]; }
Bit8u* zmm_ubyteptr() { return &zmm_ubyte[0]; }
Bit16u* zmm_u16ptr() { return &zmm_u16[0]; }
Bit32u* zmm_u32ptr() { return &zmm_u32[0]; }
Bit64u* zmm_u64ptr() { return &zmm_u64[0]; }
} BxPackedZmmRegister;
#ifdef BX_BIG_ENDIAN
@ -168,36 +196,60 @@ typedef union bx_zmm_reg_t {
#endif
#if BX_SUPPORT_EVEX
# define vmm64s(i) zmm64s(i)
# define vmm32s(i) zmm64s(i)
# define vmm16s(i) zmm16s(i)
# define vmmsbyte(i) zmmsbyte(i)
# define vmmubyte(i) zmmubyte(i)
# define vmm16u(i) zmm16u(i)
# define vmm32u(i) zmm32u(i)
# define vmm64u(i) zmm64u(i)
# define vmm128(i) zmm128(i)
# define vmm256(i) zmm256(i)
# define vmm64s(i) zmm64s(i)
# define vmm32s(i) zmm64s(i)
# define vmm16s(i) zmm16s(i)
# define vmmsbyte(i) zmmsbyte(i)
# define vmmubyte(i) zmmubyte(i)
# define vmm16u(i) zmm16u(i)
# define vmm32u(i) zmm32u(i)
# define vmm64u(i) zmm64u(i)
# define vmm128(i) zmm128(i)
# define vmm256(i) zmm256(i)
# define vmm_ubyteptr() zmm_ubyteptr()
# define vmm_sbyteptr() zmm_sbyteptr()
# define vmm_u16ptr() zmm_u16ptr()
# define vmm_s16ptr() zmm_s16ptr()
# define vmm_u32ptr() zmm_u32ptr()
# define vmm_s32ptr() zmm_s32ptr()
# define vmm_u64ptr() zmm_u64ptr()
# define vmm_s64ptr() zmm_s64ptr()
#else
# if BX_SUPPORT_AVX
# define vmm64s(i) ymm64s(i)
# define vmm32s(i) ymm64s(i)
# define vmm16s(i) ymm16s(i)
# define vmmsbyte(i) ymmsbyte(i)
# define vmmubyte(i) ymmubyte(i)
# define vmm16u(i) ymm16u(i)
# define vmm32u(i) ymm32u(i)
# define vmm64u(i) ymm64u(i)
# define vmm128(i) ymm128(i)
# define vmm64s(i) ymm64s(i)
# define vmm32s(i) ymm64s(i)
# define vmm16s(i) ymm16s(i)
# define vmmsbyte(i) ymmsbyte(i)
# define vmmubyte(i) ymmubyte(i)
# define vmm16u(i) ymm16u(i)
# define vmm32u(i) ymm32u(i)
# define vmm64u(i) ymm64u(i)
# define vmm128(i) ymm128(i)
# define vmm_ubyteptr() ymm_ubyteptr()
# define vmm_sbyteptr() ymm_sbyteptr()
# define vmm_u16ptr() ymm_u16ptr()
# define vmm_s16ptr() ymm_s16ptr()
# define vmm_u32ptr() ymm_u32ptr()
# define vmm_s32ptr() ymm_s32ptr()
# define vmm_u64ptr() ymm_u64ptr()
# define vmm_s64ptr() ymm_s64ptr()
# else
# define vmm64s(i) xmm64s(i)
# define vmm32s(i) xmm64s(i)
# define vmm16s(i) xmm16s(i)
# define vmmsbyte(i) xmmsbyte(i)
# define vmmubyte(i) xmmubyte(i)
# define vmm16u(i) xmm16u(i)
# define vmm32u(i) xmm32u(i)
# define vmm64u(i) xmm64u(i)
# define vmm64s(i) xmm64s(i)
# define vmm32s(i) xmm64s(i)
# define vmm16s(i) xmm16s(i)
# define vmmsbyte(i) xmmsbyte(i)
# define vmmubyte(i) xmmubyte(i)
# define vmm16u(i) xmm16u(i)
# define vmm32u(i) xmm32u(i)
# define vmm64u(i) xmm64u(i)
# define vmm_ubyteptr() xmm_ubyteptr()
# define vmm_sbyteptr() xmm_sbyteptr()
# define vmm_u16ptr() xmm_u16ptr()
# define vmm_s16ptr() xmm_s16ptr()
# define vmm_u32ptr() xmm_u32ptr()
# define vmm_s32ptr() xmm_s32ptr()
# define vmm_u64ptr() xmm_u64ptr()
# define vmm_s64ptr() xmm_s64ptr()
# endif
#endif