After a lot of thinking and browsing in the SVM arch forums I assume now that it shold be fine to enter to paged real mode under SVM guest.
The test case to consider:
(paged) real mode guest -> entering Pmode (not paged) -> disabling the Pmode back
Ths assumption still should be validated with real AMD hardware
Context: AMD's manual about CR0 intercept priority :
"Checks non-memory exceptions (CPL, illegal bit combinations, etc.) before the intercept"
The check for 'paged real mode' suposed to be illegal bit combination ...
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