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Add RDRAND/RDSEED instructions support (+ disasm)

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Of course no true random numbers will be generated - use standard "C" rand() function as stub.
In future it will be possible to improve (using another random generator) or even use real rdrand/rdseed intrinsics
This commit is contained in:
Stanislav Shwartsman 2012-10-09 15:16:48 +00:00
parent 1f7aa18003
commit 2638c1136a
15 changed files with 449 additions and 94 deletions
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9
bochs/cpu/Makefile.in
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@ -113,7 +113,8 @@ OBJS = \
bit32.o \
bmi32.o \
string.o \
paging.o
paging.o \
rdrand.o
# Objects which are only used for x86-64 code
OBJS64 = \
@ -749,3 +750,9 @@ xsave.o: xsave.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.
../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h descriptor.h \
instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h fpu/softfloat.h \
fpu/tag_w.h fpu/status_w.h fpu/control_w.h xmm.h stack.h
rdrand.o: rdrand.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
../config.h ../osdep.h ../gui/siminterface.h ../cpudb.h \
../gui/paramtree.h ../memory/memory.h ../pc_system.h ../gui/gui.h \
../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h descriptor.h \
instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h fpu/softfloat.h \
fpu/tag_w.h fpu/status_w.h fpu/control_w.h xmm.h stack.h

15
bochs/cpu/cpu.h
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@ -3218,6 +3218,19 @@ public: // for now...
BX_SMF BX_INSF_TYPE STAC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
// SMAP
// RDRAND/RDSEED
BX_SMF BX_INSF_TYPE RDRAND_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE RDRAND_Ed(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#if BX_SUPPORT_X86_64
BX_SMF BX_INSF_TYPE RDRAND_Eq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
BX_SMF BX_INSF_TYPE RDSEED_Ew(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE RDSEED_Ed(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#if BX_SUPPORT_X86_64
BX_SMF BX_INSF_TYPE RDSEED_Eq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
#if BX_SUPPORT_X86_64
// 64 bit extensions
BX_SMF BX_INSF_TYPE ADD_GqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -4900,7 +4913,7 @@ enum {
#define BxGroup6 BxGroupN
#define BxGroup7 BxFPEscape
#define BxGroup8 BxGroupN
#define BxGroup9 BxGroupN
#define BxGroup9 BxSplitGroupN
#define BxGroup11 BxGroupN
#define BxGroup12 BxGroupN

7
bochs/cpu/cpudb/corei7_ivy_bridge_3770K.cc
View File

@ -44,7 +44,7 @@ corei7_ivy_bridge_3770k_t::corei7_ivy_bridge_3770k_t(BX_CPU_C *cpu): bx_cpuid_t(
if (! BX_SUPPORT_MONITOR_MWAIT)
BX_INFO(("WARNING: MONITOR/MWAIT support is not compiled in !"));
BX_INFO(("WARNING: RDRAND is not implemented yet !"));
BX_INFO(("WARNING: RDRAND would not produce true random numbers !"));
}
void corei7_ivy_bridge_3770k_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const
@ -151,6 +151,7 @@ Bit64u corei7_ivy_bridge_3770k_t::get_isa_extensions_bitmask(void) const
BX_ISA_FSGSBASE |
BX_ISA_AVX |
BX_ISA_AVX_F16C |
BX_ISA_RDRAND |
BX_ISA_CMPXCHG16B |
BX_ISA_LM_LAHF_SAHF;
}
@ -327,8 +328,8 @@ void corei7_ivy_bridge_3770k_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf) con
BX_CPUID_EXT_AES |
BX_CPUID_EXT_XSAVE |
BX_CPUID_EXT_AVX |
BX_CPUID_EXT_AVX_F16C;
// BX_CPUID_EXT_RDRAND not implemented yet
BX_CPUID_EXT_AVX_F16C |
BX_CPUID_EXT_RDRAND;
if (cpu->cr4.get_OSXSAVE())
leaf->ecx |= BX_CPUID_EXT_OSXSAVE;

4
bochs/cpu/fetchdecode.cc
View File

@ -663,7 +663,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F C4 /w */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PINSRW_PqEwIb, BxOpcodeGroupSSE_0fc4 },
/* 0F C5 /w */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PEXTRW_GdPqIb, BxOpcodeGroupSSE_0fc5R },
/* 0F C6 /w */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_SHUFPS_VpsWpsIb, BxOpcodeGroupSSE_0fc6 },
/* 0F C7 /w */ { BxGroup9, BX_IA_ERROR, BxOpcodeInfoG9M },
/* 0F C7 /w */ { BxGroup9, BX_IA_ERROR, BxOpcodeInfoG9w },
/* 0F C8 /w */ { 0, BX_IA_BSWAP_RX },
/* 0F C9 /w */ { 0, BX_IA_BSWAP_RX },
/* 0F CA /w */ { 0, BX_IA_BSWAP_RX },
@ -1208,7 +1208,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F C4 /d */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PINSRW_PqEwIb, BxOpcodeGroupSSE_0fc4 },
/* 0F C5 /d */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PEXTRW_GdPqIb, BxOpcodeGroupSSE_0fc5R },
/* 0F C6 /d */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_SHUFPS_VpsWpsIb, BxOpcodeGroupSSE_0fc6 },
/* 0F C7 /d */ { BxGroup9, BX_IA_ERROR, BxOpcodeInfoG9M },
/* 0F C7 /d */ { BxGroup9, BX_IA_ERROR, BxOpcodeInfoG9d },
/* 0F C8 /d */ { 0, BX_IA_BSWAP_ERX },
/* 0F C9 /d */ { 0, BX_IA_BSWAP_ERX },
/* 0F CA /d */ { 0, BX_IA_BSWAP_ERX },

48
bochs/cpu/fetchdecode.h
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@ -641,7 +641,40 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G8EqIb[8] = {
/* Group 9 */
/* ******* */
static const BxOpcodeInfo_t BxOpcodeInfoG9M[8] = {
static const BxOpcodeInfo_t BxOpcodeInfoG9w[8*2] = {
/* /r form */
/* 0 */ { 0, BX_IA_ERROR },
/* 1 */ { 0, BX_IA_ERROR },
/* 2 */ { 0, BX_IA_ERROR },
/* 3 */ { 0, BX_IA_ERROR },
/* 4 */ { 0, BX_IA_ERROR },
/* 5 */ { 0, BX_IA_ERROR },
/* 6 */ { BxPrefixSSE, BX_IA_RDRAND_Ew, BxOpcodeGroupSSE_ERR },
/* 7 */ { BxPrefixSSE, BX_IA_RDSEED_Ew, BxOpcodeGroupSSE_ERR },
/* /m form */
/* 0 */ { 0, BX_IA_ERROR },
/* 1 */ { BxLockable, BX_IA_CMPXCHG8B },
/* 2 */ { 0, BX_IA_ERROR },
/* 3 */ { 0, BX_IA_ERROR },
/* 4 */ { 0, BX_IA_ERROR },
/* 5 */ { 0, BX_IA_ERROR },
/* 6 */ { BxPrefixSSE, BX_IA_VMPTRLD_Mq, BxOpcodeGroupSSE_G9VMX6 },
/* 7 */ { BxPrefixSSE, BX_IA_VMPTRST_Mq, BxOpcodeGroupSSE_ERR }
};
static const BxOpcodeInfo_t BxOpcodeInfoG9d[8*2] = {
/* /r form */
/* 0 */ { 0, BX_IA_ERROR },
/* 1 */ { 0, BX_IA_ERROR },
/* 2 */ { 0, BX_IA_ERROR },
/* 3 */ { 0, BX_IA_ERROR },
/* 4 */ { 0, BX_IA_ERROR },
/* 5 */ { 0, BX_IA_ERROR },
/* 6 */ { BxPrefixSSE, BX_IA_RDRAND_Ed, BxOpcodeGroupSSE_ERR },
/* 7 */ { BxPrefixSSE, BX_IA_RDSEED_Ed, BxOpcodeGroupSSE_ERR },
/* /m form */
/* 0 */ { 0, BX_IA_ERROR },
/* 1 */ { BxLockable, BX_IA_CMPXCHG8B },
/* 2 */ { 0, BX_IA_ERROR },
@ -653,7 +686,18 @@ static const BxOpcodeInfo_t BxOpcodeInfoG9M[8] = {
};
#if BX_SUPPORT_X86_64
static const BxOpcodeInfo_t BxOpcodeInfo64G9qM[8] = {
static const BxOpcodeInfo_t BxOpcodeInfo64G9q[8*2] = {
/* /r form */
/* 0 */ { 0, BX_IA_ERROR },
/* 1 */ { 0, BX_IA_ERROR },
/* 2 */ { 0, BX_IA_ERROR },
/* 3 */ { 0, BX_IA_ERROR },
/* 4 */ { 0, BX_IA_ERROR },
/* 5 */ { 0, BX_IA_ERROR },
/* 6 */ { BxPrefixSSE, BX_IA_RDRAND_Eq, BxOpcodeGroupSSE_ERR },
/* 7 */ { BxPrefixSSE, BX_IA_RDSEED_Eq, BxOpcodeGroupSSE_ERR },
/* /m form */
/* 0 */ { 0, BX_IA_ERROR },
/* 1 */ { BxLockable, BX_IA_CMPXCHG16B },
/* 2 */ { 0, BX_IA_ERROR },

6
bochs/cpu/fetchdecode64.cc
View File

@ -595,7 +595,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F C4 /w */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PINSRW_PqEwIb, BxOpcodeGroupSSE_0fc4 },
/* 0F C5 /w */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PEXTRW_GdPqIb, BxOpcodeGroupSSE_0fc5R },
/* 0F C6 /w */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_SHUFPS_VpsWpsIb, BxOpcodeGroupSSE_0fc6 },
/* 0F C7 /w */ { BxGroup9, BX_IA_ERROR, BxOpcodeInfoG9M },
/* 0F C7 /w */ { BxGroup9, BX_IA_ERROR, BxOpcodeInfoG9w },
/* 0F C8 /w */ { 0, BX_IA_BSWAP_RX },
/* 0F C9 /w */ { 0, BX_IA_BSWAP_RX },
/* 0F CA /w */ { 0, BX_IA_BSWAP_RX },
@ -1110,7 +1110,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F C4 /d */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PINSRW_PqEwIb, BxOpcodeGroupSSE_0fc4 },
/* 0F C5 /d */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PEXTRW_GdPqIb, BxOpcodeGroupSSE_0fc5R },
/* 0F C6 /d */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_SHUFPS_VpsWpsIb, BxOpcodeGroupSSE_0fc6 },
/* 0F C7 /d */ { BxGroup9, BX_IA_ERROR, BxOpcodeInfoG9M },
/* 0F C7 /d */ { BxGroup9, BX_IA_ERROR, BxOpcodeInfoG9d },
/* 0F C8 /d */ { 0, BX_IA_BSWAP_ERX },
/* 0F C9 /d */ { 0, BX_IA_BSWAP_ERX },
/* 0F CA /d */ { 0, BX_IA_BSWAP_ERX },
@ -1625,7 +1625,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F C4 /q */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PINSRW_PqEwIb, BxOpcodeGroupSSE_0fc4 },
/* 0F C5 /q */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PEXTRW_GdPqIb, BxOpcodeGroupSSE_0fc5R },
/* 0F C6 /q */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_SHUFPS_VpsWpsIb, BxOpcodeGroupSSE_0fc6 },
/* 0F C7 /q */ { BxGroup9, BX_IA_ERROR, BxOpcodeInfo64G9qM },
/* 0F C7 /q */ { BxGroup9, BX_IA_ERROR, BxOpcodeInfo64G9q },
/* 0F C8 /q */ { 0, BX_IA_BSWAP_RRX },
/* 0F C9 /q */ { 0, BX_IA_BSWAP_RRX },
/* 0F CA /q */ { 0, BX_IA_BSWAP_RRX },

14
bochs/cpu/ia_opcodes.h
View File

@ -2222,3 +2222,17 @@ bx_define_opcode(BX_IA_ADOX_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::ADOX_GqEqR, BX_
// SMAP
bx_define_opcode(BX_IA_STAC, NULL, &BX_CPU_C::STAC, BX_ISA_SMAP, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0)
bx_define_opcode(BX_IA_CLAC, NULL, &BX_CPU_C::STAC, BX_ISA_SMAP, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0)
// RDRAND
bx_define_opcode(BX_IA_RDRAND_Ew, NULL, &BX_CPU_C::RDRAND_Ew, BX_ISA_RDRAND, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0)
bx_define_opcode(BX_IA_RDRAND_Ed, NULL, &BX_CPU_C::RDRAND_Ew, BX_ISA_RDRAND, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0)
#if BX_SUPPORT_X86_64
bx_define_opcode(BX_IA_RDRAND_Eq, NULL, &BX_CPU_C::RDRAND_Ew, BX_ISA_RDRAND, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0)
#endif
// RDSEED
bx_define_opcode(BX_IA_RDSEED_Ew, NULL, &BX_CPU_C::RDSEED_Ew, BX_ISA_RDSEED, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0)
bx_define_opcode(BX_IA_RDSEED_Ed, NULL, &BX_CPU_C::RDSEED_Ew, BX_ISA_RDSEED, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0)
#if BX_SUPPORT_X86_64
bx_define_opcode(BX_IA_RDSEED_Eq, NULL, &BX_CPU_C::RDSEED_Ew, BX_ISA_RDSEED, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0)
#endif

234
bochs/cpu/rdrand.cc Normal file
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@ -0,0 +1,234 @@
/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
//
/////////////////////////////////////////////////////////////////////////
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
#include <stdlib.h>
#define HW_RANDOM_GENERATOR_READY (1)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDRAND_Ew(bxInstruction_c *i)
{
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest) {
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_RDRAND_VMEXIT)) {
VMexit(VMX_VMEXIT_RDRAND, 0);
}
}
#endif
Bit16u val_16 = 0;
if (HW_RANDOM_GENERATOR_READY) {
val_16 |= rand() & 0xff; // hack using std C rand() function
val_16 <<= 8;
val_16 |= rand() & 0xff;
setEFlagsOSZAPC(EFlagsCFMask);
}
else {
setEFlagsOSZAPC(0);
}
BX_WRITE_16BIT_REG(i->dst(), val_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDRAND_Ed(bxInstruction_c *i)
{
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest) {
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_RDRAND_VMEXIT)) {
VMexit(VMX_VMEXIT_RDRAND, 0);
}
}
#endif
Bit32u val_32 = 0;
if (HW_RANDOM_GENERATOR_READY) {
val_32 |= rand() & 0xff; // hack using std C rand() function
val_32 <<= 8;
val_32 |= rand() & 0xff;
val_32 <<= 8;
val_32 |= rand() & 0xff;
val_32 <<= 8;
val_32 |= rand() & 0xff;
setEFlagsOSZAPC(EFlagsCFMask);
}
else {
setEFlagsOSZAPC(0);
}
BX_WRITE_32BIT_REGZ(i->dst(), val_32);
BX_NEXT_INSTR(i);
}
#if BX_SUPPORT_X86_64
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDRAND_Eq(bxInstruction_c *i)
{
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest) {
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_RDRAND_VMEXIT)) {
VMexit(VMX_VMEXIT_RDRAND, 0);
}
}
#endif
Bit64u val_64 = 0;
if (HW_RANDOM_GENERATOR_READY) {
val_64 |= rand() & 0xff; // hack using std C rand() function
val_64 <<= 8;
val_64 |= rand() & 0xff;
val_64 <<= 8;
val_64 |= rand() & 0xff;
val_64 <<= 8;
val_64 |= rand() & 0xff;
val_64 <<= 8;
val_64 |= rand() & 0xff;
val_64 <<= 8;
val_64 |= rand() & 0xff;
val_64 <<= 8;
val_64 |= rand() & 0xff;
val_64 <<= 8;
val_64 |= rand() & 0xff;
setEFlagsOSZAPC(EFlagsCFMask);
}
else {
setEFlagsOSZAPC(0);
}
BX_WRITE_64BIT_REG(i->dst(), val_64);
BX_NEXT_INSTR(i);
}
#endif
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDSEED_Ew(bxInstruction_c *i)
{
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest) {
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_RDSEED_VMEXIT)) {
VMexit(VMX_VMEXIT_RDSEED, 0);
}
}
#endif
Bit16u val_16 = 0;
if (HW_RANDOM_GENERATOR_READY) {
val_16 |= rand() & 0xff; // hack using std C rand() function
val_16 <<= 8;
val_16 |= rand() & 0xff;
setEFlagsOSZAPC(EFlagsCFMask);
}
else {
setEFlagsOSZAPC(0);
}
BX_WRITE_16BIT_REG(i->dst(), val_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDSEED_Ed(bxInstruction_c *i)
{
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest) {
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_RDSEED_VMEXIT)) {
VMexit(VMX_VMEXIT_RDSEED, 0);
}
}
#endif
Bit32u val_32 = 0;
if (HW_RANDOM_GENERATOR_READY) {
val_32 |= rand() & 0xff; // hack using std C rand() function
val_32 <<= 8;
val_32 |= rand() & 0xff;
val_32 <<= 8;
val_32 |= rand() & 0xff;
val_32 <<= 8;
val_32 |= rand() & 0xff;
setEFlagsOSZAPC(EFlagsCFMask);
}
else {
setEFlagsOSZAPC(0);
}
BX_WRITE_32BIT_REGZ(i->dst(), val_32);
BX_NEXT_INSTR(i);
}
#if BX_SUPPORT_X86_64
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDSEED_Eq(bxInstruction_c *i)
{
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest) {
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_RDSEED_VMEXIT)) {
VMexit(VMX_VMEXIT_RDSEED, 0);
}
}
#endif
Bit64u val_64 = 0;
if (HW_RANDOM_GENERATOR_READY) {
val_64 |= rand() & 0xff; // hack using std C rand() function
val_64 <<= 8;
val_64 |= rand() & 0xff;
val_64 <<= 8;
val_64 |= rand() & 0xff;
val_64 <<= 8;
val_64 |= rand() & 0xff;
val_64 <<= 8;
val_64 |= rand() & 0xff;
val_64 <<= 8;
val_64 |= rand() & 0xff;
val_64 <<= 8;
val_64 |= rand() & 0xff;
val_64 <<= 8;
val_64 |= rand() & 0xff;
setEFlagsOSZAPC(EFlagsCFMask);
}
else {
setEFlagsOSZAPC(0);
}
BX_WRITE_64BIT_REG(i->dst(), val_64);
BX_NEXT_INSTR(i);
}
#endif

6
bochs/cpu/vmcs.cc
View File

@ -487,6 +487,8 @@ void BX_CPU_C::init_vmx_capabilities(void)
// [11] RDRAND Exiting (require RDRAND instruction support)
// [12] Enable INVPCID instruction (require INVPCID instruction support)
// [13] Enable VM Functions
// ...
// [16] RDSEED Exiting (require RDSEED instruction support)
cap->vmx_vmexec_ctrl2_supported_bits = 0;
@ -518,6 +520,10 @@ void BX_CPU_C::init_vmx_capabilities(void)
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_INVPCID))
cap->vmx_vmexec_ctrl2_supported_bits |= VMX_VM_EXEC_CTRL3_INVPCID;
#endif
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_RDRAND))
cap->vmx_vmexec_ctrl2_supported_bits |= VMX_VM_EXEC_CTRL3_RDRAND_VMEXIT;
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_RDSEED))
cap->vmx_vmexec_ctrl2_supported_bits |= VMX_VM_EXEC_CTRL3_RDSEED_VMEXIT;
// enable secondary vm exec controls if needed
if (cap->vmx_vmexec_ctrl2_supported_bits != 0)

10
bochs/disasm/dis_decode.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Copyright (c) 2005-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -270,6 +270,14 @@ x86_insn disassembler::decode(bx_bool is_32, bx_bool is_64, bx_address base, bx_
attr = 0;
continue;
case _GRPSSENONE:
/* SSE opcode group with no prefix only allowed */
sse_opcode = 1;
if (sse_prefix != SSE_PREFIX_NONE)
entry = &(BxDisasmGroupSSE_ERR[sse_prefix]);
attr = 0;
continue;
case _GRPSSE:
sse_opcode = 1;
/* For SSE opcodes, look into another 4 entries table

18
bochs/disasm/dis_tables.h
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Copyright (c) 2005-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -31,10 +31,11 @@
#define _GRPSSE66 6
#define _GRPSSEF2 7
#define _GRPSSEF3 8
#define _GRPRM 9
#define _GRP3BOP 10
#define _GRP64B 11
#define _GRPVEXW 12
#define _GRPSSENONE 9
#define _GRPRM 10
#define _GRP3BOP 11
#define _GRP64B 12
#define _GRPVEXW 13
/* ************************************************************************ */
#define GRPSSE(n) _GRPSSE, BxDisasmGroupSSE_##n
@ -50,9 +51,10 @@
/* ************************************************************************ */
/* ************************************************************************ */
#define GRPSSE66(n) _GRPSSE66, &n
#define GRPSSEF2(n) _GRPSSEF2, &n
#define GRPSSEF3(n) _GRPSSEF3, &n
#define GRPSSE66(n) _GRPSSE66, &n
#define GRPSSEF2(n) _GRPSSEF2, &n
#define GRPSSEF3(n) _GRPSSEF3, &n
#define GRPSSENONE(n) _GRPSSENONE, &n
/* ************************************************************************ */
#define Apw &disassembler::Apw

144
bochs/disasm/dis_tables.inc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Copyright (c) 2005-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -386,26 +386,18 @@ static BxDisasmOpcodeTable_t BxDisasmGroupRmINVLPG[8] = {
/* VMX */
static BxDisasmOpcodeTable_t BxDisasmGroupRmG7VMX[8] = {
/* 0 */ { 0, &Ia_Invalid },
/* 1 */ { 0, &Ia_vmcall },
/* 2 */ { 0, &Ia_vmlaunch },
/* 3 */ { 0, &Ia_vmresume },
/* 4 */ { 0, &Ia_vmxoff },
/* 1 */ { GRPSSENONE(Ia_vmcall) },
/* 2 */ { GRPSSENONE(Ia_vmlaunch) },
/* 3 */ { GRPSSENONE(Ia_vmresume) },
/* 4 */ { GRPSSENONE(Ia_vmxoff) },
/* 5 */ { 0, &Ia_Invalid },
/* 6 */ { 0, &Ia_Invalid },
/* 7 */ { 0, &Ia_Invalid }
};
/* VMX */
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G7VMX[4] = {
/* -- */ { GRPRM(G7VMX) },
/* 66 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupRmMONITOR[8] = {
/* 0 */ { 0, &Ia_monitor },
/* 1 */ { 0, &Ia_mwait },
/* 0 */ { GRPSSENONE(Ia_monitor) },
/* 1 */ { GRPSSENONE(Ia_mwait) },
/* 2 */ { 0, &Ia_clac },
/* 3 */ { 0, &Ia_stac },
/* 4 */ { 0, &Ia_Invalid },
@ -415,11 +407,11 @@ static BxDisasmOpcodeTable_t BxDisasmGroupRmMONITOR[8] = {
};
static BxDisasmOpcodeTable_t BxDisasmGroupRmXSETGET[8] = {
/* 0 */ { 0, &Ia_xgetbv },
/* 1 */ { 0, &Ia_xsetbv },
/* 0 */ { GRPSSENONE(Ia_xgetbv) },
/* 1 */ { GRPSSENONE(Ia_xsetbv) },
/* 2 */ { 0, &Ia_Invalid },
/* 3 */ { 0, &Ia_Invalid },
/* 4 */ { 0, &Ia_vmfunc }, // VMX
/* 4 */ { GRPSSENONE(Ia_vmfunc) },
/* 5 */ { 0, &Ia_Invalid },
/* 6 */ { 0, &Ia_Invalid },
/* 7 */ { 0, &Ia_Invalid }
@ -437,7 +429,7 @@ static BxDisasmOpcodeTable_t BxDisasmGroupRmG7SVM[8] = {
};
static BxDisasmOpcodeTable_t BxDisasmGroupG7R[8] = {
/* 0 */ { GRPSSE(G7VMX) }, // VMX
/* 0 */ { GRPRM(G7VMX) }, // VMX
/* 1 */ { GRPRM(MONITOR) },
/* 2 */ { GRPRM(XSETGET) },
/* 3 */ { GRPRM(G7SVM) }, // SVM
@ -486,7 +478,9 @@ static BxDisasmOpcodeTable_t BxDisasmGroupG8EqIb[8] = {
/* 7 */ { 0, &Ia_btcq_Eq_Ib }
};
/* ****** */
/* Group9 */
/* ****** */
/* VMX */
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G9VMX6[4] = {
@ -496,36 +490,76 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G9VMX6[4] = {
/* F2 */ { 0, &Ia_Invalid }
};
/* VMX */
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G9VMX7[4] = {
/* -- */ { 0, &Ia_vmptrst_Mq },
/* 66 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG9[8] = {
static BxDisasmOpcodeTable_t BxDisasmGroupG9M[8] = {
/* 0 */ { 0, &Ia_Invalid },
/* 1 */ { 0, &Ia_cmpxchg8b_Mq },
/* 2 */ { 0, &Ia_Invalid },
/* 3 */ { 0, &Ia_Invalid },
/* 4 */ { 0, &Ia_Invalid },
/* 5 */ { 0, &Ia_Invalid },
/* 6 */ { GRPSSE(G9VMX6) }, // VMX
/* 7 */ { GRPSSE(G9VMX7) } // VMX
/* 6 */ { GRPSSE(G9VMX6) },
/* 7 */ { GRPSSENONE(Ia_vmptrst_Mq) }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG9q[8] = {
static BxDisasmOpcodeTable_t BxDisasmGroupG9Mq[8] = {
/* 0 */ { 0, &Ia_Invalid },
/* 1 */ { 0, &Ia_cmpxchg16b_Mdq },
/* 2 */ { 0, &Ia_Invalid },
/* 3 */ { 0, &Ia_Invalid },
/* 4 */ { 0, &Ia_Invalid },
/* 5 */ { 0, &Ia_Invalid },
/* 6 */ { GRPSSE(G9VMX6) }, // VMX
/* 7 */ { GRPSSE(G9VMX7) } // VMX
/* 6 */ { GRPSSE(G9VMX6) },
/* 7 */ { GRPSSENONE(Ia_vmptrst_Mq) }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG9Rw[8] = {
/* 0 */ { 0, &Ia_Invalid },
/* 1 */ { 0, &Ia_Invalid },
/* 2 */ { 0, &Ia_Invalid },
/* 3 */ { 0, &Ia_Invalid },
/* 4 */ { 0, &Ia_Invalid },
/* 5 */ { 0, &Ia_Invalid },
/* 6 */ { GRPSSENONE(Ia_rdrand_Ew) },
/* 7 */ { GRPSSENONE(Ia_rdseed_Ew) }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG9Rd[8] = {
/* 0 */ { 0, &Ia_Invalid },
/* 1 */ { 0, &Ia_Invalid },
/* 2 */ { 0, &Ia_Invalid },
/* 3 */ { 0, &Ia_Invalid },
/* 4 */ { 0, &Ia_Invalid },
/* 5 */ { 0, &Ia_Invalid },
/* 6 */ { GRPSSENONE(Ia_rdrand_Ed) },
/* 7 */ { GRPSSENONE(Ia_rdseed_Ed) }
};
static BxDisasmOpcodeTable_t BxDisasmGroupG9Rq[8] = {
/* 0 */ { 0, &Ia_Invalid },
/* 1 */ { 0, &Ia_Invalid },
/* 2 */ { 0, &Ia_Invalid },
/* 3 */ { 0, &Ia_Invalid },
/* 4 */ { 0, &Ia_Invalid },
/* 5 */ { 0, &Ia_Invalid },
/* 6 */ { GRPSSENONE(Ia_rdrand_Eq) },
/* 7 */ { GRPSSENONE(Ia_rdseed_Eq) }
};
static BxDisasmOpcodeTable_t BxDisasmGroupModG9w[2] = {
/* R */ { GRPN(G9Rw) },
/* M */ { GRPN(G9M) }
};
static BxDisasmOpcodeTable_t BxDisasmGroupModG9d[2] = {
/* R */ { GRPN(G9Rd) },
/* M */ { GRPN(G9M) }
};
static BxDisasmOpcodeTable_t BxDisasmGroupModG9q[2] = {
/* R */ { GRPN(G9Rq) },
/* M */ { GRPN(G9Mq) }
};
/* Group11 */
static BxDisasmOpcodeTable_t BxDisasmGroupG11Eb[8] = {
/* 0 */ { 0, &Ia_movb_Eb_Ib },
@ -1106,11 +1140,11 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes16[256*2] = {
/* 0F C0 */ { 0, &Ia_xaddb_Eb_Gb },
/* 0F C0 */ { 0, &Ia_xaddw_Ew_Gw },
/* 0F C2 */ { GRPSSE(0fc2) },
/* 0F C3 */ { GRPSSE(0fc3) },
/* 0F C3 */ { GRPSSENONE(Ia_movnti_Md_Gd) },
/* 0F C4 */ { GRPSSE(0fc4) },
/* 0F C5 */ { GRPSSE(0fc5) },
/* 0F C6 */ { GRPSSE(0fc6) },
/* 0F C7 */ { GRPN(G9) },
/* 0F C7 */ { GRPMOD(G9w) },
/* 0F C8 */ { 0, &Ia_bswapl_ERX },
/* 0F C9 */ { 0, &Ia_bswapl_ERX },
/* 0F CA */ { 0, &Ia_bswapl_ERX },
@ -1626,12 +1660,12 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes32[256*2] = {
/* 0F BF */ { 0, &Ia_movswl_Gd_Ew },
/* 0F C0 */ { 0, &Ia_xaddb_Eb_Gb },
/* 0F C0 */ { 0, &Ia_xaddl_Ed_Gd },
/* 0F C2 */ { GRPSSE(0fc2) },
/* 0F C3 */ { GRPSSE(0fc3) },
/* 0F C4 */ { GRPSSE(0fc4) },
/* 0F C5 */ { GRPSSE(0fc5) },
/* 0F C6 */ { GRPSSE(0fc6) },
/* 0F C7 */ { GRPN(G9) },
/* 0F C2 */ { GRPSSE(0fc2) },
/* 0F C3 */ { GRPSSENONE(Ia_movnti_Md_Gd) },
/* 0F C4 */ { GRPSSE(0fc4) },
/* 0F C5 */ { GRPSSE(0fc5) },
/* 0F C6 */ { GRPSSE(0fc6) },
/* 0F C7 */ { GRPMOD(G9d) },
/* 0F C8 */ { 0, &Ia_bswapl_ERX },
/* 0F C9 */ { 0, &Ia_bswapl_ERX },
/* 0F CA */ { 0, &Ia_bswapl_ERX },
@ -2148,11 +2182,11 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes64w[256*2] = {
/* 0F C0 */ { 0, &Ia_xaddb_Eb_Gb },
/* 0F C0 */ { 0, &Ia_xaddw_Ew_Gw },
/* 0F C2 */ { GRPSSE(0fc2) },
/* 0F C3 */ { GRPSSE(0fc3) },
/* 0F C3 */ { GRPSSENONE(Ia_movnti_Md_Gd) },
/* 0F C4 */ { GRPSSE(0fc4) },
/* 0F C5 */ { GRPSSE(0fc5) },
/* 0F C6 */ { GRPSSE(0fc6) },
/* 0F C7 */ { GRPN(G9) },
/* 0F C7 */ { GRPMOD(G9w) },
/* 0F C8 */ { 0, &Ia_bswapl_ERX },
/* 0F C9 */ { 0, &Ia_bswapl_ERX },
/* 0F CA */ { 0, &Ia_bswapl_ERX },
@ -2665,12 +2699,12 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes64d[256*2] = {
/* 0F BF */ { 0, &Ia_movswl_Gd_Ew },
/* 0F C0 */ { 0, &Ia_xaddb_Eb_Gb },
/* 0F C0 */ { 0, &Ia_xaddl_Ed_Gd },
/* 0F C2 */ { GRPSSE(0fc2) },
/* 0F C3 */ { GRPSSE(0fc3) },
/* 0F C4 */ { GRPSSE(0fc4) },
/* 0F C5 */ { GRPSSE(0fc5) },
/* 0F C6 */ { GRPSSE(0fc6) },
/* 0F C7 */ { GRPN(G9) },
/* 0F C2 */ { GRPSSE(0fc2) },
/* 0F C3 */ { GRPSSENONE(Ia_movnti_Md_Gd) },
/* 0F C4 */ { GRPSSE(0fc4) },
/* 0F C5 */ { GRPSSE(0fc5) },
/* 0F C6 */ { GRPSSE(0fc6) },
/* 0F C7 */ { GRPMOD(G9d) },
/* 0F C8 */ { 0, &Ia_bswapl_ERX },
/* 0F C9 */ { 0, &Ia_bswapl_ERX },
/* 0F CA */ { 0, &Ia_bswapl_ERX },
@ -3183,12 +3217,12 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes64q[256*2] = {
/* 0F BF */ { 0, &Ia_movswq_Gq_Ew },
/* 0F C0 */ { 0, &Ia_xaddb_Eb_Gb },
/* 0F C0 */ { 0, &Ia_xaddq_Eq_Gq },
/* 0F C2 */ { GRPSSE(0fc2) },
/* 0F C3 */ { GRPSSE(0fc3Q) },
/* 0F C4 */ { GRPSSE(0fc4) },
/* 0F C5 */ { GRPSSE(0fc5) },
/* 0F C6 */ { GRPSSE(0fc6) },
/* 0F C7 */ { GRPN(G9q) },
/* 0F C2 */ { GRPSSE(0fc2) },
/* 0F C3 */ { GRPSSENONE(Ia_movntiq_Mq_Gq) },
/* 0F C4 */ { GRPSSE(0fc4) },
/* 0F C5 */ { GRPSSE(0fc5) },
/* 0F C6 */ { GRPSSE(0fc6) },
/* 0F C7 */ { GRPMOD(G9q) },
/* 0F C8 */ { 0, &Ia_bswapq_RRX },
/* 0F C9 */ { 0, &Ia_bswapq_RRX },
/* 0F CA */ { 0, &Ia_bswapq_RRX },

16
bochs/disasm/dis_tables_sse.inc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Copyright (c) 2005-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -479,20 +479,6 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0fc2[4] = {
/* F2 */ { 0, &Ia_cmpsd_Vsd_Wsd_Ib }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0fc3[4] = {
/* -- */ { 0, &Ia_movnti_Md_Gd },
/* 66 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0fc3Q[4] = {
/* -- */ { 0, &Ia_movntiq_Mq_Gq },
/* 66 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0fc4[4] = {
/* -- */ { 0, &Ia_pinsrw_Pq_Ew_Ib },
/* 66 */ { 0, &Ia_pinsrw_Vdq_Ew_Ib },

2
bochs/disasm/disasm.h
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Copyright (c) 2005-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or

10
bochs/disasm/opcodes.inc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Copyright (c) 2005-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -1134,6 +1134,12 @@ Ia_rdfsbase_Ry = { "rdfsbase", "rdfsbase", Ry, XX, XX, XX, IA_FSGSBASE },
Ia_rdgsbase_Ry = { "rdgsbase", "rdgsbase", Ry, XX, XX, XX, IA_FSGSBASE },
Ia_rdmsr = { "rdmsr", "rdmsr", XX, XX, XX, XX, IA_PENTIUM },
Ia_rdpmc = { "rdpmc", "rdpmc", XX, XX, XX, XX, IA_P6 },
Ia_rdrand_Ed = { "rdrand", "rdrandd", Ed, XX, XX, XX, IA_RDRAND },
Ia_rdrand_Eq = { "rdrand", "rdrandq", Eq, XX, XX, XX, IA_RDRAND },
Ia_rdrand_Ew = { "rdrand", "rdrandw", Ew, XX, XX, XX, IA_RDRAND },
Ia_rdseed_Ed = { "rdseed", "rdseedd", Ed, XX, XX, XX, IA_RDSEED },
Ia_rdseed_Eq = { "rdseed", "rdseedq", Eq, XX, XX, XX, IA_RDSEED },
Ia_rdseed_Ew = { "rdseed", "rdseedw", Ew, XX, XX, XX, IA_RDSEED },
Ia_rdtsc = { "rdtsc", "rdtsc", XX, XX, XX, XX, IA_PENTIUM },
Ia_rdtscp = { "rdtscp", "rdtscp", XX, XX, XX, XX, IA_RDTSCP },
Ia_ret = { "ret", "ret", XX, XX, XX, XX, 0 },
@ -1844,7 +1850,7 @@ Ia_vunpcklpd_Vpd_Hpd_Wpd = { "vunpcklpd", "vunpcklpd", Vpd, Hpd, Wpd, XX, IA_AVX
Ia_vunpcklps_Vps_Hps_Wps = { "vunpcklps", "vunpcklps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vxorpd_Vpd_Hpd_Wpd = { "vxorpd", "vxorpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vxorps_Vps_Hps_Wps = { "vxorps", "vxorps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vzerall = { "vzeroall", "vzeroall", XX, XX, XX, XX, IA_AVX },
Ia_vzeroall = { "vzeroall", "vzeroall", XX, XX, XX, XX, IA_AVX },
Ia_vzeroupper = { "vzeroupper", "vzeroupper", XX, XX, XX, XX, IA_AVX },
Ia_wbinvd = { "wbinvd", "wbinvd", XX, XX, XX, XX, IA_486 },
Ia_wrfsbase_Ry = { "wrfsbase", "wrfsbase", Ry, XX, XX, XX, IA_FSGSBASE },