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Suppress 'entering paged real mode' CR0 check for SVM guest

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After a lot of thinking and browsing in the SVM arch forums I assume now that it shold be fine to enter to paged real mode under SVM guest.
The test case to consider:

  (paged) real mode guest -> entering Pmode (not paged) -> disabling the Pmode back

Ths assumption still should be validated with real AMD hardware

Context: AMD's manual about CR0 intercept priority :
	"Checks non-memory exceptions (CPL, illegal bit combinations, etc.) before the intercept"

The check for 'paged real mode' suposed to be illegal bit combination ...
This commit is contained in:
Stanislav Shwartsman 2013-02-27 19:11:28 +00:00
parent b81622cf31
commit 39ae66b5a3
1 changed files with 8 additions and 3 deletions
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11
bochs/cpu/crregs.cc
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@ -970,9 +970,14 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::check_CR0(bx_address cr0_val)
temp_cr0.set32((Bit32u) cr0_val);
if (temp_cr0.get_PG() && !temp_cr0.get_PE()) {
BX_ERROR(("check_CR0(0x%08x): attempt to set CR0.PG with CR0.PE cleared !", temp_cr0.get32()));
return 0;
#if BX_SUPPORT_SVM
if (! BX_CPU_THIS_PTR in_svm_guest) // it should be fine to enter paged real mode in SVM guest
#endif
{
if (temp_cr0.get_PG() && !temp_cr0.get_PE()) {
BX_ERROR(("check_CR0(0x%08x): attempt to set CR0.PG with CR0.PE cleared !", temp_cr0.get32()));
return 0;
}
}
#if BX_CPU_LEVEL >= 4