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fixed small avx issues

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This commit is contained in:
Stanislav Shwartsman 2012-12-11 21:01:05 +00:00
parent 318ad5e26d
commit db4d75317a
3 changed files with 10 additions and 9 deletions
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12
bochs/cpu/avx.cc
View File

@ -598,7 +598,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_VpsHpsMps(bxInstruction
for (int n=4*len-1; n >= 0; n--) {
if (mask.avx32u(n) & 0x80000000)
result.avx32u(n) = read_virtual_dword(i->seg(), (eaddr + 4*n) & i->asize_mask());
result.avx32u(n) = read_virtual_dword(i->seg(), eaddr + 4*n);
else
result.avx32u(n) = 0;
}
@ -638,7 +638,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_VpdHpdMpd(bxInstruction
for (int n=2*len-1; n >= 0; n--) {
if (mask.avx32u(n*2+1) & 0x80000000)
result.avx64u(n) = read_virtual_qword(i->seg(), (eaddr + 8*n) & i->asize_mask());
result.avx64u(n) = read_virtual_qword(i->seg(), eaddr + 8*n);
else
result.avx64u(n) = 0;
}
@ -679,12 +679,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_MpsHpsVps(bxInstruction
// see you can successfully write all the elements first
for (int n=4*len-1; n >= 0; n--) {
if (mask.avx32u(n) & 0x80000000)
read_RMW_virtual_dword(i->seg(), (eaddr + 4*n) & i->asize_mask());
read_RMW_virtual_dword(i->seg(), eaddr + 4*n);
}
for (unsigned n=0; n < (4*len); n++) {
if (mask.avx32u(n) & 0x80000000)
write_virtual_dword(i->seg(), (eaddr + 4*n) & i->asize_mask(), op.avx32u(n));
write_virtual_dword(i->seg(), eaddr + 4*n, op.avx32u(n));
}
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
@ -721,12 +721,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_MpdHpdVpd(bxInstruction
// see you can successfully write all the elements first
for (int n=2*len-1; n >= 0; n--) {
if (mask.avx32u(2*n+1) & 0x80000000)
read_RMW_virtual_qword(i->seg(), (eaddr + 8*n) & i->asize_mask());
read_RMW_virtual_qword(i->seg(), eaddr + 8*n);
}
for (unsigned n=0; n < (2*len); n++) {
if (mask.avx32u(2*n+1) & 0x80000000)
write_virtual_qword(i->seg(), (eaddr + 8*n) & i->asize_mask(), op.avx64u(n));
write_virtual_qword(i->seg(), eaddr + 8*n, op.avx64u(n));
}
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK

4
bochs/cpu/fetchdecode_avx.h
View File

@ -391,13 +391,13 @@ static const BxOpcodeInfo_t BxOpcodeGroupAVX256_0f11[3] = {
static const BxOpcodeInfo_t BxOpcodeGroupAVX128_0f12[3] = {
/* 66 */ { 0, BX_IA_V128_VMOVLPD_VpdHpdMq },
/* F3 */ { 0, BX_IA_VMOVSLDUP_VpsWps },
/* F2 */ { 0, BX_IA_VMOVDDUP_VpdWpd }
/* F2 */ { 0, BX_IA_V128_VMOVDDUP_VpdWpd }
};
static const BxOpcodeInfo_t BxOpcodeGroupAVX256_0f12[3] = {
/* 66 */ { 0, BX_IA_ERROR },
/* F3 */ { 0, BX_IA_VMOVSLDUP_VpsWps },
/* F2 */ { 0, BX_IA_VMOVDDUP_VpdWpd }
/* F2 */ { 0, BX_IA_V256_VMOVDDUP_VpdWpd }
};
static const BxOpcodeInfo_t BxOpcodeGroupAVX128_0f13M[3] = {

3
bochs/cpu/ia_opcodes.h
View File

@ -1565,7 +1565,8 @@ bx_define_opcode(BX_IA_V128_VMOVLPD_MqVsd, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::
bx_define_opcode(BX_IA_V128_VMOVHPD_MqVsd, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVLPD_VpdHpdMq, &BX_CPU_C::VMOVLPD_VpdHpdMq, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVHPD_VpdHpdMq, &BX_CPU_C::VMOVHPD_VpdHpdMq, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSHDUP_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VLDDQU_VdqMdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)